tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: crypto: fsl,sec-v4.0: Convert to DT schema
Convert Freescale CAAM/SEC4 binding to DT schema format. The
'fsl,sec-v4.0' and 'fsl,sec-v4.0-mon' parts are independent, so split
them into separate schema files.
Add a bunch of missing compatibles for v5.0, v5.4, etc. Drop unused
'ranges', '#address-cells', and '#size-cells' from fsl,sec-v4.0-mon nodes.
There's one DTB warning for LS1012a which has a 2nd 'reg' entry for
'fsl,sec-v4.0-rtic'. Leaving that as there is no clue as to what it is for.
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230220213334.353779-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
+417
-556
+150
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml
+150
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Freescale Secure Non-Volatile Storage (SNVS)
9
+
10
+
maintainers:
11
+
- '"Horia Geantă" <horia.geanta@nxp.com>'
12
+
- Pankaj Gupta <pankaj.gupta@nxp.com>
13
+
- Gaurav Jain <gaurav.jain@nxp.com>
14
+
15
+
description:
16
+
Node defines address range and the associated interrupt for the SNVS function.
17
+
This function monitors security state information & reports security
18
+
violations. This also included rtc, system power off and ON/OFF key.
19
+
20
+
properties:
21
+
compatible:
22
+
oneOf:
23
+
- items:
24
+
- const: fsl,sec-v4.0-mon
25
+
- const: syscon
26
+
- const: simple-mfd
27
+
- items:
28
+
- const: fsl,sec-v5.0-mon
29
+
- const: fsl,sec-v4.0-mon
30
+
- items:
31
+
- enum:
32
+
- fsl,sec-v5.3-mon
33
+
- fsl,sec-v5.4-mon
34
+
- const: fsl,sec-v5.0-mon
35
+
- const: fsl,sec-v4.0-mon
36
+
37
+
reg:
38
+
maxItems: 1
39
+
40
+
interrupts:
41
+
maxItems: 2
42
+
43
+
snvs-rtc-lp:
44
+
type: object
45
+
additionalProperties: false
46
+
description:
47
+
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
48
+
49
+
properties:
50
+
compatible:
51
+
const: fsl,sec-v4.0-mon-rtc-lp
52
+
53
+
clocks:
54
+
maxItems: 1
55
+
56
+
clock-names:
57
+
const: snvs-rtc
58
+
59
+
interrupts:
60
+
# VFxxx has only one. What is the 2nd one?
61
+
minItems: 1
62
+
maxItems: 2
63
+
64
+
regmap:
65
+
description: Parent node containing registers
66
+
$ref: /schemas/types.yaml#/definitions/phandle
67
+
68
+
offset:
69
+
description: LP register offset
70
+
$ref: /schemas/types.yaml#/definitions/uint32
71
+
default: 0x34
72
+
73
+
required:
74
+
- compatible
75
+
- interrupts
76
+
- regmap
77
+
78
+
snvs-powerkey:
79
+
type: object
80
+
additionalProperties: false
81
+
description:
82
+
The snvs-pwrkey is designed to enable POWER key function which controlled
83
+
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
84
+
system if pressed after system suspend.
85
+
86
+
properties:
87
+
compatible:
88
+
const: fsl,sec-v4.0-pwrkey
89
+
90
+
clocks:
91
+
maxItems: 1
92
+
93
+
clock-names:
94
+
const: snvs-pwrkey
95
+
96
+
interrupts:
97
+
maxItems: 1
98
+
99
+
regmap:
100
+
description: Parent node containing registers
101
+
$ref: /schemas/types.yaml#/definitions/phandle
102
+
103
+
wakeup-source: true
104
+
105
+
linux,keycode:
106
+
default: 116
107
+
108
+
required:
109
+
- compatible
110
+
- interrupts
111
+
- regmap
112
+
113
+
snvs-lpgpr:
114
+
$ref: /schemas/nvmem/snvs-lpgpr.yaml#
115
+
116
+
required:
117
+
- compatible
118
+
- reg
119
+
120
+
additionalProperties: false
121
+
122
+
examples:
123
+
- |
124
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
125
+
#include <dt-bindings/clock/imx7d-clock.h>
126
+
127
+
sec_mon: sec-mon@314000 {
128
+
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
129
+
reg = <0x314000 0x1000>;
130
+
131
+
snvs-rtc-lp {
132
+
compatible = "fsl,sec-v4.0-mon-rtc-lp";
133
+
regmap = <&sec_mon>;
134
+
offset = <0x34>;
135
+
clocks = <&clks IMX7D_SNVS_CLK>;
136
+
clock-names = "snvs-rtc";
137
+
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
138
+
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
139
+
};
140
+
141
+
snvs-powerkey {
142
+
compatible = "fsl,sec-v4.0-pwrkey";
143
+
regmap = <&sec_mon>;
144
+
clocks = <&clks IMX7D_SNVS_CLK>;
145
+
clock-names = "snvs-pwrkey";
146
+
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
147
+
linux,keycode = <116>; /* KEY_POWER */
148
+
wakeup-source;
149
+
};
150
+
};
+266
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml
+266
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Freescale SEC 4
9
+
10
+
maintainers:
11
+
- '"Horia Geantă" <horia.geanta@nxp.com>'
12
+
- Pankaj Gupta <pankaj.gupta@nxp.com>
13
+
- Gaurav Jain <gaurav.jain@nxp.com>
14
+
15
+
description: |
16
+
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
17
+
Accelerator and Assurance Module (CAAM).
18
+
19
+
SEC 4 h/w can process requests from 2 types of sources.
20
+
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
21
+
2. Job Rings (HW interface between cores & SEC 4 registers).
22
+
23
+
High Speed Data Path Configuration:
24
+
25
+
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
26
+
such as the P4080. The number of simultaneous dequeues the QI can make is
27
+
equal to the number of Descriptor Controller (DECO) engines in a particular
28
+
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
29
+
dequeue from 5 subportals simultaneously.
30
+
31
+
Job Ring Data Path Configuration:
32
+
33
+
Each JR is located on a separate 4k page, they may (or may not) be made visible
34
+
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
35
+
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
36
+
37
+
properties:
38
+
compatible:
39
+
oneOf:
40
+
- items:
41
+
- const: fsl,sec-v5.4
42
+
- const: fsl,sec-v5.0
43
+
- const: fsl,sec-v4.0
44
+
- items:
45
+
- enum:
46
+
- fsl,imx6ul-caam
47
+
- fsl,sec-v5.0
48
+
- const: fsl,sec-v4.0
49
+
- const: fsl,sec-v4.0
50
+
51
+
reg:
52
+
maxItems: 1
53
+
54
+
ranges:
55
+
maxItems: 1
56
+
57
+
'#address-cells':
58
+
enum: [1, 2]
59
+
60
+
'#size-cells':
61
+
enum: [1, 2]
62
+
63
+
clocks:
64
+
minItems: 1
65
+
maxItems: 4
66
+
67
+
clock-names:
68
+
minItems: 1
69
+
maxItems: 4
70
+
items:
71
+
enum: [mem, aclk, ipg, emi_slow]
72
+
73
+
dma-coherent: true
74
+
75
+
interrupts:
76
+
maxItems: 1
77
+
78
+
fsl,sec-era:
79
+
description: Defines the 'ERA' of the SEC device.
80
+
$ref: /schemas/types.yaml#/definitions/uint32
81
+
82
+
patternProperties:
83
+
'^jr@[0-9a-f]+$':
84
+
type: object
85
+
additionalProperties: false
86
+
description:
87
+
Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
88
+
peripheral bus for purposes of processing cryptographic descriptors. The
89
+
specified address range can be made visible to one (or more) cores. The
90
+
interrupt defined for this node is controlled within the address range of
91
+
this node.
92
+
93
+
properties:
94
+
compatible:
95
+
oneOf:
96
+
- items:
97
+
- const: fsl,sec-v5.4-job-ring
98
+
- const: fsl,sec-v5.0-job-ring
99
+
- const: fsl,sec-v4.0-job-ring
100
+
- items:
101
+
- const: fsl,sec-v5.0-job-ring
102
+
- const: fsl,sec-v4.0-job-ring
103
+
- const: fsl,sec-v4.0-job-ring
104
+
105
+
reg:
106
+
maxItems: 1
107
+
108
+
interrupts:
109
+
maxItems: 1
110
+
111
+
fsl,liodn:
112
+
description:
113
+
Specifies the LIODN to be used in conjunction with the ppid-to-liodn
114
+
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
115
+
used. Value is a 12 bit value where value is a LIODN ID for this JR.
116
+
This property is normally set by boot firmware.
117
+
$ref: /schemas/types.yaml#/definitions/uint32
118
+
maximum: 0xfff
119
+
120
+
'^rtic@[0-9a-f]+$':
121
+
type: object
122
+
additionalProperties: false
123
+
description:
124
+
Run Time Integrity Check (RTIC) Node. Defines a register space that
125
+
contains up to 5 sets of addresses and their lengths (sizes) that will be
126
+
checked at run time. After an initial hash result is calculated, these
127
+
addresses are checked by HW to monitor any change. If any memory is
128
+
modified, a Security Violation is triggered (see SNVS definition).
129
+
130
+
properties:
131
+
compatible:
132
+
oneOf:
133
+
- items:
134
+
- const: fsl,sec-v5.4-rtic
135
+
- const: fsl,sec-v5.0-rtic
136
+
- const: fsl,sec-v4.0-rtic
137
+
- const: fsl,sec-v4.0-rtic
138
+
139
+
reg:
140
+
maxItems: 1
141
+
142
+
ranges:
143
+
maxItems: 1
144
+
145
+
interrupts:
146
+
maxItems: 1
147
+
148
+
'#address-cells':
149
+
const: 1
150
+
151
+
'#size-cells':
152
+
const: 1
153
+
154
+
patternProperties:
155
+
'^rtic-[a-z]@[0-9a-f]+$':
156
+
type: object
157
+
additionalProperties: false
158
+
description:
159
+
Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
160
+
memory regions that are used to perform run-time integrity check of
161
+
memory areas that should not modified. The node defines a register
162
+
that contains the memory address & length (combined) and a second
163
+
register that contains the hash result in big endian format.
164
+
165
+
properties:
166
+
compatible:
167
+
oneOf:
168
+
- items:
169
+
- const: fsl,sec-v5.4-rtic-memory
170
+
- const: fsl,sec-v5.0-rtic-memory
171
+
- const: fsl,sec-v4.0-rtic-memory
172
+
- const: fsl,sec-v4.0-rtic-memory
173
+
174
+
reg:
175
+
items:
176
+
- description: RTIC memory address
177
+
- description: RTIC hash result
178
+
179
+
fsl,liodn:
180
+
description:
181
+
Specifies the LIODN to be used in conjunction with the
182
+
ppid-to-liodn table that specifies the PPID to LIODN mapping.
183
+
Needed if the PAMU is used. Value is a 12 bit value where value
184
+
is a LIODN ID for this JR. This property is normally set by boot
185
+
firmware.
186
+
$ref: /schemas/types.yaml#/definitions/uint32
187
+
maximum: 0xfff
188
+
189
+
fsl,rtic-region:
190
+
description:
191
+
Specifies the HW address (36 bit address) for this region
192
+
followed by the length of the HW partition to be checked;
193
+
the address is represented as a 64 bit quantity followed
194
+
by a 32 bit length.
195
+
$ref: /schemas/types.yaml#/definitions/uint32-array
196
+
197
+
required:
198
+
- compatible
199
+
- reg
200
+
- ranges
201
+
202
+
additionalProperties: false
203
+
204
+
examples:
205
+
- |
206
+
crypto@300000 {
207
+
compatible = "fsl,sec-v4.0";
208
+
#address-cells = <1>;
209
+
#size-cells = <1>;
210
+
reg = <0x300000 0x10000>;
211
+
ranges = <0 0x300000 0x10000>;
212
+
interrupts = <92 2>;
213
+
214
+
jr@1000 {
215
+
compatible = "fsl,sec-v4.0-job-ring";
216
+
reg = <0x1000 0x1000>;
217
+
interrupts = <88 2>;
218
+
};
219
+
220
+
jr@2000 {
221
+
compatible = "fsl,sec-v4.0-job-ring";
222
+
reg = <0x2000 0x1000>;
223
+
interrupts = <89 2>;
224
+
};
225
+
226
+
jr@3000 {
227
+
compatible = "fsl,sec-v4.0-job-ring";
228
+
reg = <0x3000 0x1000>;
229
+
interrupts = <90 2>;
230
+
};
231
+
232
+
jr@4000 {
233
+
compatible = "fsl,sec-v4.0-job-ring";
234
+
reg = <0x4000 0x1000>;
235
+
interrupts = <91 2>;
236
+
};
237
+
238
+
rtic@6000 {
239
+
compatible = "fsl,sec-v4.0-rtic";
240
+
#address-cells = <1>;
241
+
#size-cells = <1>;
242
+
reg = <0x6000 0x100>;
243
+
ranges = <0x0 0x6100 0xe00>;
244
+
245
+
rtic-a@0 {
246
+
compatible = "fsl,sec-v4.0-rtic-memory";
247
+
reg = <0x00 0x20>, <0x100 0x80>;
248
+
};
249
+
250
+
rtic-b@20 {
251
+
compatible = "fsl,sec-v4.0-rtic-memory";
252
+
reg = <0x20 0x20>, <0x200 0x80>;
253
+
};
254
+
255
+
rtic-c@40 {
256
+
compatible = "fsl,sec-v4.0-rtic-memory";
257
+
reg = <0x40 0x20>, <0x300 0x80>;
258
+
};
259
+
260
+
rtic-d@60 {
261
+
compatible = "fsl,sec-v4.0-rtic-memory";
262
+
reg = <0x60 0x20>, <0x500 0x80>;
263
+
};
264
+
};
265
+
};
266
+
...
-553
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
-553
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
···
1
-
=====================================================================
2
-
SEC 4 Device Tree Binding
3
-
Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4
-
5
-
CONTENTS
6
-
-Overview
7
-
-SEC 4 Node
8
-
-Job Ring Node
9
-
-Run Time Integrity Check (RTIC) Node
10
-
-Run Time Integrity Check (RTIC) Memory Node
11
-
-Secure Non-Volatile Storage (SNVS) Node
12
-
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
13
-
-Full Example
14
-
15
-
NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
16
-
Accelerator and Assurance Module (CAAM).
17
-
18
-
=====================================================================
19
-
Overview
20
-
21
-
DESCRIPTION
22
-
23
-
SEC 4 h/w can process requests from 2 types of sources.
24
-
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25
-
2. Job Rings (HW interface between cores & SEC 4 registers).
26
-
27
-
High Speed Data Path Configuration:
28
-
29
-
HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
30
-
such as the P4080. The number of simultaneous dequeues the QI can make is
31
-
equal to the number of Descriptor Controller (DECO) engines in a particular
32
-
SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
33
-
dequeue from 5 subportals simultaneously.
34
-
35
-
Job Ring Data Path Configuration:
36
-
37
-
Each JR is located on a separate 4k page, they may (or may not) be made visible
38
-
in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
39
-
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
40
-
41
-
=====================================================================
42
-
SEC 4 Node
43
-
44
-
Description
45
-
46
-
Node defines the base address of the SEC 4 block.
47
-
This block specifies the address range of all global
48
-
configuration registers for the SEC 4 block. It
49
-
also receives interrupts from the Run Time Integrity Check
50
-
(RTIC) function within the SEC 4 block.
51
-
52
-
PROPERTIES
53
-
54
-
- compatible
55
-
Usage: required
56
-
Value type: <string>
57
-
Definition: Must include "fsl,sec-v4.0"
58
-
59
-
- fsl,sec-era
60
-
Usage: optional
61
-
Value type: <u32>
62
-
Definition: A standard property. Define the 'ERA' of the SEC
63
-
device.
64
-
65
-
- #address-cells
66
-
Usage: required
67
-
Value type: <u32>
68
-
Definition: A standard property. Defines the number of cells
69
-
for representing physical addresses in child nodes.
70
-
71
-
- #size-cells
72
-
Usage: required
73
-
Value type: <u32>
74
-
Definition: A standard property. Defines the number of cells
75
-
for representing the size of physical addresses in
76
-
child nodes.
77
-
78
-
- reg
79
-
Usage: required
80
-
Value type: <prop-encoded-array>
81
-
Definition: A standard property. Specifies the physical
82
-
address and length of the SEC4 configuration registers.
83
-
registers
84
-
85
-
- ranges
86
-
Usage: required
87
-
Value type: <prop-encoded-array>
88
-
Definition: A standard property. Specifies the physical address
89
-
range of the SEC 4.0 register space (-SNVS not included). A
90
-
triplet that includes the child address, parent address, &
91
-
length.
92
-
93
-
- interrupts
94
-
Usage: required
95
-
Value type: <prop_encoded-array>
96
-
Definition: Specifies the interrupts generated by this
97
-
device. The value of the interrupts property
98
-
consists of one interrupt specifier. The format
99
-
of the specifier is defined by the binding document
100
-
describing the node's interrupt parent.
101
-
102
-
- clocks
103
-
Usage: required if SEC 4.0 requires explicit enablement of clocks
104
-
Value type: <prop_encoded-array>
105
-
Definition: A list of phandle and clock specifier pairs describing
106
-
the clocks required for enabling and disabling SEC 4.0.
107
-
108
-
- clock-names
109
-
Usage: required if SEC 4.0 requires explicit enablement of clocks
110
-
Value type: <string>
111
-
Definition: A list of clock name strings in the same order as the
112
-
clocks property.
113
-
114
-
Note: All other standard properties (see the Devicetree Specification)
115
-
are allowed but are optional.
116
-
117
-
118
-
EXAMPLE
119
-
120
-
iMX6QDL/SX requires four clocks
121
-
122
-
crypto@300000 {
123
-
compatible = "fsl,sec-v4.0";
124
-
fsl,sec-era = <2>;
125
-
#address-cells = <1>;
126
-
#size-cells = <1>;
127
-
reg = <0x300000 0x10000>;
128
-
ranges = <0 0x300000 0x10000>;
129
-
interrupt-parent = <&mpic>;
130
-
interrupts = <92 2>;
131
-
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
132
-
<&clks IMX6QDL_CLK_CAAM_ACLK>,
133
-
<&clks IMX6QDL_CLK_CAAM_IPG>,
134
-
<&clks IMX6QDL_CLK_EIM_SLOW>;
135
-
clock-names = "mem", "aclk", "ipg", "emi_slow";
136
-
};
137
-
138
-
139
-
iMX6UL does only require three clocks
140
-
141
-
crypto: crypto@2140000 {
142
-
compatible = "fsl,sec-v4.0";
143
-
#address-cells = <1>;
144
-
#size-cells = <1>;
145
-
reg = <0x2140000 0x3c000>;
146
-
ranges = <0 0x2140000 0x3c000>;
147
-
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
148
-
149
-
clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
150
-
<&clks IMX6UL_CLK_CAAM_ACLK>,
151
-
<&clks IMX6UL_CLK_CAAM_IPG>;
152
-
clock-names = "mem", "aclk", "ipg";
153
-
};
154
-
155
-
=====================================================================
156
-
Job Ring (JR) Node
157
-
158
-
Child of the crypto node defines data processing interface to SEC 4
159
-
across the peripheral bus for purposes of processing
160
-
cryptographic descriptors. The specified address
161
-
range can be made visible to one (or more) cores.
162
-
The interrupt defined for this node is controlled within
163
-
the address range of this node.
164
-
165
-
- compatible
166
-
Usage: required
167
-
Value type: <string>
168
-
Definition: Must include "fsl,sec-v4.0-job-ring"
169
-
170
-
- reg
171
-
Usage: required
172
-
Value type: <prop-encoded-array>
173
-
Definition: Specifies a two JR parameters: an offset from
174
-
the parent physical address and the length the JR registers.
175
-
176
-
- fsl,liodn
177
-
Usage: optional-but-recommended
178
-
Value type: <prop-encoded-array>
179
-
Definition:
180
-
Specifies the LIODN to be used in conjunction with
181
-
the ppid-to-liodn table that specifies the PPID to LIODN mapping.
182
-
Needed if the PAMU is used. Value is a 12 bit value
183
-
where value is a LIODN ID for this JR. This property is
184
-
normally set by boot firmware.
185
-
186
-
- interrupts
187
-
Usage: required
188
-
Value type: <prop_encoded-array>
189
-
Definition: Specifies the interrupts generated by this
190
-
device. The value of the interrupts property
191
-
consists of one interrupt specifier. The format
192
-
of the specifier is defined by the binding document
193
-
describing the node's interrupt parent.
194
-
195
-
EXAMPLE
196
-
jr@1000 {
197
-
compatible = "fsl,sec-v4.0-job-ring";
198
-
reg = <0x1000 0x1000>;
199
-
fsl,liodn = <0x081>;
200
-
interrupt-parent = <&mpic>;
201
-
interrupts = <88 2>;
202
-
};
203
-
204
-
205
-
=====================================================================
206
-
Run Time Integrity Check (RTIC) Node
207
-
208
-
Child node of the crypto node. Defines a register space that
209
-
contains up to 5 sets of addresses and their lengths (sizes) that
210
-
will be checked at run time. After an initial hash result is
211
-
calculated, these addresses are checked by HW to monitor any
212
-
change. If any memory is modified, a Security Violation is
213
-
triggered (see SNVS definition).
214
-
215
-
216
-
- compatible
217
-
Usage: required
218
-
Value type: <string>
219
-
Definition: Must include "fsl,sec-v4.0-rtic".
220
-
221
-
- #address-cells
222
-
Usage: required
223
-
Value type: <u32>
224
-
Definition: A standard property. Defines the number of cells
225
-
for representing physical addresses in child nodes. Must
226
-
have a value of 1.
227
-
228
-
- #size-cells
229
-
Usage: required
230
-
Value type: <u32>
231
-
Definition: A standard property. Defines the number of cells
232
-
for representing the size of physical addresses in
233
-
child nodes. Must have a value of 1.
234
-
235
-
- reg
236
-
Usage: required
237
-
Value type: <prop-encoded-array>
238
-
Definition: A standard property. Specifies a two parameters:
239
-
an offset from the parent physical address and the length
240
-
the SEC4 registers.
241
-
242
-
- ranges
243
-
Usage: required
244
-
Value type: <prop-encoded-array>
245
-
Definition: A standard property. Specifies the physical address
246
-
range of the SEC 4 register space (-SNVS not included). A
247
-
triplet that includes the child address, parent address, &
248
-
length.
249
-
250
-
EXAMPLE
251
-
rtic@6000 {
252
-
compatible = "fsl,sec-v4.0-rtic";
253
-
#address-cells = <1>;
254
-
#size-cells = <1>;
255
-
reg = <0x6000 0x100>;
256
-
ranges = <0x0 0x6100 0xe00>;
257
-
};
258
-
259
-
=====================================================================
260
-
Run Time Integrity Check (RTIC) Memory Node
261
-
A child node that defines individual RTIC memory regions that are used to
262
-
perform run-time integrity check of memory areas that should not modified.
263
-
The node defines a register that contains the memory address &
264
-
length (combined) and a second register that contains the hash result
265
-
in big endian format.
266
-
267
-
- compatible
268
-
Usage: required
269
-
Value type: <string>
270
-
Definition: Must include "fsl,sec-v4.0-rtic-memory".
271
-
272
-
- reg
273
-
Usage: required
274
-
Value type: <prop-encoded-array>
275
-
Definition: A standard property. Specifies two parameters:
276
-
an offset from the parent physical address and the length:
277
-
278
-
1. The location of the RTIC memory address & length registers.
279
-
2. The location RTIC hash result.
280
-
281
-
- fsl,rtic-region
282
-
Usage: optional-but-recommended
283
-
Value type: <prop-encoded-array>
284
-
Definition:
285
-
Specifies the HW address (36 bit address) for this region
286
-
followed by the length of the HW partition to be checked;
287
-
the address is represented as a 64 bit quantity followed
288
-
by a 32 bit length.
289
-
290
-
- fsl,liodn
291
-
Usage: optional-but-recommended
292
-
Value type: <prop-encoded-array>
293
-
Definition:
294
-
Specifies the LIODN to be used in conjunction with
295
-
the ppid-to-liodn table that specifies the PPID to LIODN
296
-
mapping. Needed if the PAMU is used. Value is a 12 bit value
297
-
where value is a LIODN ID for this RTIC memory region. This
298
-
property is normally set by boot firmware.
299
-
300
-
EXAMPLE
301
-
rtic-a@0 {
302
-
compatible = "fsl,sec-v4.0-rtic-memory";
303
-
reg = <0x00 0x20 0x100 0x80>;
304
-
fsl,liodn = <0x03c>;
305
-
fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
306
-
};
307
-
308
-
=====================================================================
309
-
Secure Non-Volatile Storage (SNVS) Node
310
-
311
-
Node defines address range and the associated
312
-
interrupt for the SNVS function. This function
313
-
monitors security state information & reports
314
-
security violations. This also included rtc,
315
-
system power off and ON/OFF key.
316
-
317
-
- compatible
318
-
Usage: required
319
-
Value type: <string>
320
-
Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
321
-
322
-
- reg
323
-
Usage: required
324
-
Value type: <prop-encoded-array>
325
-
Definition: A standard property. Specifies the physical
326
-
address and length of the SEC4 configuration
327
-
registers.
328
-
329
-
- #address-cells
330
-
Usage: required
331
-
Value type: <u32>
332
-
Definition: A standard property. Defines the number of cells
333
-
for representing physical addresses in child nodes. Must
334
-
have a value of 1.
335
-
336
-
- #size-cells
337
-
Usage: required
338
-
Value type: <u32>
339
-
Definition: A standard property. Defines the number of cells
340
-
for representing the size of physical addresses in
341
-
child nodes. Must have a value of 1.
342
-
343
-
- ranges
344
-
Usage: required
345
-
Value type: <prop-encoded-array>
346
-
Definition: A standard property. Specifies the physical address
347
-
range of the SNVS register space. A triplet that includes
348
-
the child address, parent address, & length.
349
-
350
-
- interrupts
351
-
Usage: optional
352
-
Value type: <prop_encoded-array>
353
-
Definition: Specifies the interrupts generated by this
354
-
device. The value of the interrupts property
355
-
consists of one interrupt specifier. The format
356
-
of the specifier is defined by the binding document
357
-
describing the node's interrupt parent.
358
-
359
-
EXAMPLE
360
-
sec_mon@314000 {
361
-
compatible = "fsl,sec-v4.0-mon", "syscon";
362
-
reg = <0x314000 0x1000>;
363
-
ranges = <0 0x314000 0x1000>;
364
-
interrupt-parent = <&mpic>;
365
-
interrupts = <93 2>;
366
-
};
367
-
368
-
=====================================================================
369
-
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
370
-
371
-
A SNVS child node that defines SNVS LP RTC.
372
-
373
-
- compatible
374
-
Usage: required
375
-
Value type: <string>
376
-
Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
377
-
378
-
- interrupts
379
-
Usage: required
380
-
Value type: <prop_encoded-array>
381
-
Definition: Specifies the interrupts generated by this
382
-
device. The value of the interrupts property
383
-
consists of one interrupt specifier. The format
384
-
of the specifier is defined by the binding document
385
-
describing the node's interrupt parent.
386
-
387
-
- regmap
388
-
Usage: required
389
-
Value type: <phandle>
390
-
Definition: this is phandle to the register map node.
391
-
392
-
- offset
393
-
Usage: option
394
-
value type: <u32>
395
-
Definition: LP register offset. default it is 0x34.
396
-
397
-
- clocks
398
-
Usage: optional, required if SNVS LP RTC requires explicit
399
-
enablement of clocks
400
-
Value type: <prop_encoded-array>
401
-
Definition: a clock specifier describing the clock required for
402
-
enabling and disabling SNVS LP RTC.
403
-
404
-
- clock-names
405
-
Usage: optional, required if SNVS LP RTC requires explicit
406
-
enablement of clocks
407
-
Value type: <string>
408
-
Definition: clock name string should be "snvs-rtc".
409
-
410
-
EXAMPLE
411
-
sec_mon_rtc_lp@1 {
412
-
compatible = "fsl,sec-v4.0-mon-rtc-lp";
413
-
interrupts = <93 2>;
414
-
regmap = <&snvs>;
415
-
offset = <0x34>;
416
-
clocks = <&clks IMX7D_SNVS_CLK>;
417
-
clock-names = "snvs-rtc";
418
-
};
419
-
420
-
=====================================================================
421
-
System ON/OFF key driver
422
-
423
-
The snvs-pwrkey is designed to enable POWER key function which controlled
424
-
by SNVS ONOFF, the driver can report the status of POWER key and wakeup
425
-
system if pressed after system suspend.
426
-
427
-
- compatible:
428
-
Usage: required
429
-
Value type: <string>
430
-
Definition: Mush include "fsl,sec-v4.0-pwrkey".
431
-
432
-
- interrupts:
433
-
Usage: required
434
-
Value type: <prop_encoded-array>
435
-
Definition: The SNVS ON/OFF interrupt number to the CPU(s).
436
-
437
-
- linux,keycode:
438
-
Usage: option
439
-
Value type: <int>
440
-
Definition: Keycode to emit, KEY_POWER by default.
441
-
442
-
- wakeup-source:
443
-
Usage: option
444
-
Value type: <boo>
445
-
Definition: Button can wake-up the system.
446
-
447
-
- regmap:
448
-
Usage: required:
449
-
Value type: <phandle>
450
-
Definition: this is phandle to the register map node.
451
-
452
-
EXAMPLE:
453
-
snvs-pwrkey@020cc000 {
454
-
compatible = "fsl,sec-v4.0-pwrkey";
455
-
regmap = <&snvs>;
456
-
interrupts = <0 4 0x4>
457
-
linux,keycode = <116>; /* KEY_POWER */
458
-
wakeup-source;
459
-
};
460
-
461
-
=====================================================================
462
-
FULL EXAMPLE
463
-
464
-
crypto: crypto@300000 {
465
-
compatible = "fsl,sec-v4.0";
466
-
#address-cells = <1>;
467
-
#size-cells = <1>;
468
-
reg = <0x300000 0x10000>;
469
-
ranges = <0 0x300000 0x10000>;
470
-
interrupt-parent = <&mpic>;
471
-
interrupts = <92 2>;
472
-
473
-
sec_jr0: jr@1000 {
474
-
compatible = "fsl,sec-v4.0-job-ring";
475
-
reg = <0x1000 0x1000>;
476
-
interrupt-parent = <&mpic>;
477
-
interrupts = <88 2>;
478
-
};
479
-
480
-
sec_jr1: jr@2000 {
481
-
compatible = "fsl,sec-v4.0-job-ring";
482
-
reg = <0x2000 0x1000>;
483
-
interrupt-parent = <&mpic>;
484
-
interrupts = <89 2>;
485
-
};
486
-
487
-
sec_jr2: jr@3000 {
488
-
compatible = "fsl,sec-v4.0-job-ring";
489
-
reg = <0x3000 0x1000>;
490
-
interrupt-parent = <&mpic>;
491
-
interrupts = <90 2>;
492
-
};
493
-
494
-
sec_jr3: jr@4000 {
495
-
compatible = "fsl,sec-v4.0-job-ring";
496
-
reg = <0x4000 0x1000>;
497
-
interrupt-parent = <&mpic>;
498
-
interrupts = <91 2>;
499
-
};
500
-
501
-
rtic@6000 {
502
-
compatible = "fsl,sec-v4.0-rtic";
503
-
#address-cells = <1>;
504
-
#size-cells = <1>;
505
-
reg = <0x6000 0x100>;
506
-
ranges = <0x0 0x6100 0xe00>;
507
-
508
-
rtic_a: rtic-a@0 {
509
-
compatible = "fsl,sec-v4.0-rtic-memory";
510
-
reg = <0x00 0x20 0x100 0x80>;
511
-
};
512
-
513
-
rtic_b: rtic-b@20 {
514
-
compatible = "fsl,sec-v4.0-rtic-memory";
515
-
reg = <0x20 0x20 0x200 0x80>;
516
-
};
517
-
518
-
rtic_c: rtic-c@40 {
519
-
compatible = "fsl,sec-v4.0-rtic-memory";
520
-
reg = <0x40 0x20 0x300 0x80>;
521
-
};
522
-
523
-
rtic_d: rtic-d@60 {
524
-
compatible = "fsl,sec-v4.0-rtic-memory";
525
-
reg = <0x60 0x20 0x500 0x80>;
526
-
};
527
-
};
528
-
};
529
-
530
-
sec_mon: sec_mon@314000 {
531
-
compatible = "fsl,sec-v4.0-mon";
532
-
reg = <0x314000 0x1000>;
533
-
ranges = <0 0x314000 0x1000>;
534
-
535
-
sec_mon_rtc_lp@34 {
536
-
compatible = "fsl,sec-v4.0-mon-rtc-lp";
537
-
regmap = <&sec_mon>;
538
-
offset = <0x34>;
539
-
interrupts = <93 2>;
540
-
clocks = <&clks IMX7D_SNVS_CLK>;
541
-
clock-names = "snvs-rtc";
542
-
};
543
-
544
-
snvs-pwrkey@020cc000 {
545
-
compatible = "fsl,sec-v4.0-pwrkey";
546
-
regmap = <&sec_mon>;
547
-
interrupts = <0 4 0x4>;
548
-
linux,keycode = <116>; /* KEY_POWER */
549
-
wakeup-source;
550
-
};
551
-
};
552
-
553
-
=====================================================================
-1
Documentation/devicetree/bindings/input/snvs-pwrkey.txt
-1
Documentation/devicetree/bindings/input/snvs-pwrkey.txt
···
1
-
See Documentation/devicetree/bindings/crypto/fsl-sec4.txt
-1
Documentation/devicetree/bindings/rtc/snvs-rtc.txt
-1
Documentation/devicetree/bindings/rtc/snvs-rtc.txt
···
1
-
See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
8100
8100
M: Gaurav Jain <gaurav.jain@nxp.com>
8101
8101
L: linux-crypto@vger.kernel.org
8102
8102
S: Maintained
8103
-
F: Documentation/devicetree/bindings/crypto/fsl-sec4.txt
8103
+
F: Documentation/devicetree/bindings/crypto/fsl,sec-v4.0*
8104
8104
F: drivers/crypto/caam/
8105
8105
8106
8106
FREESCALE COLDFIRE M5441X MMC DRIVER