phy: qcom-qmp: qserdes-com-v5: add missing registers

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add missing registers, verified against:
- msm-5.4's qcom,usb3-5nm-qmp-uni.h
- msm-5.4's qcom,usb3-5nm-qmp-combo.h

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-25-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by

Vinod Koul 3 years ago 03baa67f 1195c1da

+210 -4

2 changed files

expand all

drivers

phy

qualcomm

phy-qcom-qmp-qserdes-com-v5.h

phy-qcom-qmp-qserdes-txrx-v5.h

+59

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h

··· 7 7 #define QCOM_PHY_QMP_QSERDES_COM_V5_H_ 8 8 9 9 /* Only for QMP V5 PHY - QSERDES COM registers */ 10 + #define QSERDES_V5_COM_ATB_SEL1 0x000 11 + #define QSERDES_V5_COM_ATB_SEL2 0x004 12 + #define QSERDES_V5_COM_FREQ_UPDATE 0x008 13 + #define QSERDES_V5_COM_BG_TIMER 0x00c 10 14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 15 + #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 16 + #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 11 17 #define QSERDES_V5_COM_SSC_PER1 0x01c 12 18 #define QSERDES_V5_COM_SSC_PER2 0x020 13 19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 14 20 #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 21 + #define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c 15 22 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 16 23 #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 24 + #define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 25 + #define QSERDES_V5_COM_POST_DIV 0x03c 26 + #define QSERDES_V5_COM_POST_DIV_MUX 0x040 17 27 #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 18 28 #define QSERDES_V5_COM_CLK_ENABLE1 0x048 29 + #define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c 19 30 #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 31 + #define QSERDES_V5_COM_PLL_EN 0x054 20 32 #define QSERDES_V5_COM_PLL_IVCO 0x058 33 + #define QSERDES_V5_COM_CMN_IETRIM 0x05c 34 + #define QSERDES_V5_COM_CMN_IPTRIM 0x060 35 + #define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 36 + #define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 37 + #define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c 38 + #define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 21 39 #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 22 40 #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 23 41 #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 24 42 #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 25 43 #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 26 44 #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 45 + #define QSERDES_V5_COM_PLL_CNTRL 0x08c 46 + #define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 27 47 #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 48 + #define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 49 + #define QSERDES_V5_COM_RESETSM_CNTRL 0x09c 50 + #define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 28 51 #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 29 52 #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 30 53 #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac ··· 55 32 #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 56 33 #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 57 34 #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 35 + #define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 58 36 #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 37 + #define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 59 38 #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 60 39 #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 61 40 #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 62 41 #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 63 42 #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 64 43 #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 44 + #define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 45 + #define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 46 + #define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 47 + #define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 48 + #define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 49 + #define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 50 + #define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc 51 + #define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 52 + #define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 53 + #define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 65 54 #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 66 55 #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 67 56 #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 68 57 #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 69 58 #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 59 + #define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 70 60 #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 61 + #define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 62 + #define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c 63 + #define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 64 + #define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 65 + #define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 66 + #define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c 67 + #define QSERDES_V5_COM_CMN_STATUS 0x140 68 + #define QSERDES_V5_COM_RESET_SM_STATUS 0x144 69 + #define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 70 + #define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c 71 + #define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 71 72 #define QSERDES_V5_COM_CLK_SELECT 0x154 72 73 #define QSERDES_V5_COM_HSCLK_SEL 0x158 73 74 #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 75 + #define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 76 + #define QSERDES_V5_COM_PLL_ANALOG 0x164 74 77 #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 75 78 #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 79 + #define QSERDES_V5_COM_SW_RESET 0x170 76 80 #define QSERDES_V5_COM_CORE_CLK_EN 0x174 81 + #define QSERDES_V5_COM_C_READY_STATUS 0x178 77 82 #define QSERDES_V5_COM_CMN_CONFIG 0x17c 83 + #define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 84 + #define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 85 + #define QSERDES_V5_COM_DEBUG_BUS0 0x188 86 + #define QSERDES_V5_COM_DEBUG_BUS1 0x18c 87 + #define QSERDES_V5_COM_DEBUG_BUS2 0x190 88 + #define QSERDES_V5_COM_DEBUG_BUS3 0x194 89 + #define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 78 90 #define QSERDES_V5_COM_CMN_MISC1 0x19c 79 91 #define QSERDES_V5_COM_CMN_MODE 0x1a0 80 92 #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 ··· 119 61 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 120 62 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 121 63 #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 64 + #define QSERDES_V5_COM_RESERVED_1 0x1c0 122 65 123 66 #endif

+151 -4

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h

··· 8 8 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ 9 9 10 10 /* Only for QMP V5 PHY - TX registers */ 11 + #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 + #define QSERDES_V5_TX_BIST_INVERT 0x004 13 + #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 + #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 + #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 + #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 + #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 + #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 + #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 + #define QSERDES_V5_TX_TX_BAND 0x024 21 + #define QSERDES_V5_TX_SLEW_CNTL 0x028 22 + #define QSERDES_V5_TX_INTERFACE_SELECT 0x02c 23 + #define QSERDES_V5_TX_LPB_EN 0x030 11 24 #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 12 25 #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 13 26 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c 14 27 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 28 + #define QSERDES_V5_TX_PERL_LENGTH1 0x044 29 + #define QSERDES_V5_TX_PERL_LENGTH2 0x048 30 + #define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c 31 + #define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 32 + #define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 33 + #define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 34 + #define QSERDES_V5_TX_TX_POL_INV 0x05c 35 + #define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 36 + #define QSERDES_V5_TX_BIST_PATTERN1 0x064 37 + #define QSERDES_V5_TX_BIST_PATTERN2 0x068 38 + #define QSERDES_V5_TX_BIST_PATTERN3 0x06c 39 + #define QSERDES_V5_TX_BIST_PATTERN4 0x070 40 + #define QSERDES_V5_TX_BIST_PATTERN5 0x074 41 + #define QSERDES_V5_TX_BIST_PATTERN6 0x078 42 + #define QSERDES_V5_TX_BIST_PATTERN7 0x07c 43 + #define QSERDES_V5_TX_BIST_PATTERN8 0x080 15 44 #define QSERDES_V5_TX_LANE_MODE_1 0x084 16 45 #define QSERDES_V5_TX_LANE_MODE_2 0x088 17 46 #define QSERDES_V5_TX_LANE_MODE_3 0x08c 18 47 #define QSERDES_V5_TX_LANE_MODE_4 0x090 19 48 #define QSERDES_V5_TX_LANE_MODE_5 0x094 49 + #define QSERDES_V5_TX_ATB_SEL1 0x098 50 + #define QSERDES_V5_TX_ATB_SEL2 0x09c 51 + #define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 20 52 #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 53 + #define QSERDES_V5_TX_PRBS_SEED1 0x0a8 54 + #define QSERDES_V5_TX_PRBS_SEED2 0x0ac 55 + #define QSERDES_V5_TX_PRBS_SEED3 0x0b0 56 + #define QSERDES_V5_TX_PRBS_SEED4 0x0b4 57 + #define QSERDES_V5_TX_RESET_GEN 0x0b8 58 + #define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc 21 59 #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 60 + #define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 61 + #define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 62 + #define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc 63 + #define QSERDES_V5_TX_BIST_STATUS 0x0d0 64 + #define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 65 + #define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 66 + #define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc 67 + #define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 22 68 #define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 23 - #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 24 - #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 25 - #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 26 - #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 69 + #define QSERDES_V5_TX_PRE_EMPH 0x0e8 70 + #define QSERDES_V5_TX_SW_RESET 0x0ec 71 + #define QSERDES_V5_TX_DCC_OFFSET 0x0f0 72 + #define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 73 + #define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 74 + #define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc 75 + #define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 76 + #define QSERDES_V5_TX_DEBUG_BUS0 0x104 77 + #define QSERDES_V5_TX_DEBUG_BUS1 0x108 78 + #define QSERDES_V5_TX_DEBUG_BUS2 0x10c 79 + #define QSERDES_V5_TX_DEBUG_BUS3 0x110 80 + #define QSERDES_V5_TX_READ_EQCODE 0x114 81 + #define QSERDES_V5_TX_READ_OFFSETCODE 0x118 82 + #define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c 83 + #define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 84 + #define QSERDES_V5_TX_VGA_READ_CODE 0x124 85 + #define QSERDES_V5_TX_VTH_READ_CODE 0x128 86 + #define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c 87 + #define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 88 + #define QSERDES_V5_TX_IDAC_STATUS_I 0x134 89 + #define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 90 + #define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c 91 + #define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 92 + #define QSERDES_V5_TX_IDAC_STATUS_A 0x144 93 + #define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 94 + #define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c 95 + #define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 96 + #define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 97 + #define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 98 + #define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c 27 99 28 100 /* Only for QMP V5 PHY - RX registers */ 101 + #define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 102 + #define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 29 103 #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 104 + #define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c 105 + #define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 30 106 #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 107 + #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 108 + #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c 109 + #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 110 + #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 111 + #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 112 + #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c 31 113 #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 32 114 #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 115 + #define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 33 116 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 34 117 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 35 118 #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 ··· 121 38 #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 122 39 #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 123 40 #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 41 + #define QSERDES_V5_RX_AUX_CONTROL 0x05c 124 42 #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 125 43 #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 126 44 #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 45 + #define QSERDES_V5_RX_AC_JTAG_INITP 0x06c 46 + #define QSERDES_V5_RX_AC_JTAG_INITN 0x070 47 + #define QSERDES_V5_RX_AC_JTAG_LVL 0x074 127 48 #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 49 + #define QSERDES_V5_RX_AC_JTAG_RESET 0x07c 128 50 #define QSERDES_V5_RX_RX_TERM_BW 0x080 51 + #define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 52 + #define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 53 + #define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c 54 + #define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 55 + #define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 56 + #define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 57 + #define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c 58 + #define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 59 + #define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 60 + #define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 61 + #define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac 62 + #define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 63 + #define QSERDES_V5_RX_DFE_1 0x0b4 64 + #define QSERDES_V5_RX_DFE_2 0x0b8 65 + #define QSERDES_V5_RX_DFE_3 0x0bc 66 + #define QSERDES_V5_RX_DFE_4 0x0c0 67 + #define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 68 + #define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 129 69 #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 70 + #define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 130 71 #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 131 72 #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 132 73 #define QSERDES_V5_RX_GM_CAL 0x0dc 74 + #define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 75 + #define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 133 76 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 134 77 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 135 78 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 ··· 163 54 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 164 55 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 165 56 #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 57 + #define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 58 + #define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 59 + #define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c 166 60 #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 167 61 #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 168 62 #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 ··· 173 61 #define QSERDES_V5_RX_SIGDET_LVL 0x120 174 62 #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 175 63 #define QSERDES_V5_RX_RX_BAND 0x128 64 + #define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c 65 + #define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 66 + #define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 67 + #define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 68 + #define QSERDES_V5_RX_SJ_AMP1 0x13c 69 + #define QSERDES_V5_RX_SJ_AMP2 0x140 70 + #define QSERDES_V5_RX_SJ_PER1 0x144 71 + #define QSERDES_V5_RX_SJ_PER2 0x148 72 + #define QSERDES_V5_RX_PPM_OFFSET1 0x14c 73 + #define QSERDES_V5_RX_PPM_OFFSET2 0x150 74 + #define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 75 + #define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 176 76 #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 177 77 #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 178 78 #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 ··· 200 76 #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 201 77 #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 202 78 #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 79 + #define QSERDES_V5_RX_PHPRE_CTRL 0x198 80 + #define QSERDES_V5_RX_PHPRE_INITVAL 0x19c 203 81 #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 204 82 #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 205 83 #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 84 + #define QSERDES_V5_RX_DCC_CTRL2 0x1ac 206 85 #define QSERDES_V5_RX_VTH_CODE 0x1b0 86 + #define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 87 + #define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 88 + #define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc 89 + #define QSERDES_V5_RX_PI_CTRL1 0x1c0 90 + #define QSERDES_V5_RX_PI_CTRL2 0x1c4 91 + #define QSERDES_V5_RX_PI_QUAD 0x1c8 92 + #define QSERDES_V5_RX_IDATA1 0x1cc 93 + #define QSERDES_V5_RX_IDATA2 0x1d0 94 + #define QSERDES_V5_RX_AUX_DATA1 0x1d4 95 + #define QSERDES_V5_RX_AUX_DATA2 0x1d8 96 + #define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc 97 + #define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 98 + #define QSERDES_V5_RX_RX_SIGDET 0x1e4 99 + #define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8 100 + 101 + /* Only for QMP V5 UFS ? */ 102 + #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 103 + #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 104 + #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 105 + #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 207 106 208 107 #endif