tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc/tegra: fuse: Rename core_* to soc_*
There's a mixture of core_* and soc_* prefixes for variables storing
information related to the VDD_CORE rail. Choose one (soc_*) and use it
more consistently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
+45
-45
+4
-4
drivers/soc/tegra/fuse/fuse-tegra.c
+4
-4
drivers/soc/tegra/fuse/fuse-tegra.c
···
304
304
305
305
fuse->soc->init(fuse);
306
306
307
-
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
307
+
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
308
308
tegra_revision_name[tegra_sku_info.revision],
309
309
tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
310
-
tegra_sku_info.core_process_id);
311
-
pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
312
-
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
310
+
tegra_sku_info.soc_process_id);
311
+
pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
312
+
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
313
313
314
314
return 0;
315
315
}
+1
-1
drivers/soc/tegra/fuse/fuse-tegra20.c
+1
-1
drivers/soc/tegra/fuse/fuse-tegra20.c
···
143
143
randomness[1] = tegra_read_straps();
144
144
randomness[2] = tegra_read_chipid();
145
145
randomness[3] = tegra_sku_info.cpu_process_id << 16;
146
-
randomness[3] |= tegra_sku_info.core_process_id;
146
+
randomness[3] |= tegra_sku_info.soc_process_id;
147
147
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
148
148
randomness[4] |= tegra_sku_info.soc_speedo_id;
149
149
randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
+1
-1
drivers/soc/tegra/fuse/fuse-tegra30.c
+1
-1
drivers/soc/tegra/fuse/fuse-tegra30.c
···
78
78
randomness[1] = tegra_read_straps();
79
79
randomness[2] = tegra_read_chipid();
80
80
randomness[3] = tegra_sku_info.cpu_process_id << 16;
81
-
randomness[3] |= tegra_sku_info.core_process_id;
81
+
randomness[3] |= tegra_sku_info.soc_process_id;
82
82
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
83
83
randomness[4] |= tegra_sku_info.soc_speedo_id;
84
84
randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
+8
-8
drivers/soc/tegra/fuse/speedo-tegra114.c
+8
-8
drivers/soc/tegra/fuse/speedo-tegra114.c
···
22
22
23
23
#include "fuse.h"
24
24
25
-
#define CORE_PROCESS_CORNERS 2
25
+
#define SOC_PROCESS_CORNERS 2
26
26
#define CPU_PROCESS_CORNERS 2
27
27
28
28
enum {
···
31
31
THRESHOLD_INDEX_COUNT,
32
32
};
33
33
34
-
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
34
+
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
35
35
{1123, UINT_MAX},
36
36
{0, UINT_MAX},
37
37
};
···
84
84
void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
85
85
{
86
86
u32 cpu_speedo_val;
87
-
u32 core_speedo_val;
87
+
u32 soc_speedo_val;
88
88
int threshold;
89
89
int i;
90
90
91
91
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
92
92
THRESHOLD_INDEX_COUNT);
93
-
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
93
+
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
94
94
THRESHOLD_INDEX_COUNT);
95
95
96
96
rev_sku_to_speedo_ids(sku_info, &threshold);
97
97
98
98
cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
99
-
core_speedo_val = tegra_fuse_read_early(0x134);
99
+
soc_speedo_val = tegra_fuse_read_early(0x134);
100
100
101
101
for (i = 0; i < CPU_PROCESS_CORNERS; i++)
102
102
if (cpu_speedo_val < cpu_process_speedos[threshold][i])
103
103
break;
104
104
sku_info->cpu_process_id = i;
105
105
106
-
for (i = 0; i < CORE_PROCESS_CORNERS; i++)
107
-
if (core_speedo_val < core_process_speedos[threshold][i])
106
+
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
107
+
if (soc_speedo_val < soc_process_speedos[threshold][i])
108
108
break;
109
-
sku_info->core_process_id = i;
109
+
sku_info->soc_process_id = i;
110
110
}
+6
-6
drivers/soc/tegra/fuse/speedo-tegra124.c
+6
-6
drivers/soc/tegra/fuse/speedo-tegra124.c
···
24
24
25
25
#define CPU_PROCESS_CORNERS 2
26
26
#define GPU_PROCESS_CORNERS 2
27
-
#define CORE_PROCESS_CORNERS 2
27
+
#define SOC_PROCESS_CORNERS 2
28
28
29
29
#define FUSE_CPU_SPEEDO_0 0x14
30
30
#define FUSE_CPU_SPEEDO_1 0x2c
···
53
53
{0, UINT_MAX},
54
54
};
55
55
56
-
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
56
+
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
57
57
{2101, UINT_MAX},
58
58
{0, UINT_MAX},
59
59
};
···
119
119
THRESHOLD_INDEX_COUNT);
120
120
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
121
121
THRESHOLD_INDEX_COUNT);
122
-
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
122
+
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
123
123
THRESHOLD_INDEX_COUNT);
124
124
125
125
cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
···
157
157
break;
158
158
sku_info->cpu_process_id = i;
159
159
160
-
for (i = 0; i < CORE_PROCESS_CORNERS; i++)
160
+
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
161
161
if (soc_speedo_0_value <
162
-
core_process_speedos[threshold][i])
162
+
soc_process_speedos[threshold][i])
163
163
break;
164
-
sku_info->core_process_id = i;
164
+
sku_info->soc_process_id = i;
165
165
166
166
pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
167
167
sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
+11
-11
drivers/soc/tegra/fuse/speedo-tegra20.c
+11
-11
drivers/soc/tegra/fuse/speedo-tegra20.c
···
28
28
#define CPU_SPEEDO_REDUND_MSBIT 39
29
29
#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
30
30
31
-
#define CORE_SPEEDO_LSBIT 40
32
-
#define CORE_SPEEDO_MSBIT 47
33
-
#define CORE_SPEEDO_REDUND_LSBIT 48
34
-
#define CORE_SPEEDO_REDUND_MSBIT 55
35
-
#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
31
+
#define SOC_SPEEDO_LSBIT 40
32
+
#define SOC_SPEEDO_MSBIT 47
33
+
#define SOC_SPEEDO_REDUND_LSBIT 48
34
+
#define SOC_SPEEDO_REDUND_MSBIT 55
35
+
#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
36
36
37
37
#define SPEEDO_MULT 4
38
38
···
56
56
{316, 331, 383, UINT_MAX},
57
57
};
58
58
59
-
static const u32 __initconst core_process_speedos[][PROCESS_CORNERS_NUM] = {
59
+
static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
60
60
{165, 195, 224, UINT_MAX},
61
61
{165, 195, 224, UINT_MAX},
62
62
{165, 195, 224, UINT_MAX},
···
69
69
int i;
70
70
71
71
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
72
-
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
72
+
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
73
73
74
74
if (SPEEDO_ID_SELECT_0(sku_info->revision))
75
75
sku_info->soc_speedo_id = SPEEDO_ID_0;
···
94
94
sku_info->cpu_process_id = i;
95
95
96
96
val = 0;
97
-
for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
97
+
for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
98
98
reg = tegra_fuse_read_spare(i) |
99
-
tegra_fuse_read_spare(i + CORE_SPEEDO_REDUND_OFFS);
99
+
tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
100
100
val = (val << 1) | (reg & 0x1);
101
101
}
102
102
val = val * SPEEDO_MULT;
103
103
pr_debug("Core speedo value %u\n", val);
104
104
105
105
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
106
-
if (val <= core_process_speedos[sku_info->soc_speedo_id][i])
106
+
if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
107
107
break;
108
108
}
109
-
sku_info->core_process_id = i;
109
+
sku_info->soc_process_id = i;
110
110
}
+13
-13
drivers/soc/tegra/fuse/speedo-tegra30.c
+13
-13
drivers/soc/tegra/fuse/speedo-tegra30.c
···
22
22
23
23
#include "fuse.h"
24
24
25
-
#define CORE_PROCESS_CORNERS 1
25
+
#define SOC_PROCESS_CORNERS 1
26
26
#define CPU_PROCESS_CORNERS 6
27
27
28
28
#define FUSE_SPEEDO_CALIB_0 0x14
···
54
54
THRESHOLD_INDEX_COUNT,
55
55
};
56
56
57
-
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
57
+
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
58
58
{180},
59
59
{170},
60
60
{195},
···
246
246
void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
247
247
{
248
248
u32 cpu_speedo_val;
249
-
u32 core_speedo_val;
249
+
u32 soc_speedo_val;
250
250
int i;
251
251
252
252
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
253
253
THRESHOLD_INDEX_COUNT);
254
-
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
254
+
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
255
255
THRESHOLD_INDEX_COUNT);
256
256
257
257
258
258
rev_sku_to_speedo_ids(sku_info);
259
-
fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
259
+
fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
260
260
pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
261
-
pr_debug("Tegra Core speedo value %u\n", core_speedo_val);
261
+
pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
262
262
263
263
for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
264
264
if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
···
273
273
sku_info->cpu_speedo_id = 1;
274
274
}
275
275
276
-
for (i = 0; i < CORE_PROCESS_CORNERS; i++) {
277
-
if (core_speedo_val < core_process_speedos[threshold_index][i])
276
+
for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
277
+
if (soc_speedo_val < soc_process_speedos[threshold_index][i])
278
278
break;
279
279
}
280
-
sku_info->core_process_id = i - 1;
280
+
sku_info->soc_process_id = i - 1;
281
281
282
-
if (sku_info->core_process_id == -1) {
283
-
pr_warn("Tegra CORE speedo value %3d out of range",
284
-
core_speedo_val);
285
-
sku_info->core_process_id = 0;
282
+
if (sku_info->soc_process_id == -1) {
283
+
pr_warn("Tegra SoC speedo value %3d out of range",
284
+
soc_speedo_val);
285
+
sku_info->soc_process_id = 0;
286
286
sku_info->soc_speedo_id = 1;
287
287
}
288
288
}