Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

crypto: omap - Use new crypto_engine_op interface

Use the new crypto_engine_op interface where the callback is stored
in the algorithm object.

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

+365 -340
+12 -13
drivers/crypto/omap-aes-gcm.c
··· 7 7 * Copyright (c) 2016 Texas Instruments Incorporated 8 8 */ 9 9 10 - #include <linux/errno.h> 11 - #include <linux/scatterlist.h> 12 - #include <linux/dma-mapping.h> 13 - #include <linux/dmaengine.h> 14 - #include <linux/omap-dma.h> 15 - #include <linux/interrupt.h> 16 - #include <linux/pm_runtime.h> 17 10 #include <crypto/aes.h> 11 + #include <crypto/engine.h> 18 12 #include <crypto/gcm.h> 13 + #include <crypto/internal/aead.h> 19 14 #include <crypto/scatterwalk.h> 20 15 #include <crypto/skcipher.h> 21 - #include <crypto/internal/aead.h> 16 + #include <linux/errno.h> 17 + #include <linux/dma-mapping.h> 18 + #include <linux/dmaengine.h> 19 + #include <linux/interrupt.h> 20 + #include <linux/kernel.h> 21 + #include <linux/omap-dma.h> 22 + #include <linux/pm_runtime.h> 23 + #include <linux/scatterlist.h> 24 + #include <linux/string.h> 22 25 23 26 #include "omap-crypto.h" 24 27 #include "omap-aes.h" ··· 357 354 return crypto_rfc4106_check_authsize(authsize); 358 355 } 359 356 360 - static int omap_aes_gcm_crypt_req(struct crypto_engine *engine, void *areq) 357 + int omap_aes_gcm_crypt_req(struct crypto_engine *engine, void *areq) 361 358 { 362 359 struct aead_request *req = container_of(areq, struct aead_request, 363 360 base); ··· 382 379 383 380 int omap_aes_gcm_cra_init(struct crypto_aead *tfm) 384 381 { 385 - struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); 386 - 387 - ctx->enginectx.op.do_one_request = omap_aes_gcm_crypt_req; 388 - 389 382 crypto_aead_set_reqsize(tfm, sizeof(struct omap_aes_reqctx)); 390 383 391 384 return 0;
+112 -98
drivers/crypto/omap-aes.c
··· 33 33 #include <linux/platform_device.h> 34 34 #include <linux/pm_runtime.h> 35 35 #include <linux/scatterlist.h> 36 + #include <linux/string.h> 36 37 37 38 #include "omap-crypto.h" 38 39 #include "omap-aes.h" ··· 639 638 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) + 640 639 crypto_skcipher_reqsize(blk)); 641 640 642 - ctx->enginectx.op.do_one_request = omap_aes_crypt_req; 643 - 644 641 return 0; 645 642 } 646 643 ··· 654 655 655 656 /* ********************** ALGS ************************************ */ 656 657 657 - static struct skcipher_alg algs_ecb_cbc[] = { 658 + static struct skcipher_engine_alg algs_ecb_cbc[] = { 658 659 { 659 - .base.cra_name = "ecb(aes)", 660 - .base.cra_driver_name = "ecb-aes-omap", 661 - .base.cra_priority = 300, 662 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 663 - CRYPTO_ALG_ASYNC | 664 - CRYPTO_ALG_NEED_FALLBACK, 665 - .base.cra_blocksize = AES_BLOCK_SIZE, 666 - .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 667 - .base.cra_module = THIS_MODULE, 660 + .base = { 661 + .base.cra_name = "ecb(aes)", 662 + .base.cra_driver_name = "ecb-aes-omap", 663 + .base.cra_priority = 300, 664 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 665 + CRYPTO_ALG_ASYNC | 666 + CRYPTO_ALG_NEED_FALLBACK, 667 + .base.cra_blocksize = AES_BLOCK_SIZE, 668 + .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 669 + .base.cra_module = THIS_MODULE, 668 670 669 - .min_keysize = AES_MIN_KEY_SIZE, 670 - .max_keysize = AES_MAX_KEY_SIZE, 671 - .setkey = omap_aes_setkey, 672 - .encrypt = omap_aes_ecb_encrypt, 673 - .decrypt = omap_aes_ecb_decrypt, 674 - .init = omap_aes_init_tfm, 675 - .exit = omap_aes_exit_tfm, 671 + .min_keysize = AES_MIN_KEY_SIZE, 672 + .max_keysize = AES_MAX_KEY_SIZE, 673 + .setkey = omap_aes_setkey, 674 + .encrypt = omap_aes_ecb_encrypt, 675 + .decrypt = omap_aes_ecb_decrypt, 676 + .init = omap_aes_init_tfm, 677 + .exit = omap_aes_exit_tfm, 678 + }, 679 + .op.do_one_request = omap_aes_crypt_req, 676 680 }, 677 681 { 678 - .base.cra_name = "cbc(aes)", 679 - .base.cra_driver_name = "cbc-aes-omap", 680 - .base.cra_priority = 300, 681 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 682 - CRYPTO_ALG_ASYNC | 683 - CRYPTO_ALG_NEED_FALLBACK, 684 - .base.cra_blocksize = AES_BLOCK_SIZE, 685 - .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 686 - .base.cra_module = THIS_MODULE, 682 + .base = { 683 + .base.cra_name = "cbc(aes)", 684 + .base.cra_driver_name = "cbc-aes-omap", 685 + .base.cra_priority = 300, 686 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 687 + CRYPTO_ALG_ASYNC | 688 + CRYPTO_ALG_NEED_FALLBACK, 689 + .base.cra_blocksize = AES_BLOCK_SIZE, 690 + .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 691 + .base.cra_module = THIS_MODULE, 687 692 688 - .min_keysize = AES_MIN_KEY_SIZE, 689 - .max_keysize = AES_MAX_KEY_SIZE, 690 - .ivsize = AES_BLOCK_SIZE, 691 - .setkey = omap_aes_setkey, 692 - .encrypt = omap_aes_cbc_encrypt, 693 - .decrypt = omap_aes_cbc_decrypt, 694 - .init = omap_aes_init_tfm, 695 - .exit = omap_aes_exit_tfm, 693 + .min_keysize = AES_MIN_KEY_SIZE, 694 + .max_keysize = AES_MAX_KEY_SIZE, 695 + .ivsize = AES_BLOCK_SIZE, 696 + .setkey = omap_aes_setkey, 697 + .encrypt = omap_aes_cbc_encrypt, 698 + .decrypt = omap_aes_cbc_decrypt, 699 + .init = omap_aes_init_tfm, 700 + .exit = omap_aes_exit_tfm, 701 + }, 702 + .op.do_one_request = omap_aes_crypt_req, 696 703 } 697 704 }; 698 705 699 - static struct skcipher_alg algs_ctr[] = { 706 + static struct skcipher_engine_alg algs_ctr[] = { 700 707 { 701 - .base.cra_name = "ctr(aes)", 702 - .base.cra_driver_name = "ctr-aes-omap", 703 - .base.cra_priority = 300, 704 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 705 - CRYPTO_ALG_ASYNC | 706 - CRYPTO_ALG_NEED_FALLBACK, 707 - .base.cra_blocksize = 1, 708 - .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 709 - .base.cra_module = THIS_MODULE, 708 + .base = { 709 + .base.cra_name = "ctr(aes)", 710 + .base.cra_driver_name = "ctr-aes-omap", 711 + .base.cra_priority = 300, 712 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 713 + CRYPTO_ALG_ASYNC | 714 + CRYPTO_ALG_NEED_FALLBACK, 715 + .base.cra_blocksize = 1, 716 + .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 717 + .base.cra_module = THIS_MODULE, 710 718 711 - .min_keysize = AES_MIN_KEY_SIZE, 712 - .max_keysize = AES_MAX_KEY_SIZE, 713 - .ivsize = AES_BLOCK_SIZE, 714 - .setkey = omap_aes_setkey, 715 - .encrypt = omap_aes_ctr_encrypt, 716 - .decrypt = omap_aes_ctr_decrypt, 717 - .init = omap_aes_init_tfm, 718 - .exit = omap_aes_exit_tfm, 719 + .min_keysize = AES_MIN_KEY_SIZE, 720 + .max_keysize = AES_MAX_KEY_SIZE, 721 + .ivsize = AES_BLOCK_SIZE, 722 + .setkey = omap_aes_setkey, 723 + .encrypt = omap_aes_ctr_encrypt, 724 + .decrypt = omap_aes_ctr_decrypt, 725 + .init = omap_aes_init_tfm, 726 + .exit = omap_aes_exit_tfm, 727 + }, 728 + .op.do_one_request = omap_aes_crypt_req, 719 729 } 720 730 }; 721 731 ··· 735 727 }, 736 728 }; 737 729 738 - static struct aead_alg algs_aead_gcm[] = { 730 + static struct aead_engine_alg algs_aead_gcm[] = { 739 731 { 740 732 .base = { 741 - .cra_name = "gcm(aes)", 742 - .cra_driver_name = "gcm-aes-omap", 743 - .cra_priority = 300, 744 - .cra_flags = CRYPTO_ALG_ASYNC | 745 - CRYPTO_ALG_KERN_DRIVER_ONLY, 746 - .cra_blocksize = 1, 747 - .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 748 - .cra_alignmask = 0xf, 749 - .cra_module = THIS_MODULE, 733 + .base = { 734 + .cra_name = "gcm(aes)", 735 + .cra_driver_name = "gcm-aes-omap", 736 + .cra_priority = 300, 737 + .cra_flags = CRYPTO_ALG_ASYNC | 738 + CRYPTO_ALG_KERN_DRIVER_ONLY, 739 + .cra_blocksize = 1, 740 + .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 741 + .cra_alignmask = 0xf, 742 + .cra_module = THIS_MODULE, 743 + }, 744 + .init = omap_aes_gcm_cra_init, 745 + .ivsize = GCM_AES_IV_SIZE, 746 + .maxauthsize = AES_BLOCK_SIZE, 747 + .setkey = omap_aes_gcm_setkey, 748 + .setauthsize = omap_aes_gcm_setauthsize, 749 + .encrypt = omap_aes_gcm_encrypt, 750 + .decrypt = omap_aes_gcm_decrypt, 750 751 }, 751 - .init = omap_aes_gcm_cra_init, 752 - .ivsize = GCM_AES_IV_SIZE, 753 - .maxauthsize = AES_BLOCK_SIZE, 754 - .setkey = omap_aes_gcm_setkey, 755 - .setauthsize = omap_aes_gcm_setauthsize, 756 - .encrypt = omap_aes_gcm_encrypt, 757 - .decrypt = omap_aes_gcm_decrypt, 752 + .op.do_one_request = omap_aes_gcm_crypt_req, 758 753 }, 759 754 { 760 755 .base = { 761 - .cra_name = "rfc4106(gcm(aes))", 762 - .cra_driver_name = "rfc4106-gcm-aes-omap", 763 - .cra_priority = 300, 764 - .cra_flags = CRYPTO_ALG_ASYNC | 765 - CRYPTO_ALG_KERN_DRIVER_ONLY, 766 - .cra_blocksize = 1, 767 - .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 768 - .cra_alignmask = 0xf, 769 - .cra_module = THIS_MODULE, 756 + .base = { 757 + .cra_name = "rfc4106(gcm(aes))", 758 + .cra_driver_name = "rfc4106-gcm-aes-omap", 759 + .cra_priority = 300, 760 + .cra_flags = CRYPTO_ALG_ASYNC | 761 + CRYPTO_ALG_KERN_DRIVER_ONLY, 762 + .cra_blocksize = 1, 763 + .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 764 + .cra_alignmask = 0xf, 765 + .cra_module = THIS_MODULE, 766 + }, 767 + .init = omap_aes_gcm_cra_init, 768 + .maxauthsize = AES_BLOCK_SIZE, 769 + .ivsize = GCM_RFC4106_IV_SIZE, 770 + .setkey = omap_aes_4106gcm_setkey, 771 + .setauthsize = omap_aes_4106gcm_setauthsize, 772 + .encrypt = omap_aes_4106gcm_encrypt, 773 + .decrypt = omap_aes_4106gcm_decrypt, 770 774 }, 771 - .init = omap_aes_gcm_cra_init, 772 - .maxauthsize = AES_BLOCK_SIZE, 773 - .ivsize = GCM_RFC4106_IV_SIZE, 774 - .setkey = omap_aes_4106gcm_setkey, 775 - .setauthsize = omap_aes_4106gcm_setauthsize, 776 - .encrypt = omap_aes_4106gcm_encrypt, 777 - .decrypt = omap_aes_4106gcm_decrypt, 775 + .op.do_one_request = omap_aes_gcm_crypt_req, 778 776 }, 779 777 }; 780 778 ··· 1102 1088 { 1103 1089 struct device *dev = &pdev->dev; 1104 1090 struct omap_aes_dev *dd; 1105 - struct skcipher_alg *algp; 1106 - struct aead_alg *aalg; 1091 + struct skcipher_engine_alg *algp; 1092 + struct aead_engine_alg *aalg; 1107 1093 struct resource res; 1108 1094 int err = -ENOMEM, i, j, irq = -1; 1109 1095 u32 reg; ··· 1196 1182 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1197 1183 algp = &dd->pdata->algs_info[i].algs_list[j]; 1198 1184 1199 - pr_debug("reg alg: %s\n", algp->base.cra_name); 1185 + pr_debug("reg alg: %s\n", algp->base.base.cra_name); 1200 1186 1201 - err = crypto_register_skcipher(algp); 1187 + err = crypto_engine_register_skcipher(algp); 1202 1188 if (err) 1203 1189 goto err_algs; 1204 1190 ··· 1212 1198 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1213 1199 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1214 1200 1215 - pr_debug("reg alg: %s\n", aalg->base.cra_name); 1201 + pr_debug("reg alg: %s\n", aalg->base.base.cra_name); 1216 1202 1217 - err = crypto_register_aead(aalg); 1203 + err = crypto_engine_register_aead(aalg); 1218 1204 if (err) 1219 1205 goto err_aead_algs; 1220 1206 ··· 1232 1218 err_aead_algs: 1233 1219 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1234 1220 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1235 - crypto_unregister_aead(aalg); 1221 + crypto_engine_unregister_aead(aalg); 1236 1222 } 1237 1223 err_algs: 1238 1224 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1239 1225 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1240 - crypto_unregister_skcipher( 1226 + crypto_engine_unregister_skcipher( 1241 1227 &dd->pdata->algs_info[i].algs_list[j]); 1242 1228 1243 1229 err_engine: ··· 1259 1245 static int omap_aes_remove(struct platform_device *pdev) 1260 1246 { 1261 1247 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1262 - struct aead_alg *aalg; 1248 + struct aead_engine_alg *aalg; 1263 1249 int i, j; 1264 1250 1265 1251 spin_lock_bh(&list_lock); ··· 1268 1254 1269 1255 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1270 1256 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { 1271 - crypto_unregister_skcipher( 1257 + crypto_engine_unregister_skcipher( 1272 1258 &dd->pdata->algs_info[i].algs_list[j]); 1273 1259 dd->pdata->algs_info[i].registered--; 1274 1260 } 1275 1261 1276 1262 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1277 1263 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1278 - crypto_unregister_aead(aalg); 1264 + crypto_engine_unregister_aead(aalg); 1279 1265 dd->pdata->aead_algs_info->registered--; 1280 1266 } 1281 1267
+7 -8
drivers/crypto/omap-aes.h
··· 10 10 #define __OMAP_AES_H__ 11 11 12 12 #include <crypto/aes.h> 13 - #include <crypto/engine.h> 14 13 15 14 #define DST_MAXBURST 4 16 15 #define DMA_MIN (DST_MAXBURST * sizeof(u32)) ··· 92 93 }; 93 94 94 95 struct omap_aes_ctx { 95 - struct crypto_engine_ctx enginectx; 96 96 int keylen; 97 97 u32 key[AES_KEYSIZE_256 / sizeof(u32)]; 98 98 u8 nonce[4]; ··· 115 117 #define OMAP_AES_CACHE_SIZE 0 116 118 117 119 struct omap_aes_algs_info { 118 - struct skcipher_alg *algs_list; 119 - unsigned int size; 120 - unsigned int registered; 120 + struct skcipher_engine_alg *algs_list; 121 + unsigned int size; 122 + unsigned int registered; 121 123 }; 122 124 123 125 struct omap_aes_aead_algs { 124 - struct aead_alg *algs_list; 125 - unsigned int size; 126 - unsigned int registered; 126 + struct aead_engine_alg *algs_list; 127 + unsigned int size; 128 + unsigned int registered; 127 129 }; 128 130 129 131 struct omap_aes_pdata { ··· 216 218 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd); 217 219 void omap_aes_gcm_dma_out_callback(void *data); 218 220 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd); 221 + int omap_aes_gcm_crypt_req(struct crypto_engine *engine, void *areq); 219 222 220 223 #endif
+93 -88
drivers/crypto/omap-des.c
··· 16 16 #define prx(num) do { } while (0) 17 17 #endif 18 18 19 - #include <linux/err.h> 20 - #include <linux/module.h> 21 - #include <linux/init.h> 22 - #include <linux/errno.h> 23 - #include <linux/kernel.h> 24 - #include <linux/platform_device.h> 25 - #include <linux/scatterlist.h> 19 + #include <crypto/engine.h> 20 + #include <crypto/internal/des.h> 21 + #include <crypto/internal/skcipher.h> 22 + #include <crypto/scatterwalk.h> 26 23 #include <linux/dma-mapping.h> 27 24 #include <linux/dmaengine.h> 28 - #include <linux/pm_runtime.h> 25 + #include <linux/err.h> 26 + #include <linux/init.h> 27 + #include <linux/interrupt.h> 28 + #include <linux/io.h> 29 + #include <linux/kernel.h> 30 + #include <linux/module.h> 29 31 #include <linux/of.h> 30 32 #include <linux/of_device.h> 31 33 #include <linux/of_address.h> 32 - #include <linux/io.h> 33 - #include <linux/crypto.h> 34 - #include <linux/interrupt.h> 35 - #include <crypto/scatterwalk.h> 36 - #include <crypto/internal/des.h> 37 - #include <crypto/internal/skcipher.h> 38 - #include <crypto/algapi.h> 39 - #include <crypto/engine.h> 34 + #include <linux/platform_device.h> 35 + #include <linux/pm_runtime.h> 36 + #include <linux/scatterlist.h> 37 + #include <linux/string.h> 40 38 41 39 #include "omap-crypto.h" 42 40 ··· 81 83 #define FLAGS_OUT_DATA_ST_SHIFT 10 82 84 83 85 struct omap_des_ctx { 84 - struct crypto_engine_ctx enginectx; 85 86 struct omap_des_dev *dd; 86 87 87 88 int keylen; ··· 96 99 #define OMAP_DES_CACHE_SIZE 0 97 100 98 101 struct omap_des_algs_info { 99 - struct skcipher_alg *algs_list; 100 - unsigned int size; 101 - unsigned int registered; 102 + struct skcipher_engine_alg *algs_list; 103 + unsigned int size; 104 + unsigned int registered; 102 105 }; 103 106 104 107 struct omap_des_pdata { ··· 704 707 705 708 static int omap_des_init_tfm(struct crypto_skcipher *tfm) 706 709 { 707 - struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm); 708 - 709 710 pr_debug("enter\n"); 710 711 711 712 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx)); 712 - 713 - ctx->enginectx.op.do_one_request = omap_des_crypt_req; 714 713 715 714 return 0; 716 715 } 717 716 718 717 /* ********************** ALGS ************************************ */ 719 718 720 - static struct skcipher_alg algs_ecb_cbc[] = { 719 + static struct skcipher_engine_alg algs_ecb_cbc[] = { 721 720 { 722 - .base.cra_name = "ecb(des)", 723 - .base.cra_driver_name = "ecb-des-omap", 724 - .base.cra_priority = 300, 725 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 726 - CRYPTO_ALG_ASYNC, 727 - .base.cra_blocksize = DES_BLOCK_SIZE, 728 - .base.cra_ctxsize = sizeof(struct omap_des_ctx), 729 - .base.cra_module = THIS_MODULE, 721 + .base = { 722 + .base.cra_name = "ecb(des)", 723 + .base.cra_driver_name = "ecb-des-omap", 724 + .base.cra_priority = 300, 725 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 726 + CRYPTO_ALG_ASYNC, 727 + .base.cra_blocksize = DES_BLOCK_SIZE, 728 + .base.cra_ctxsize = sizeof(struct omap_des_ctx), 729 + .base.cra_module = THIS_MODULE, 730 730 731 - .min_keysize = DES_KEY_SIZE, 732 - .max_keysize = DES_KEY_SIZE, 733 - .setkey = omap_des_setkey, 734 - .encrypt = omap_des_ecb_encrypt, 735 - .decrypt = omap_des_ecb_decrypt, 736 - .init = omap_des_init_tfm, 731 + .min_keysize = DES_KEY_SIZE, 732 + .max_keysize = DES_KEY_SIZE, 733 + .setkey = omap_des_setkey, 734 + .encrypt = omap_des_ecb_encrypt, 735 + .decrypt = omap_des_ecb_decrypt, 736 + .init = omap_des_init_tfm, 737 + }, 738 + .op.do_one_request = omap_des_crypt_req, 737 739 }, 738 740 { 739 - .base.cra_name = "cbc(des)", 740 - .base.cra_driver_name = "cbc-des-omap", 741 - .base.cra_priority = 300, 742 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 743 - CRYPTO_ALG_ASYNC, 744 - .base.cra_blocksize = DES_BLOCK_SIZE, 745 - .base.cra_ctxsize = sizeof(struct omap_des_ctx), 746 - .base.cra_module = THIS_MODULE, 741 + .base = { 742 + .base.cra_name = "cbc(des)", 743 + .base.cra_driver_name = "cbc-des-omap", 744 + .base.cra_priority = 300, 745 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 746 + CRYPTO_ALG_ASYNC, 747 + .base.cra_blocksize = DES_BLOCK_SIZE, 748 + .base.cra_ctxsize = sizeof(struct omap_des_ctx), 749 + .base.cra_module = THIS_MODULE, 747 750 748 - .min_keysize = DES_KEY_SIZE, 749 - .max_keysize = DES_KEY_SIZE, 750 - .ivsize = DES_BLOCK_SIZE, 751 - .setkey = omap_des_setkey, 752 - .encrypt = omap_des_cbc_encrypt, 753 - .decrypt = omap_des_cbc_decrypt, 754 - .init = omap_des_init_tfm, 751 + .min_keysize = DES_KEY_SIZE, 752 + .max_keysize = DES_KEY_SIZE, 753 + .ivsize = DES_BLOCK_SIZE, 754 + .setkey = omap_des_setkey, 755 + .encrypt = omap_des_cbc_encrypt, 756 + .decrypt = omap_des_cbc_decrypt, 757 + .init = omap_des_init_tfm, 758 + }, 759 + .op.do_one_request = omap_des_crypt_req, 755 760 }, 756 761 { 757 - .base.cra_name = "ecb(des3_ede)", 758 - .base.cra_driver_name = "ecb-des3-omap", 759 - .base.cra_priority = 300, 760 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 761 - CRYPTO_ALG_ASYNC, 762 - .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 763 - .base.cra_ctxsize = sizeof(struct omap_des_ctx), 764 - .base.cra_module = THIS_MODULE, 762 + .base = { 763 + .base.cra_name = "ecb(des3_ede)", 764 + .base.cra_driver_name = "ecb-des3-omap", 765 + .base.cra_priority = 300, 766 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 767 + CRYPTO_ALG_ASYNC, 768 + .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 769 + .base.cra_ctxsize = sizeof(struct omap_des_ctx), 770 + .base.cra_module = THIS_MODULE, 765 771 766 - .min_keysize = DES3_EDE_KEY_SIZE, 767 - .max_keysize = DES3_EDE_KEY_SIZE, 768 - .setkey = omap_des3_setkey, 769 - .encrypt = omap_des_ecb_encrypt, 770 - .decrypt = omap_des_ecb_decrypt, 771 - .init = omap_des_init_tfm, 772 + .min_keysize = DES3_EDE_KEY_SIZE, 773 + .max_keysize = DES3_EDE_KEY_SIZE, 774 + .setkey = omap_des3_setkey, 775 + .encrypt = omap_des_ecb_encrypt, 776 + .decrypt = omap_des_ecb_decrypt, 777 + .init = omap_des_init_tfm, 778 + }, 779 + .op.do_one_request = omap_des_crypt_req, 772 780 }, 773 781 { 774 - .base.cra_name = "cbc(des3_ede)", 775 - .base.cra_driver_name = "cbc-des3-omap", 776 - .base.cra_priority = 300, 777 - .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 778 - CRYPTO_ALG_ASYNC, 779 - .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 780 - .base.cra_ctxsize = sizeof(struct omap_des_ctx), 781 - .base.cra_module = THIS_MODULE, 782 + .base = { 783 + .base.cra_name = "cbc(des3_ede)", 784 + .base.cra_driver_name = "cbc-des3-omap", 785 + .base.cra_priority = 300, 786 + .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 787 + CRYPTO_ALG_ASYNC, 788 + .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 789 + .base.cra_ctxsize = sizeof(struct omap_des_ctx), 790 + .base.cra_module = THIS_MODULE, 782 791 783 - .min_keysize = DES3_EDE_KEY_SIZE, 784 - .max_keysize = DES3_EDE_KEY_SIZE, 785 - .ivsize = DES3_EDE_BLOCK_SIZE, 786 - .setkey = omap_des3_setkey, 787 - .encrypt = omap_des_cbc_encrypt, 788 - .decrypt = omap_des_cbc_decrypt, 789 - .init = omap_des_init_tfm, 792 + .min_keysize = DES3_EDE_KEY_SIZE, 793 + .max_keysize = DES3_EDE_KEY_SIZE, 794 + .ivsize = DES3_EDE_BLOCK_SIZE, 795 + .setkey = omap_des3_setkey, 796 + .encrypt = omap_des_cbc_encrypt, 797 + .decrypt = omap_des_cbc_decrypt, 798 + .init = omap_des_init_tfm, 799 + }, 800 + .op.do_one_request = omap_des_crypt_req, 790 801 } 791 802 }; 792 803 ··· 952 947 { 953 948 struct device *dev = &pdev->dev; 954 949 struct omap_des_dev *dd; 955 - struct skcipher_alg *algp; 950 + struct skcipher_engine_alg *algp; 956 951 struct resource *res; 957 952 int err = -ENOMEM, i, j, irq = -1; 958 953 u32 reg; ··· 1040 1035 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1041 1036 algp = &dd->pdata->algs_info[i].algs_list[j]; 1042 1037 1043 - pr_debug("reg alg: %s\n", algp->base.cra_name); 1038 + pr_debug("reg alg: %s\n", algp->base.base.cra_name); 1044 1039 1045 - err = crypto_register_skcipher(algp); 1040 + err = crypto_engine_register_skcipher(algp); 1046 1041 if (err) 1047 1042 goto err_algs; 1048 1043 ··· 1055 1050 err_algs: 1056 1051 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1057 1052 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1058 - crypto_unregister_skcipher( 1053 + crypto_engine_unregister_skcipher( 1059 1054 &dd->pdata->algs_info[i].algs_list[j]); 1060 1055 1061 1056 err_engine: ··· 1085 1080 1086 1081 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1087 1082 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1088 - crypto_unregister_skcipher( 1083 + crypto_engine_unregister_skcipher( 1089 1084 &dd->pdata->algs_info[i].algs_list[j]); 1090 1085 1091 1086 tasklet_kill(&dd->done_task);
+141 -133
drivers/crypto/omap-sham.c
··· 13 13 14 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 15 16 + #include <crypto/engine.h> 17 + #include <crypto/hmac.h> 18 + #include <crypto/internal/hash.h> 19 + #include <crypto/scatterwalk.h> 20 + #include <crypto/sha1.h> 21 + #include <crypto/sha2.h> 16 22 #include <linux/err.h> 17 23 #include <linux/device.h> 18 - #include <linux/module.h> 19 - #include <linux/init.h> 20 - #include <linux/errno.h> 21 - #include <linux/interrupt.h> 22 - #include <linux/kernel.h> 23 - #include <linux/irq.h> 24 - #include <linux/io.h> 25 - #include <linux/platform_device.h> 26 - #include <linux/scatterlist.h> 27 24 #include <linux/dma-mapping.h> 28 25 #include <linux/dmaengine.h> 29 - #include <linux/pm_runtime.h> 26 + #include <linux/init.h> 27 + #include <linux/interrupt.h> 28 + #include <linux/io.h> 29 + #include <linux/irq.h> 30 + #include <linux/kernel.h> 31 + #include <linux/module.h> 30 32 #include <linux/of.h> 31 33 #include <linux/of_device.h> 32 34 #include <linux/of_address.h> 33 35 #include <linux/of_irq.h> 34 - #include <linux/delay.h> 35 - #include <linux/crypto.h> 36 - #include <crypto/scatterwalk.h> 37 - #include <crypto/algapi.h> 38 - #include <crypto/sha1.h> 39 - #include <crypto/sha2.h> 40 - #include <crypto/hash.h> 41 - #include <crypto/hmac.h> 42 - #include <crypto/internal/hash.h> 43 - #include <crypto/engine.h> 36 + #include <linux/platform_device.h> 37 + #include <linux/pm_runtime.h> 38 + #include <linux/scatterlist.h> 39 + #include <linux/slab.h> 40 + #include <linux/string.h> 44 41 45 42 #define MD5_DIGEST_SIZE 16 46 43 ··· 165 168 }; 166 169 167 170 struct omap_sham_ctx { 168 - struct crypto_engine_ctx enginectx; 169 171 unsigned long flags; 170 172 171 173 /* fallback stuff */ ··· 176 180 #define OMAP_SHAM_QUEUE_LENGTH 10 177 181 178 182 struct omap_sham_algs_info { 179 - struct ahash_alg *algs_list; 183 + struct ahash_engine_alg *algs_list; 180 184 unsigned int size; 181 185 unsigned int registered; 182 186 }; ··· 1349 1353 1350 1354 } 1351 1355 1352 - tctx->enginectx.op.do_one_request = omap_sham_hash_one_req; 1353 - 1354 1356 return 0; 1355 1357 } 1356 1358 ··· 1419 1425 return 0; 1420 1426 } 1421 1427 1422 - static struct ahash_alg algs_sha1_md5[] = { 1428 + static struct ahash_engine_alg algs_sha1_md5[] = { 1423 1429 { 1424 - .init = omap_sham_init, 1425 - .update = omap_sham_update, 1426 - .final = omap_sham_final, 1427 - .finup = omap_sham_finup, 1428 - .digest = omap_sham_digest, 1429 - .halg.digestsize = SHA1_DIGEST_SIZE, 1430 - .halg.base = { 1430 + .base.init = omap_sham_init, 1431 + .base.update = omap_sham_update, 1432 + .base.final = omap_sham_final, 1433 + .base.finup = omap_sham_finup, 1434 + .base.digest = omap_sham_digest, 1435 + .base.halg.digestsize = SHA1_DIGEST_SIZE, 1436 + .base.halg.base = { 1431 1437 .cra_name = "sha1", 1432 1438 .cra_driver_name = "omap-sha1", 1433 1439 .cra_priority = 400, ··· 1440 1446 .cra_module = THIS_MODULE, 1441 1447 .cra_init = omap_sham_cra_init, 1442 1448 .cra_exit = omap_sham_cra_exit, 1443 - } 1449 + }, 1450 + .op.do_one_request = omap_sham_hash_one_req, 1444 1451 }, 1445 1452 { 1446 - .init = omap_sham_init, 1447 - .update = omap_sham_update, 1448 - .final = omap_sham_final, 1449 - .finup = omap_sham_finup, 1450 - .digest = omap_sham_digest, 1451 - .halg.digestsize = MD5_DIGEST_SIZE, 1452 - .halg.base = { 1453 + .base.init = omap_sham_init, 1454 + .base.update = omap_sham_update, 1455 + .base.final = omap_sham_final, 1456 + .base.finup = omap_sham_finup, 1457 + .base.digest = omap_sham_digest, 1458 + .base.halg.digestsize = MD5_DIGEST_SIZE, 1459 + .base.halg.base = { 1453 1460 .cra_name = "md5", 1454 1461 .cra_driver_name = "omap-md5", 1455 1462 .cra_priority = 400, ··· 1463 1468 .cra_module = THIS_MODULE, 1464 1469 .cra_init = omap_sham_cra_init, 1465 1470 .cra_exit = omap_sham_cra_exit, 1466 - } 1471 + }, 1472 + .op.do_one_request = omap_sham_hash_one_req, 1467 1473 }, 1468 1474 { 1469 - .init = omap_sham_init, 1470 - .update = omap_sham_update, 1471 - .final = omap_sham_final, 1472 - .finup = omap_sham_finup, 1473 - .digest = omap_sham_digest, 1474 - .setkey = omap_sham_setkey, 1475 - .halg.digestsize = SHA1_DIGEST_SIZE, 1476 - .halg.base = { 1475 + .base.init = omap_sham_init, 1476 + .base.update = omap_sham_update, 1477 + .base.final = omap_sham_final, 1478 + .base.finup = omap_sham_finup, 1479 + .base.digest = omap_sham_digest, 1480 + .base.setkey = omap_sham_setkey, 1481 + .base.halg.digestsize = SHA1_DIGEST_SIZE, 1482 + .base.halg.base = { 1477 1483 .cra_name = "hmac(sha1)", 1478 1484 .cra_driver_name = "omap-hmac-sha1", 1479 1485 .cra_priority = 400, ··· 1488 1492 .cra_module = THIS_MODULE, 1489 1493 .cra_init = omap_sham_cra_sha1_init, 1490 1494 .cra_exit = omap_sham_cra_exit, 1491 - } 1495 + }, 1496 + .op.do_one_request = omap_sham_hash_one_req, 1492 1497 }, 1493 1498 { 1494 - .init = omap_sham_init, 1495 - .update = omap_sham_update, 1496 - .final = omap_sham_final, 1497 - .finup = omap_sham_finup, 1498 - .digest = omap_sham_digest, 1499 - .setkey = omap_sham_setkey, 1500 - .halg.digestsize = MD5_DIGEST_SIZE, 1501 - .halg.base = { 1499 + .base.init = omap_sham_init, 1500 + .base.update = omap_sham_update, 1501 + .base.final = omap_sham_final, 1502 + .base.finup = omap_sham_finup, 1503 + .base.digest = omap_sham_digest, 1504 + .base.setkey = omap_sham_setkey, 1505 + .base.halg.digestsize = MD5_DIGEST_SIZE, 1506 + .base.halg.base = { 1502 1507 .cra_name = "hmac(md5)", 1503 1508 .cra_driver_name = "omap-hmac-md5", 1504 1509 .cra_priority = 400, ··· 1513 1516 .cra_module = THIS_MODULE, 1514 1517 .cra_init = omap_sham_cra_md5_init, 1515 1518 .cra_exit = omap_sham_cra_exit, 1516 - } 1519 + }, 1520 + .op.do_one_request = omap_sham_hash_one_req, 1517 1521 } 1518 1522 }; 1519 1523 1520 1524 /* OMAP4 has some algs in addition to what OMAP2 has */ 1521 - static struct ahash_alg algs_sha224_sha256[] = { 1525 + static struct ahash_engine_alg algs_sha224_sha256[] = { 1522 1526 { 1523 - .init = omap_sham_init, 1524 - .update = omap_sham_update, 1525 - .final = omap_sham_final, 1526 - .finup = omap_sham_finup, 1527 - .digest = omap_sham_digest, 1528 - .halg.digestsize = SHA224_DIGEST_SIZE, 1529 - .halg.base = { 1527 + .base.init = omap_sham_init, 1528 + .base.update = omap_sham_update, 1529 + .base.final = omap_sham_final, 1530 + .base.finup = omap_sham_finup, 1531 + .base.digest = omap_sham_digest, 1532 + .base.halg.digestsize = SHA224_DIGEST_SIZE, 1533 + .base.halg.base = { 1530 1534 .cra_name = "sha224", 1531 1535 .cra_driver_name = "omap-sha224", 1532 1536 .cra_priority = 400, ··· 1540 1542 .cra_module = THIS_MODULE, 1541 1543 .cra_init = omap_sham_cra_init, 1542 1544 .cra_exit = omap_sham_cra_exit, 1543 - } 1545 + }, 1546 + .op.do_one_request = omap_sham_hash_one_req, 1544 1547 }, 1545 1548 { 1546 - .init = omap_sham_init, 1547 - .update = omap_sham_update, 1548 - .final = omap_sham_final, 1549 - .finup = omap_sham_finup, 1550 - .digest = omap_sham_digest, 1551 - .halg.digestsize = SHA256_DIGEST_SIZE, 1552 - .halg.base = { 1549 + .base.init = omap_sham_init, 1550 + .base.update = omap_sham_update, 1551 + .base.final = omap_sham_final, 1552 + .base.finup = omap_sham_finup, 1553 + .base.digest = omap_sham_digest, 1554 + .base.halg.digestsize = SHA256_DIGEST_SIZE, 1555 + .base.halg.base = { 1553 1556 .cra_name = "sha256", 1554 1557 .cra_driver_name = "omap-sha256", 1555 1558 .cra_priority = 400, ··· 1563 1564 .cra_module = THIS_MODULE, 1564 1565 .cra_init = omap_sham_cra_init, 1565 1566 .cra_exit = omap_sham_cra_exit, 1566 - } 1567 + }, 1568 + .op.do_one_request = omap_sham_hash_one_req, 1567 1569 }, 1568 1570 { 1569 - .init = omap_sham_init, 1570 - .update = omap_sham_update, 1571 - .final = omap_sham_final, 1572 - .finup = omap_sham_finup, 1573 - .digest = omap_sham_digest, 1574 - .setkey = omap_sham_setkey, 1575 - .halg.digestsize = SHA224_DIGEST_SIZE, 1576 - .halg.base = { 1571 + .base.init = omap_sham_init, 1572 + .base.update = omap_sham_update, 1573 + .base.final = omap_sham_final, 1574 + .base.finup = omap_sham_finup, 1575 + .base.digest = omap_sham_digest, 1576 + .base.setkey = omap_sham_setkey, 1577 + .base.halg.digestsize = SHA224_DIGEST_SIZE, 1578 + .base.halg.base = { 1577 1579 .cra_name = "hmac(sha224)", 1578 1580 .cra_driver_name = "omap-hmac-sha224", 1579 1581 .cra_priority = 400, ··· 1588 1588 .cra_module = THIS_MODULE, 1589 1589 .cra_init = omap_sham_cra_sha224_init, 1590 1590 .cra_exit = omap_sham_cra_exit, 1591 - } 1591 + }, 1592 + .op.do_one_request = omap_sham_hash_one_req, 1592 1593 }, 1593 1594 { 1594 - .init = omap_sham_init, 1595 - .update = omap_sham_update, 1596 - .final = omap_sham_final, 1597 - .finup = omap_sham_finup, 1598 - .digest = omap_sham_digest, 1599 - .setkey = omap_sham_setkey, 1600 - .halg.digestsize = SHA256_DIGEST_SIZE, 1601 - .halg.base = { 1595 + .base.init = omap_sham_init, 1596 + .base.update = omap_sham_update, 1597 + .base.final = omap_sham_final, 1598 + .base.finup = omap_sham_finup, 1599 + .base.digest = omap_sham_digest, 1600 + .base.setkey = omap_sham_setkey, 1601 + .base.halg.digestsize = SHA256_DIGEST_SIZE, 1602 + .base.halg.base = { 1602 1603 .cra_name = "hmac(sha256)", 1603 1604 .cra_driver_name = "omap-hmac-sha256", 1604 1605 .cra_priority = 400, ··· 1613 1612 .cra_module = THIS_MODULE, 1614 1613 .cra_init = omap_sham_cra_sha256_init, 1615 1614 .cra_exit = omap_sham_cra_exit, 1616 - } 1615 + }, 1616 + .op.do_one_request = omap_sham_hash_one_req, 1617 1617 }, 1618 1618 }; 1619 1619 1620 - static struct ahash_alg algs_sha384_sha512[] = { 1620 + static struct ahash_engine_alg algs_sha384_sha512[] = { 1621 1621 { 1622 - .init = omap_sham_init, 1623 - .update = omap_sham_update, 1624 - .final = omap_sham_final, 1625 - .finup = omap_sham_finup, 1626 - .digest = omap_sham_digest, 1627 - .halg.digestsize = SHA384_DIGEST_SIZE, 1628 - .halg.base = { 1622 + .base.init = omap_sham_init, 1623 + .base.update = omap_sham_update, 1624 + .base.final = omap_sham_final, 1625 + .base.finup = omap_sham_finup, 1626 + .base.digest = omap_sham_digest, 1627 + .base.halg.digestsize = SHA384_DIGEST_SIZE, 1628 + .base.halg.base = { 1629 1629 .cra_name = "sha384", 1630 1630 .cra_driver_name = "omap-sha384", 1631 1631 .cra_priority = 400, ··· 1639 1637 .cra_module = THIS_MODULE, 1640 1638 .cra_init = omap_sham_cra_init, 1641 1639 .cra_exit = omap_sham_cra_exit, 1642 - } 1640 + }, 1641 + .op.do_one_request = omap_sham_hash_one_req, 1643 1642 }, 1644 1643 { 1645 - .init = omap_sham_init, 1646 - .update = omap_sham_update, 1647 - .final = omap_sham_final, 1648 - .finup = omap_sham_finup, 1649 - .digest = omap_sham_digest, 1650 - .halg.digestsize = SHA512_DIGEST_SIZE, 1651 - .halg.base = { 1644 + .base.init = omap_sham_init, 1645 + .base.update = omap_sham_update, 1646 + .base.final = omap_sham_final, 1647 + .base.finup = omap_sham_finup, 1648 + .base.digest = omap_sham_digest, 1649 + .base.halg.digestsize = SHA512_DIGEST_SIZE, 1650 + .base.halg.base = { 1652 1651 .cra_name = "sha512", 1653 1652 .cra_driver_name = "omap-sha512", 1654 1653 .cra_priority = 400, ··· 1662 1659 .cra_module = THIS_MODULE, 1663 1660 .cra_init = omap_sham_cra_init, 1664 1661 .cra_exit = omap_sham_cra_exit, 1665 - } 1662 + }, 1663 + .op.do_one_request = omap_sham_hash_one_req, 1666 1664 }, 1667 1665 { 1668 - .init = omap_sham_init, 1669 - .update = omap_sham_update, 1670 - .final = omap_sham_final, 1671 - .finup = omap_sham_finup, 1672 - .digest = omap_sham_digest, 1673 - .setkey = omap_sham_setkey, 1674 - .halg.digestsize = SHA384_DIGEST_SIZE, 1675 - .halg.base = { 1666 + .base.init = omap_sham_init, 1667 + .base.update = omap_sham_update, 1668 + .base.final = omap_sham_final, 1669 + .base.finup = omap_sham_finup, 1670 + .base.digest = omap_sham_digest, 1671 + .base.setkey = omap_sham_setkey, 1672 + .base.halg.digestsize = SHA384_DIGEST_SIZE, 1673 + .base.halg.base = { 1676 1674 .cra_name = "hmac(sha384)", 1677 1675 .cra_driver_name = "omap-hmac-sha384", 1678 1676 .cra_priority = 400, ··· 1687 1683 .cra_module = THIS_MODULE, 1688 1684 .cra_init = omap_sham_cra_sha384_init, 1689 1685 .cra_exit = omap_sham_cra_exit, 1690 - } 1686 + }, 1687 + .op.do_one_request = omap_sham_hash_one_req, 1691 1688 }, 1692 1689 { 1693 - .init = omap_sham_init, 1694 - .update = omap_sham_update, 1695 - .final = omap_sham_final, 1696 - .finup = omap_sham_finup, 1697 - .digest = omap_sham_digest, 1698 - .setkey = omap_sham_setkey, 1699 - .halg.digestsize = SHA512_DIGEST_SIZE, 1700 - .halg.base = { 1690 + .base.init = omap_sham_init, 1691 + .base.update = omap_sham_update, 1692 + .base.final = omap_sham_final, 1693 + .base.finup = omap_sham_finup, 1694 + .base.digest = omap_sham_digest, 1695 + .base.setkey = omap_sham_setkey, 1696 + .base.halg.digestsize = SHA512_DIGEST_SIZE, 1697 + .base.halg.base = { 1701 1698 .cra_name = "hmac(sha512)", 1702 1699 .cra_driver_name = "omap-hmac-sha512", 1703 1700 .cra_priority = 400, ··· 1712 1707 .cra_module = THIS_MODULE, 1713 1708 .cra_init = omap_sham_cra_sha512_init, 1714 1709 .cra_exit = omap_sham_cra_exit, 1715 - } 1710 + }, 1711 + .op.do_one_request = omap_sham_hash_one_req, 1716 1712 }, 1717 1713 }; 1718 1714 ··· 2154 2148 break; 2155 2149 2156 2150 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2151 + struct ahash_engine_alg *ealg; 2157 2152 struct ahash_alg *alg; 2158 2153 2159 - alg = &dd->pdata->algs_info[i].algs_list[j]; 2154 + ealg = &dd->pdata->algs_info[i].algs_list[j]; 2155 + alg = &ealg->base; 2160 2156 alg->export = omap_sham_export; 2161 2157 alg->import = omap_sham_import; 2162 2158 alg->halg.statesize = sizeof(struct omap_sham_reqctx) + 2163 2159 BUFLEN; 2164 - err = crypto_register_ahash(alg); 2160 + err = crypto_engine_register_ahash(ealg); 2165 2161 if (err) 2166 2162 goto err_algs; 2167 2163 ··· 2182 2174 err_algs: 2183 2175 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2184 2176 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2185 - crypto_unregister_ahash( 2177 + crypto_engine_unregister_ahash( 2186 2178 &dd->pdata->algs_info[i].algs_list[j]); 2187 2179 err_engine_start: 2188 2180 crypto_engine_exit(dd->engine); ··· 2213 2205 spin_unlock_bh(&sham.lock); 2214 2206 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2215 2207 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { 2216 - crypto_unregister_ahash( 2208 + crypto_engine_unregister_ahash( 2217 2209 &dd->pdata->algs_info[i].algs_list[j]); 2218 2210 dd->pdata->algs_info[i].registered--; 2219 2211 }