tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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MIPS: Code formatting fixes.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Steven J. Hill and committed by
Ralf Baechle 03751e79 36be5051

+40 -40
+27 -27
arch/mips/kernel/cpu-probe.c
··· 340 340 __cpu_name[cpu] = "R2000"; 341 341 c->isa_level = MIPS_CPU_ISA_I; 342 342 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 343 - MIPS_CPU_NOFPUEX; 343 + MIPS_CPU_NOFPUEX; 344 344 if (__cpu_has_fpu()) 345 345 c->options |= MIPS_CPU_FPU; 346 346 c->tlbsize = 64; ··· 361 361 } 362 362 c->isa_level = MIPS_CPU_ISA_I; 363 363 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 364 - MIPS_CPU_NOFPUEX; 364 + MIPS_CPU_NOFPUEX; 365 365 if (__cpu_has_fpu()) 366 366 c->options |= MIPS_CPU_FPU; 367 367 c->tlbsize = 64; ··· 387 387 388 388 c->isa_level = MIPS_CPU_ISA_III; 389 389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 390 - MIPS_CPU_WATCH | MIPS_CPU_VCE | 391 - MIPS_CPU_LLSC; 390 + MIPS_CPU_WATCH | MIPS_CPU_VCE | 391 + MIPS_CPU_LLSC; 392 392 c->tlbsize = 48; 393 393 break; 394 394 case PRID_IMP_VR41XX: ··· 434 434 __cpu_name[cpu] = "R4300"; 435 435 c->isa_level = MIPS_CPU_ISA_III; 436 436 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 437 - MIPS_CPU_LLSC; 437 + MIPS_CPU_LLSC; 438 438 c->tlbsize = 32; 439 439 break; 440 440 case PRID_IMP_R4600: ··· 446 446 c->tlbsize = 48; 447 447 break; 448 448 #if 0 449 - case PRID_IMP_R4650: 449 + case PRID_IMP_R4650: 450 450 /* 451 451 * This processor doesn't have an MMU, so it's not 452 452 * "real easy" to run Linux on it. It is left purely ··· 455 455 */ 456 456 c->cputype = CPU_R4650; 457 457 __cpu_name[cpu] = "R4650"; 458 - c->isa_level = MIPS_CPU_ISA_III; 458 + c->isa_level = MIPS_CPU_ISA_III; 459 459 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 460 - c->tlbsize = 48; 460 + c->tlbsize = 48; 461 461 break; 462 462 #endif 463 463 case PRID_IMP_TX39: ··· 488 488 __cpu_name[cpu] = "R4700"; 489 489 c->isa_level = MIPS_CPU_ISA_III; 490 490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 491 - MIPS_CPU_LLSC; 491 + MIPS_CPU_LLSC; 492 492 c->tlbsize = 48; 493 493 break; 494 494 case PRID_IMP_TX49: ··· 505 505 __cpu_name[cpu] = "R5000"; 506 506 c->isa_level = MIPS_CPU_ISA_IV; 507 507 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 508 - MIPS_CPU_LLSC; 508 + MIPS_CPU_LLSC; 509 509 c->tlbsize = 48; 510 510 break; 511 511 case PRID_IMP_R5432: ··· 513 513 __cpu_name[cpu] = "R5432"; 514 514 c->isa_level = MIPS_CPU_ISA_IV; 515 515 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 516 - MIPS_CPU_WATCH | MIPS_CPU_LLSC; 516 + MIPS_CPU_WATCH | MIPS_CPU_LLSC; 517 517 c->tlbsize = 48; 518 518 break; 519 519 case PRID_IMP_R5500: ··· 521 521 __cpu_name[cpu] = "R5500"; 522 522 c->isa_level = MIPS_CPU_ISA_IV; 523 523 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 524 - MIPS_CPU_WATCH | MIPS_CPU_LLSC; 524 + MIPS_CPU_WATCH | MIPS_CPU_LLSC; 525 525 c->tlbsize = 48; 526 526 break; 527 527 case PRID_IMP_NEVADA: ··· 529 529 __cpu_name[cpu] = "Nevada"; 530 530 c->isa_level = MIPS_CPU_ISA_IV; 531 531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 532 - MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 532 + MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 533 533 c->tlbsize = 48; 534 534 break; 535 535 case PRID_IMP_R6000: ··· 537 537 __cpu_name[cpu] = "R6000"; 538 538 c->isa_level = MIPS_CPU_ISA_II; 539 539 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 540 - MIPS_CPU_LLSC; 540 + MIPS_CPU_LLSC; 541 541 c->tlbsize = 32; 542 542 break; 543 543 case PRID_IMP_R6000A: ··· 545 545 __cpu_name[cpu] = "R6000A"; 546 546 c->isa_level = MIPS_CPU_ISA_II; 547 547 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 548 - MIPS_CPU_LLSC; 548 + MIPS_CPU_LLSC; 549 549 c->tlbsize = 32; 550 550 break; 551 551 case PRID_IMP_RM7000: ··· 553 553 __cpu_name[cpu] = "RM7000"; 554 554 c->isa_level = MIPS_CPU_ISA_IV; 555 555 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 556 - MIPS_CPU_LLSC; 556 + MIPS_CPU_LLSC; 557 557 /* 558 558 * Undocumented RM7000: Bit 29 in the info register of 559 559 * the RM7000 v2.0 indicates if the TLB has 48 or 64 ··· 569 569 __cpu_name[cpu] = "RM9000"; 570 570 c->isa_level = MIPS_CPU_ISA_IV; 571 571 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 572 - MIPS_CPU_LLSC; 572 + MIPS_CPU_LLSC; 573 573 /* 574 574 * Bit 29 in the info register of the RM9000 575 575 * indicates if the TLB has 48 or 64 entries. ··· 584 584 __cpu_name[cpu] = "RM8000"; 585 585 c->isa_level = MIPS_CPU_ISA_IV; 586 586 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 587 - MIPS_CPU_FPU | MIPS_CPU_32FPR | 588 - MIPS_CPU_LLSC; 587 + MIPS_CPU_FPU | MIPS_CPU_32FPR | 588 + MIPS_CPU_LLSC; 589 589 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 590 590 break; 591 591 case PRID_IMP_R10000: ··· 593 593 __cpu_name[cpu] = "R10000"; 594 594 c->isa_level = MIPS_CPU_ISA_IV; 595 595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 596 - MIPS_CPU_FPU | MIPS_CPU_32FPR | 596 + MIPS_CPU_FPU | MIPS_CPU_32FPR | 597 597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 598 - MIPS_CPU_LLSC; 598 + MIPS_CPU_LLSC; 599 599 c->tlbsize = 64; 600 600 break; 601 601 case PRID_IMP_R12000: ··· 603 603 __cpu_name[cpu] = "R12000"; 604 604 c->isa_level = MIPS_CPU_ISA_IV; 605 605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 606 - MIPS_CPU_FPU | MIPS_CPU_32FPR | 606 + MIPS_CPU_FPU | MIPS_CPU_32FPR | 607 607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 608 - MIPS_CPU_LLSC; 608 + MIPS_CPU_LLSC; 609 609 c->tlbsize = 64; 610 610 break; 611 611 case PRID_IMP_R14000: ··· 613 613 __cpu_name[cpu] = "R14000"; 614 614 c->isa_level = MIPS_CPU_ISA_IV; 615 615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 616 - MIPS_CPU_FPU | MIPS_CPU_32FPR | 616 + MIPS_CPU_FPU | MIPS_CPU_32FPR | 617 617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 618 - MIPS_CPU_LLSC; 618 + MIPS_CPU_LLSC; 619 619 c->tlbsize = 64; 620 620 break; 621 621 case PRID_IMP_LOONGSON2: ··· 739 739 if (config3 & MIPS_CONF3_VEIC) 740 740 c->options |= MIPS_CPU_VEIC; 741 741 if (config3 & MIPS_CONF3_MT) 742 - c->ases |= MIPS_ASE_MIPSMT; 742 + c->ases |= MIPS_ASE_MIPSMT; 743 743 if (config3 & MIPS_CONF3_ULRI) 744 744 c->options |= MIPS_CPU_ULRI; 745 745 ··· 767 767 768 768 /* MIPS32 or MIPS64 compliant CPU. */ 769 769 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 770 - MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 770 + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 771 771 772 772 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 773 773
+13 -13
arch/mips/kernel/proc.c
··· 41 41 42 42 seq_printf(m, "processor\t\t: %ld\n", n); 43 43 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", 44 - cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); 44 + cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); 45 45 seq_printf(m, fmt, __cpu_name[n], 46 - (version >> 4) & 0x0f, version & 0x0f, 47 - (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 46 + (version >> 4) & 0x0f, version & 0x0f, 47 + (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 48 48 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", 49 - cpu_data[n].udelay_val / (500000/HZ), 50 - (cpu_data[n].udelay_val / (5000/HZ)) % 100); 49 + cpu_data[n].udelay_val / (500000/HZ), 50 + (cpu_data[n].udelay_val / (5000/HZ)) % 100); 51 51 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); 52 52 seq_printf(m, "microsecond timers\t: %s\n", 53 - cpu_has_counter ? "yes" : "no"); 53 + cpu_has_counter ? "yes" : "no"); 54 54 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); 55 55 seq_printf(m, "extra interrupt vector\t: %s\n", 56 - cpu_has_divec ? "yes" : "no"); 56 + cpu_has_divec ? "yes" : "no"); 57 57 seq_printf(m, "hardware watchpoint\t: %s", 58 - cpu_has_watch ? "yes, " : "no\n"); 58 + cpu_has_watch ? "yes, " : "no\n"); 59 59 if (cpu_has_watch) { 60 60 seq_printf(m, "count: %d, address/irw mask: [", 61 - cpu_data[n].watch_reg_count); 61 + cpu_data[n].watch_reg_count); 62 62 for (i = 0; i < cpu_data[n].watch_reg_count; i++) 63 63 seq_printf(m, "%s0x%04x", i ? ", " : "" , 64 - cpu_data[n].watch_reg_masks[i]); 64 + cpu_data[n].watch_reg_masks[i]); 65 65 seq_printf(m, "]\n"); 66 66 } 67 67 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", ··· 73 73 cpu_has_mipsmt ? " mt" : "" 74 74 ); 75 75 seq_printf(m, "shadow register sets\t: %d\n", 76 - cpu_data[n].srsets); 76 + cpu_data[n].srsets); 77 77 seq_printf(m, "kscratch registers\t: %d\n", 78 - hweight8(cpu_data[n].kscratch_mask)); 78 + hweight8(cpu_data[n].kscratch_mask)); 79 79 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); 80 80 81 81 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 82 - cpu_has_vce ? "%u" : "not available"); 82 + cpu_has_vce ? "%u" : "not available"); 83 83 seq_printf(m, fmt, 'D', vced_count); 84 84 seq_printf(m, fmt, 'I', vcei_count); 85 85 seq_printf(m, "\n");