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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
phy: qcom-qmp: Add MSM8996 UFS QMP support
The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.
Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
authored by
Bjorn Andersson
and committed by
Kishon Vijay Abraham I
0347f0dc
afa4ba05
+111
+5
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+5
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
···
8
8
- compatible: compatible list, contains:
9
9
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10
10
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11
+
"qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
11
12
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12
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"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
13
14
"qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
···
47
46
For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
48
47
For "qcom,msm8996-qmp-pcie-phy" must contain:
49
48
"aux", "cfg_ahb", "ref".
49
+
For "qcom,msm8996-qmp-ufs-phy" must contain:
50
+
"ref".
50
51
For "qcom,msm8996-qmp-usb3-phy" must contain:
51
52
"aux", "cfg_ahb", "ref".
52
53
For "qcom,msm8998-qmp-usb3-phy" must contain:
···
81
78
"phy", "common".
82
79
For "qcom,msm8996-qmp-pcie-phy" must contain:
83
80
"phy", "common", "cfg".
81
+
For "qcom,msm8996-qmp-ufs-phy": must contain:
82
+
"ufsphy".
84
83
For "qcom,msm8996-qmp-usb3-phy" must contain
85
84
"phy", "common".
86
85
For "qcom,msm8998-qmp-usb3-phy" must contain
+106
drivers/phy/qualcomm/phy-qcom-qmp.c
+106
drivers/phy/qualcomm/phy-qcom-qmp.c
···
121
121
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
122
122
};
123
123
124
+
static const unsigned int msm8996_ufsphy_regs_layout[] = {
125
+
[QPHY_START_CTRL] = 0x00,
126
+
[QPHY_PCS_READY_STATUS] = 0x168,
127
+
};
128
+
124
129
static const unsigned int pciephy_regs_layout[] = {
125
130
[QPHY_COM_SW_RESET] = 0x400,
126
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[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
···
346
341
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
347
342
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
348
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
344
+
};
345
+
346
+
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
347
+
QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
348
+
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
349
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
350
+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
351
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
352
+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
353
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
354
+
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
355
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
356
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
357
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
358
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
359
+
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
360
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
361
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
362
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
363
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
364
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
365
+
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
366
+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
367
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
368
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
369
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
370
+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
371
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
372
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
373
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
374
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
375
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
376
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
377
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
378
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
379
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
380
+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
381
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
382
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
383
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
384
+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
385
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
386
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
387
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
388
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
389
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
390
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
391
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
392
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
393
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
394
+
};
395
+
396
+
static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
397
+
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
398
+
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
399
+
};
400
+
401
+
static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
402
+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
403
+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
404
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
405
+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
406
+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
407
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
408
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
409
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
410
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
411
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
412
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
349
413
};
350
414
351
415
static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
···
1433
1359
"aux", "cfg_ahb", "ref",
1434
1360
};
1435
1361
1362
+
static const char * const msm8996_ufs_phy_clk_l[] = {
1363
+
"ref",
1364
+
};
1365
+
1436
1366
static const char * const qmp_v3_phy_clk_l[] = {
1437
1367
"aux", "cfg_ahb", "ref", "com_aux",
1438
1368
};
···
1496
1418
.has_pwrdn_delay = true,
1497
1419
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1498
1420
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1421
+
};
1422
+
1423
+
static const struct qmp_phy_cfg msm8996_ufs_cfg = {
1424
+
.type = PHY_TYPE_UFS,
1425
+
.nlanes = 1,
1426
+
1427
+
.serdes_tbl = msm8996_ufs_serdes_tbl,
1428
+
.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
1429
+
.tx_tbl = msm8996_ufs_tx_tbl,
1430
+
.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
1431
+
.rx_tbl = msm8996_ufs_rx_tbl,
1432
+
.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
1433
+
1434
+
.clk_list = msm8996_ufs_phy_clk_l,
1435
+
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
1436
+
1437
+
.vreg_list = qmp_phy_vreg_l,
1438
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1439
+
1440
+
.regs = msm8996_ufsphy_regs_layout,
1441
+
1442
+
.start_ctrl = SERDES_START,
1443
+
.pwrdn_ctrl = SW_PWRDN,
1444
+
1445
+
.no_pcs_sw_reset = true,
1499
1446
};
1500
1447
1501
1448
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
···
2500
2397
{
2501
2398
.compatible = "qcom,msm8996-qmp-pcie-phy",
2502
2399
.data = &msm8996_pciephy_cfg,
2400
+
}, {
2401
+
.compatible = "qcom,msm8996-qmp-ufs-phy",
2402
+
.data = &msm8996_ufs_cfg,
2503
2403
}, {
2504
2404
.compatible = "qcom,msm8996-qmp-usb3-phy",
2505
2405
.data = &msm8996_usb3phy_cfg,