Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'rtc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:
"Many cleanups and a few drivers removal this cycle.

Subsystem:
- Introduce features bitfield and the first feature: RTC_FEATURE_ALARM

Removed drivers:
- ab3100
- coh901331
- tx4939
- sirfsoc

Drivers:
- use rtc_lock and rtc_unlock instead of opencoding
- constify all struct rtc_class_ops
- quiet maybe-unused variable warning
- replace spin_lock_irqsave with spin_lock in hard IRQ
- pcf2127: disable Power-On Reset Override and run OTP refresh"

* tag 'rtc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (81 commits)
rtc: abx80x: Add utility function for writing configuration key
rtc: pcf2127: properly set flag WD_CD for rtc chips(pcf2129, pca2129)
rtc: pcf8563: Add NXP PCA8565 compatible
rtc: s3c: quiet maybe-unused variable warning
rtc: s3c: stop setting bogus time
rtc: sd3078: quiet maybe-unused variable warning
rtc: s35390a: quiet maybe-unused variable warning
rtc: rx8581: quiet maybe-unused variable warning
rtc: rx8010: quiet maybe-unused variable warning
rtc: rv8803: quiet maybe-unused variable warning
rtc: rv3032: quiet maybe-unused variable warning
rtc: rv3029: quiet maybe-unused variable warning
rtc: rv3028: quiet maybe-unused variable warning
rtc: rs5c372: quiet maybe-unused variable warning
rtc: pcf85363: quiet maybe-unused variable warning
rtc: pcf85063: quiet maybe-unused variable warnings
rtc: meson: quiet maybe-unused variable warning
rtc: m41t80: quiet maybe-unused variable warning
rtc: isl1208: quiet maybe-unused variable warning
rtc: ds3232: quiet maybe-unused variable warning
...

+322 -1718
+1
Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml
··· 20 20 - atmel,sama5d4-rtc 21 21 - atmel,sama5d2-rtc 22 22 - microchip,sam9x60-rtc 23 + - microchip,sama7g5-rtc 23 24 24 25 reg: 25 26 maxItems: 1
+51
Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/nxp,pcf2127.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NXP PCF2127 Real Time Clock 8 + 9 + allOf: 10 + - $ref: "rtc.yaml#" 11 + 12 + maintainers: 13 + - Alexandre Belloni <alexandre.belloni@bootlin.com> 14 + 15 + properties: 16 + compatible: 17 + const: nxp,pcf2127 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + interrupts: 23 + maxItems: 1 24 + 25 + start-year: true 26 + 27 + reset-source: true 28 + 29 + required: 30 + - compatible 31 + - reg 32 + 33 + additionalProperties: false 34 + 35 + examples: 36 + - | 37 + #include <dt-bindings/interrupt-controller/irq.h> 38 + i2c { 39 + #address-cells = <1>; 40 + #size-cells = <0>; 41 + 42 + rtc@51 { 43 + compatible = "nxp,pcf2127"; 44 + reg = <0x51>; 45 + pinctrl-0 = <&rtc_nint_pins>; 46 + interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>; 47 + reset-source; 48 + }; 49 + }; 50 + 51 + ...
+2 -1
Documentation/devicetree/bindings/rtc/pcf8563.txt
··· 5 5 Required properties: 6 6 - compatible: Should contain "nxp,pcf8563", 7 7 "epson,rtc8564" or 8 - "microcrystal,rv8564" 8 + "microcrystal,rv8564" or 9 + "nxp,pca8565" 9 10 - reg: I2C address for chip. 10 11 11 12 Optional property:
-13
Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt
··· 1 - SiRFSoC Real Time Clock 2 - 3 - Required properties: 4 - - compatible: must be "sirf,prima2-sysrtc" 5 - - reg: address range of rtc register set. 6 - - interrupts: rtc alarm interrupts. 7 - 8 - Example: 9 - rtc@2000 { 10 - compatible = "sirf,prima2-sysrtc"; 11 - reg = <0x2000 0x1000>; 12 - interrupts = <52 53 54>; 13 - };
-16
Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt
··· 1 - ST-Ericsson COH 901 331 Real Time Clock 2 - 3 - Required properties: 4 - - compatible: must be "stericsson,coh901331" 5 - - reg: address range of rtc register set. 6 - - interrupts: rtc alarm interrupt. 7 - - clocks: phandle to the rtc clock source 8 - 9 - Example: 10 - rtc: rtc@c0017000 { 11 - compatible = "stericsson,coh901331"; 12 - reg = <0xc0017000 0x1000>; 13 - interrupt-parent = <&vicb>; 14 - interrupts = <10>; 15 - clocks = <&rtc_clk>; 16 - };
+1 -5
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
··· 48 48 - microcrystal,rv3029 49 49 # Real Time Clock 50 50 - microcrystal,rv8523 51 - # Real-time clock 52 - - nxp,pcf2127 53 - # Real-time clock 54 - - nxp,pcf2129 55 - # Real-time clock 56 51 - nxp,pca2129 52 + - nxp,pcf2129 57 53 # Real-time Clock Module 58 54 - pericom,pt7c4338 59 55 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+3 -35
drivers/rtc/Kconfig
··· 692 692 tristate "Samsung S2M/S5M series" 693 693 depends on MFD_SEC_CORE || COMPILE_TEST 694 694 select REGMAP_IRQ 695 + select REGMAP_I2C 695 696 help 696 697 If you say yes here you will get support for the 697 698 RTC of Samsung S2MPS14 and S5M PMIC series. ··· 1259 1258 If you say yes here you get support for the RTC subsystem of the 1260 1259 NXP PCF50633 used in embedded systems. 1261 1260 1262 - config RTC_DRV_AB3100 1263 - tristate "ST-Ericsson AB3100 RTC" 1264 - depends on AB3100_CORE 1265 - default y if AB3100_CORE 1266 - help 1267 - Select this to enable the ST-Ericsson AB3100 Mixed Signal IC RTC 1268 - support. This chip contains a battery- and capacitor-backed RTC. 1269 - 1270 1261 config RTC_DRV_AB8500 1271 1262 tristate "ST-Ericsson AB8500 RTC" 1272 1263 depends on AB8500_CORE ··· 1281 1288 1282 1289 config RTC_DRV_ZYNQMP 1283 1290 tristate "Xilinx Zynq Ultrascale+ MPSoC RTC" 1284 - depends on OF 1291 + depends on OF && HAS_IOMEM 1285 1292 help 1286 1293 If you say yes here you get support for the RTC controller found on 1287 1294 Xilinx Zynq Ultrascale+ MPSoC. ··· 1568 1575 If you say Y here you will get support for the RTC found on 1569 1576 Starfire systems. 1570 1577 1571 - config RTC_DRV_TX4939 1572 - tristate "TX4939 SoC" 1573 - depends on SOC_TX4939 || COMPILE_TEST 1574 - help 1575 - Driver for the internal RTC (Realtime Clock) module found on 1576 - Toshiba TX4939 SoC. 1577 - 1578 1578 config RTC_DRV_MV 1579 1579 tristate "Marvell SoC RTC" 1580 1580 depends on ARCH_DOVE || ARCH_MVEBU || COMPILE_TEST ··· 1582 1596 config RTC_DRV_ARMADA38X 1583 1597 tristate "Armada 38x Marvell SoC RTC" 1584 1598 depends on ARCH_MVEBU || COMPILE_TEST 1599 + depends on OF 1585 1600 help 1586 1601 If you say yes here you will get support for the in-chip RTC 1587 1602 that can be found in the Armada 38x Marvell's SoC device ··· 1619 1632 1620 1633 This driver can also be built as a module. If so, the module 1621 1634 will be called rtc-ps3. 1622 - 1623 - config RTC_DRV_COH901331 1624 - tristate "ST-Ericsson COH 901 331 RTC" 1625 - depends on ARCH_U300 || COMPILE_TEST 1626 - help 1627 - If you say Y here you will get access to ST-Ericsson 1628 - COH 901 331 RTC clock found in some ST-Ericsson Mobile 1629 - Platforms. 1630 - 1631 - This driver can also be built as a module. If so, the module 1632 - will be called "rtc-coh901331". 1633 - 1634 1635 1635 1636 config RTC_DRV_STMP 1636 1637 tristate "Freescale STMP3xxx/i.MX23/i.MX28 RTC" ··· 1761 1786 help 1762 1787 If you say yes here you get support for the NXP i.MX System 1763 1788 Controller RTC module. 1764 - 1765 - config RTC_DRV_SIRFSOC 1766 - tristate "SiRFSOC RTC" 1767 - depends on ARCH_SIRF 1768 - help 1769 - Say "yes" here to support the real time clock on SiRF SOC chips. 1770 - This driver can also be built as a module called rtc-sirfsoc. 1771 1789 1772 1790 config RTC_DRV_ST_LPC 1773 1791 tristate "STMicroelectronics LPC RTC"
-4
drivers/rtc/Makefile
··· 19 19 20 20 obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o 21 21 obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o 22 - obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o 23 22 obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o 24 23 obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o 25 24 obj-$(CONFIG_RTC_DRV_ABEOZ9) += rtc-ab-eoz9.o ··· 37 38 obj-$(CONFIG_RTC_DRV_BRCMSTB) += rtc-brcmstb-waketimer.o 38 39 obj-$(CONFIG_RTC_DRV_CADENCE) += rtc-cadence.o 39 40 obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o 40 - obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o 41 41 obj-$(CONFIG_RTC_DRV_CPCAP) += rtc-cpcap.o 42 42 obj-$(CONFIG_RTC_DRV_CROS_EC) += rtc-cros-ec.o 43 43 obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o ··· 152 154 obj-$(CONFIG_RTC_DRV_SC27XX) += rtc-sc27xx.o 153 155 obj-$(CONFIG_RTC_DRV_SD3078) += rtc-sd3078.o 154 156 obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o 155 - obj-$(CONFIG_RTC_DRV_SIRFSOC) += rtc-sirfsoc.o 156 157 obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o 157 158 obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o 158 159 obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o ··· 168 171 obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o 169 172 obj-$(CONFIG_RTC_DRV_TPS80031) += rtc-tps80031.o 170 173 obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o 171 - obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o 172 174 obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o 173 175 obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o 174 176 obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o
+5 -5
drivers/rtc/class.c
··· 231 231 rtc->pie_timer.function = rtc_pie_update_irq; 232 232 rtc->pie_enabled = 0; 233 233 234 + set_bit(RTC_FEATURE_ALARM, rtc->features); 235 + 234 236 return rtc; 235 237 } 236 238 ··· 324 322 rtc->offset_secs = 0; 325 323 } 326 324 327 - /** 328 - * rtc_device_unregister - removes the previously registered RTC class device 329 - * 330 - * @rtc: the RTC class device to destroy 331 - */ 332 325 static void devm_rtc_unregister_device(void *data) 333 326 { 334 327 struct rtc_device *rtc = data; ··· 382 385 dev_dbg(&rtc->dev, "no ops set\n"); 383 386 return -EINVAL; 384 387 } 388 + 389 + if (!rtc->ops->set_alarm) 390 + clear_bit(RTC_FEATURE_ALARM, rtc->features); 385 391 386 392 rtc->owner = owner; 387 393 rtc_device_get_offset(rtc);
+6 -6
drivers/rtc/interface.c
··· 186 186 187 187 if (!rtc->ops) { 188 188 err = -ENODEV; 189 - } else if (!rtc->ops->read_alarm) { 189 + } else if (!test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->read_alarm) { 190 190 err = -EINVAL; 191 191 } else { 192 192 alarm->enabled = 0; ··· 392 392 return err; 393 393 if (!rtc->ops) { 394 394 err = -ENODEV; 395 - } else if (!rtc->ops->read_alarm) { 395 + } else if (!test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->read_alarm) { 396 396 err = -EINVAL; 397 397 } else { 398 398 memset(alarm, 0, sizeof(struct rtc_wkalrm)); ··· 436 436 437 437 if (!rtc->ops) 438 438 err = -ENODEV; 439 - else if (!rtc->ops->set_alarm) 439 + else if (!test_bit(RTC_FEATURE_ALARM, rtc->features)) 440 440 err = -EINVAL; 441 441 else 442 442 err = rtc->ops->set_alarm(rtc->dev.parent, alarm); ··· 451 451 452 452 if (!rtc->ops) 453 453 return -ENODEV; 454 - else if (!rtc->ops->set_alarm) 454 + else if (!test_bit(RTC_FEATURE_ALARM, rtc->features)) 455 455 return -EINVAL; 456 456 457 457 err = rtc_valid_tm(&alarm->time); ··· 531 531 /* nothing */; 532 532 else if (!rtc->ops) 533 533 err = -ENODEV; 534 - else if (!rtc->ops->alarm_irq_enable) 534 + else if (!test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->alarm_irq_enable) 535 535 err = -EINVAL; 536 536 else 537 537 err = rtc->ops->alarm_irq_enable(rtc->dev.parent, enabled); ··· 843 843 844 844 static void rtc_alarm_disable(struct rtc_device *rtc) 845 845 { 846 - if (!rtc->ops || !rtc->ops->alarm_irq_enable) 846 + if (!rtc->ops || !test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->alarm_irq_enable) 847 847 return; 848 848 849 849 rtc->ops->alarm_irq_enable(rtc->dev.parent, false);
-254
drivers/rtc/rtc-ab3100.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Copyright (C) 2007-2009 ST-Ericsson AB 4 - * RTC clock driver for the AB3100 Analog Baseband Chip 5 - * Author: Linus Walleij <linus.walleij@stericsson.com> 6 - */ 7 - #include <linux/module.h> 8 - #include <linux/kernel.h> 9 - #include <linux/init.h> 10 - #include <linux/platform_device.h> 11 - #include <linux/rtc.h> 12 - #include <linux/mfd/abx500.h> 13 - 14 - /* Clock rate in Hz */ 15 - #define AB3100_RTC_CLOCK_RATE 32768 16 - 17 - /* 18 - * The AB3100 RTC registers. These are the same for 19 - * AB3000 and AB3100. 20 - * Control register: 21 - * Bit 0: RTC Monitor cleared=0, active=1, if you set it 22 - * to 1 it remains active until RTC power is lost. 23 - * Bit 1: 32 kHz Oscillator, 0 = on, 1 = bypass 24 - * Bit 2: Alarm on, 0 = off, 1 = on 25 - * Bit 3: 32 kHz buffer disabling, 0 = enabled, 1 = disabled 26 - */ 27 - #define AB3100_RTC 0x53 28 - /* default setting, buffer disabled, alarm on */ 29 - #define RTC_SETTING 0x30 30 - /* Alarm when AL0-AL3 == TI0-TI3 */ 31 - #define AB3100_AL0 0x56 32 - #define AB3100_AL1 0x57 33 - #define AB3100_AL2 0x58 34 - #define AB3100_AL3 0x59 35 - /* This 48-bit register that counts up at 32768 Hz */ 36 - #define AB3100_TI0 0x5a 37 - #define AB3100_TI1 0x5b 38 - #define AB3100_TI2 0x5c 39 - #define AB3100_TI3 0x5d 40 - #define AB3100_TI4 0x5e 41 - #define AB3100_TI5 0x5f 42 - 43 - /* 44 - * RTC clock functions and device struct declaration 45 - */ 46 - static int ab3100_rtc_set_time(struct device *dev, struct rtc_time *tm) 47 - { 48 - u8 regs[] = {AB3100_TI0, AB3100_TI1, AB3100_TI2, 49 - AB3100_TI3, AB3100_TI4, AB3100_TI5}; 50 - unsigned char buf[6]; 51 - u64 hw_counter = rtc_tm_to_time64(tm) * AB3100_RTC_CLOCK_RATE * 2; 52 - int err = 0; 53 - int i; 54 - 55 - buf[0] = (hw_counter) & 0xFF; 56 - buf[1] = (hw_counter >> 8) & 0xFF; 57 - buf[2] = (hw_counter >> 16) & 0xFF; 58 - buf[3] = (hw_counter >> 24) & 0xFF; 59 - buf[4] = (hw_counter >> 32) & 0xFF; 60 - buf[5] = (hw_counter >> 40) & 0xFF; 61 - 62 - for (i = 0; i < 6; i++) { 63 - err = abx500_set_register_interruptible(dev, 0, 64 - regs[i], buf[i]); 65 - if (err) 66 - return err; 67 - } 68 - 69 - /* Set the flag to mark that the clock is now set */ 70 - return abx500_mask_and_set_register_interruptible(dev, 0, 71 - AB3100_RTC, 72 - 0x01, 0x01); 73 - 74 - } 75 - 76 - static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm) 77 - { 78 - time64_t time; 79 - u8 rtcval; 80 - int err; 81 - 82 - err = abx500_get_register_interruptible(dev, 0, 83 - AB3100_RTC, &rtcval); 84 - if (err) 85 - return err; 86 - 87 - if (!(rtcval & 0x01)) { 88 - dev_info(dev, "clock not set (lost power)"); 89 - return -EINVAL; 90 - } else { 91 - u64 hw_counter; 92 - u8 buf[6]; 93 - 94 - /* Read out time registers */ 95 - err = abx500_get_register_page_interruptible(dev, 0, 96 - AB3100_TI0, 97 - buf, 6); 98 - if (err != 0) 99 - return err; 100 - 101 - hw_counter = ((u64) buf[5] << 40) | ((u64) buf[4] << 32) | 102 - ((u64) buf[3] << 24) | ((u64) buf[2] << 16) | 103 - ((u64) buf[1] << 8) | (u64) buf[0]; 104 - time = hw_counter / (u64) (AB3100_RTC_CLOCK_RATE * 2); 105 - } 106 - 107 - rtc_time64_to_tm(time, tm); 108 - 109 - return 0; 110 - } 111 - 112 - static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 113 - { 114 - time64_t time; 115 - u64 hw_counter; 116 - u8 buf[6]; 117 - u8 rtcval; 118 - int err; 119 - 120 - /* Figure out if alarm is enabled or not */ 121 - err = abx500_get_register_interruptible(dev, 0, 122 - AB3100_RTC, &rtcval); 123 - if (err) 124 - return err; 125 - if (rtcval & 0x04) 126 - alarm->enabled = 1; 127 - else 128 - alarm->enabled = 0; 129 - /* No idea how this could be represented */ 130 - alarm->pending = 0; 131 - /* Read out alarm registers, only 4 bytes */ 132 - err = abx500_get_register_page_interruptible(dev, 0, 133 - AB3100_AL0, buf, 4); 134 - if (err) 135 - return err; 136 - hw_counter = ((u64) buf[3] << 40) | ((u64) buf[2] << 32) | 137 - ((u64) buf[1] << 24) | ((u64) buf[0] << 16); 138 - time = hw_counter / (u64) (AB3100_RTC_CLOCK_RATE * 2); 139 - 140 - rtc_time64_to_tm(time, &alarm->time); 141 - 142 - return rtc_valid_tm(&alarm->time); 143 - } 144 - 145 - static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 146 - { 147 - u8 regs[] = {AB3100_AL0, AB3100_AL1, AB3100_AL2, AB3100_AL3}; 148 - unsigned char buf[4]; 149 - time64_t secs; 150 - u64 hw_counter; 151 - int err; 152 - int i; 153 - 154 - secs = rtc_tm_to_time64(&alarm->time); 155 - hw_counter = secs * AB3100_RTC_CLOCK_RATE * 2; 156 - buf[0] = (hw_counter >> 16) & 0xFF; 157 - buf[1] = (hw_counter >> 24) & 0xFF; 158 - buf[2] = (hw_counter >> 32) & 0xFF; 159 - buf[3] = (hw_counter >> 40) & 0xFF; 160 - 161 - /* Set the alarm */ 162 - for (i = 0; i < 4; i++) { 163 - err = abx500_set_register_interruptible(dev, 0, 164 - regs[i], buf[i]); 165 - if (err) 166 - return err; 167 - } 168 - /* Then enable the alarm */ 169 - return abx500_mask_and_set_register_interruptible(dev, 0, 170 - AB3100_RTC, (1 << 2), 171 - alarm->enabled << 2); 172 - } 173 - 174 - static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled) 175 - { 176 - /* 177 - * It's not possible to enable/disable the alarm IRQ for this RTC. 178 - * It does not actually trigger any IRQ: instead its only function is 179 - * to power up the system, if it wasn't on. This will manifest as 180 - * a "power up cause" in the AB3100 power driver (battery charging etc) 181 - * and need to be handled there instead. 182 - */ 183 - if (enabled) 184 - return abx500_mask_and_set_register_interruptible(dev, 0, 185 - AB3100_RTC, (1 << 2), 186 - 1 << 2); 187 - else 188 - return abx500_mask_and_set_register_interruptible(dev, 0, 189 - AB3100_RTC, (1 << 2), 190 - 0); 191 - } 192 - 193 - static const struct rtc_class_ops ab3100_rtc_ops = { 194 - .read_time = ab3100_rtc_read_time, 195 - .set_time = ab3100_rtc_set_time, 196 - .read_alarm = ab3100_rtc_read_alarm, 197 - .set_alarm = ab3100_rtc_set_alarm, 198 - .alarm_irq_enable = ab3100_rtc_irq_enable, 199 - }; 200 - 201 - static int __init ab3100_rtc_probe(struct platform_device *pdev) 202 - { 203 - int err; 204 - u8 regval; 205 - struct rtc_device *rtc; 206 - 207 - /* The first RTC register needs special treatment */ 208 - err = abx500_get_register_interruptible(&pdev->dev, 0, 209 - AB3100_RTC, &regval); 210 - if (err) { 211 - dev_err(&pdev->dev, "unable to read RTC register\n"); 212 - return -ENODEV; 213 - } 214 - 215 - if ((regval & 0xFE) != RTC_SETTING) { 216 - dev_warn(&pdev->dev, "not default value in RTC reg 0x%x\n", 217 - regval); 218 - } 219 - 220 - if ((regval & 1) == 0) { 221 - /* 222 - * Set bit to detect power loss. 223 - * This bit remains until RTC power is lost. 224 - */ 225 - regval = 1 | RTC_SETTING; 226 - err = abx500_set_register_interruptible(&pdev->dev, 0, 227 - AB3100_RTC, regval); 228 - /* Ignore any error on this write */ 229 - } 230 - 231 - rtc = devm_rtc_allocate_device(&pdev->dev); 232 - if (IS_ERR(rtc)) 233 - return PTR_ERR(rtc); 234 - 235 - rtc->ops = &ab3100_rtc_ops; 236 - /* 48bit counter at (AB3100_RTC_CLOCK_RATE * 2) */ 237 - rtc->range_max = U32_MAX; 238 - 239 - platform_set_drvdata(pdev, rtc); 240 - 241 - return devm_rtc_register_device(rtc); 242 - } 243 - 244 - static struct platform_driver ab3100_rtc_driver = { 245 - .driver = { 246 - .name = "ab3100-rtc", 247 - }, 248 - }; 249 - 250 - module_platform_driver_probe(ab3100_rtc_driver, ab3100_rtc_probe); 251 - 252 - MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 253 - MODULE_DESCRIPTION("AB3100 RTC Driver"); 254 - MODULE_LICENSE("GPL");
+16 -23
drivers/rtc/rtc-abx80x.c
··· 117 117 struct watchdog_device wdog; 118 118 }; 119 119 120 + static int abx80x_write_config_key(struct i2c_client *client, u8 key) 121 + { 122 + if (i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, key) < 0) { 123 + dev_err(&client->dev, "Unable to write configuration key\n"); 124 + return -EIO; 125 + } 126 + 127 + return 0; 128 + } 129 + 120 130 static int abx80x_is_rc_mode(struct i2c_client *client) 121 131 { 122 132 int flags = 0; ··· 150 140 * Write the configuration key register to enable access to the Trickle 151 141 * register 152 142 */ 153 - err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, 154 - ABX8XX_CFG_KEY_MISC); 155 - if (err < 0) { 156 - dev_err(&client->dev, "Unable to write configuration key\n"); 143 + if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0) 157 144 return -EIO; 158 - } 159 145 160 146 err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE, 161 147 ABX8XX_TRICKLE_CHARGE_ENABLE | ··· 364 358 } 365 359 366 360 /* Unlock write access to Oscillator Control Register */ 367 - retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, 368 - ABX8XX_CFG_KEY_OSC); 369 - if (retval < 0) { 370 - dev_err(dev, "Failed to write CONFIG_KEY register\n"); 371 - return retval; 372 - } 361 + if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0) 362 + return -EIO; 373 363 374 364 retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags); 375 365 ··· 452 450 flags |= (ABX8XX_OSC_OSEL); 453 451 454 452 /* Unlock write access on Oscillator Control register */ 455 - retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, 456 - ABX8XX_CFG_KEY_OSC); 457 - if (retval < 0) { 458 - dev_err(dev, "Failed to write CONFIG_KEY register\n"); 459 - return retval; 460 - } 453 + if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0) 454 + return -EIO; 461 455 462 456 retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags); 463 457 if (retval < 0) { ··· 760 762 * Write the configuration key register to enable access to 761 763 * the config2 register 762 764 */ 763 - err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, 764 - ABX8XX_CFG_KEY_MISC); 765 - if (err < 0) { 766 - dev_err(&client->dev, 767 - "Unable to write configuration key\n"); 765 + if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0) 768 766 return -EIO; 769 - } 770 767 771 768 err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL, 772 769 data | ABX8XX_OUT_CTRL_EXDS);
+2 -2
drivers/rtc/rtc-ac100.c
··· 528 528 unsigned int val = 0; 529 529 int ret; 530 530 531 - mutex_lock(&chip->rtc->ops_lock); 531 + rtc_lock(chip->rtc); 532 532 533 533 /* read status */ 534 534 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val); ··· 551 551 } 552 552 553 553 out: 554 - mutex_unlock(&chip->rtc->ops_lock); 554 + rtc_unlock(chip->rtc); 555 555 return IRQ_HANDLED; 556 556 } 557 557
+4 -17
drivers/rtc/rtc-armada38x.c
··· 458 458 .set_offset = armada38x_rtc_set_offset, 459 459 }; 460 460 461 - static const struct rtc_class_ops armada38x_rtc_ops_noirq = { 462 - .read_time = armada38x_rtc_read_time, 463 - .set_time = armada38x_rtc_set_time, 464 - .read_alarm = armada38x_rtc_read_alarm, 465 - .read_offset = armada38x_rtc_read_offset, 466 - .set_offset = armada38x_rtc_set_offset, 467 - }; 468 - 469 461 static const struct armada38x_rtc_data armada38x_data = { 470 462 .update_mbus_timing = rtc_update_38x_mbus_timing_params, 471 463 .read_rtc_reg = read_rtc_register_38x_wa, ··· 532 540 } 533 541 platform_set_drvdata(pdev, rtc); 534 542 535 - if (rtc->irq != -1) { 543 + if (rtc->irq != -1) 536 544 device_init_wakeup(&pdev->dev, 1); 537 - rtc->rtc_dev->ops = &armada38x_rtc_ops; 538 - } else { 539 - /* 540 - * If there is no interrupt available then we can't 541 - * use the alarm 542 - */ 543 - rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq; 544 - } 545 + else 546 + clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features); 545 547 546 548 /* Update RTC-MBUS bridge timing parameters */ 547 549 rtc->data->update_mbus_timing(rtc); 548 550 551 + rtc->rtc_dev->ops = &armada38x_rtc_ops; 549 552 rtc->rtc_dev->range_max = U32_MAX; 550 553 551 554 return devm_rtc_register_device(rtc->rtc_dev);
+3 -3
drivers/rtc/rtc-asm9260.c
··· 116 116 u32 isr; 117 117 unsigned long events = 0; 118 118 119 - mutex_lock(&priv->rtc->ops_lock); 119 + rtc_lock(priv->rtc); 120 120 isr = ioread32(priv->iobase + HW_CIIR); 121 121 if (!isr) { 122 - mutex_unlock(&priv->rtc->ops_lock); 122 + rtc_unlock(priv->rtc); 123 123 return IRQ_NONE; 124 124 } 125 125 126 126 iowrite32(0, priv->iobase + HW_CIIR); 127 - mutex_unlock(&priv->rtc->ops_lock); 127 + rtc_unlock(priv->rtc); 128 128 129 129 events |= RTC_AF | RTC_IRQF; 130 130
+1 -1
drivers/rtc/rtc-bq32k.c
··· 311 311 }; 312 312 MODULE_DEVICE_TABLE(i2c, bq32k_id); 313 313 314 - static const struct of_device_id bq32k_of_match[] = { 314 + static const __maybe_unused struct of_device_id bq32k_of_match[] = { 315 315 { .compatible = "ti,bq32000" }, 316 316 { } 317 317 };
+1 -1
drivers/rtc/rtc-brcmstb-waketimer.c
··· 306 306 static SIMPLE_DEV_PM_OPS(brcmstb_waketmr_pm_ops, 307 307 brcmstb_waketmr_suspend, brcmstb_waketmr_resume); 308 308 309 - static const struct of_device_id brcmstb_waketmr_of_match[] = { 309 + static const __maybe_unused struct of_device_id brcmstb_waketmr_of_match[] = { 310 310 { .compatible = "brcm,brcmstb-waketimer" }, 311 311 { /* sentinel */ }, 312 312 };
+5 -12
drivers/rtc/rtc-cmos.c
··· 574 574 .alarm_irq_enable = cmos_alarm_irq_enable, 575 575 }; 576 576 577 - static const struct rtc_class_ops cmos_rtc_ops_no_alarm = { 578 - .read_time = cmos_read_time, 579 - .set_time = cmos_set_time, 580 - .proc = cmos_procfs, 581 - }; 582 - 583 577 /*----------------------------------------------------------------*/ 584 578 585 579 /* ··· 643 649 644 650 static irqreturn_t cmos_interrupt(int irq, void *p) 645 651 { 646 - unsigned long flags; 647 652 u8 irqstat; 648 653 u8 rtc_control; 649 654 650 - spin_lock_irqsave(&rtc_lock, flags); 655 + spin_lock(&rtc_lock); 651 656 652 657 /* When the HPET interrupt handler calls us, the interrupt 653 658 * status is passed as arg1 instead of the irq number. But ··· 680 687 hpet_mask_rtc_irq_bit(RTC_AIE); 681 688 CMOS_READ(RTC_INTR_FLAGS); 682 689 } 683 - spin_unlock_irqrestore(&rtc_lock, flags); 690 + spin_unlock(&rtc_lock); 684 691 685 692 if (is_intr(irqstat)) { 686 693 rtc_update_irq(p, 1, irqstat); ··· 858 865 dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); 859 866 goto cleanup1; 860 867 } 861 - 862 - cmos_rtc.rtc->ops = &cmos_rtc_ops; 863 868 } else { 864 - cmos_rtc.rtc->ops = &cmos_rtc_ops_no_alarm; 869 + clear_bit(RTC_FEATURE_ALARM, cmos_rtc.rtc->features); 865 870 } 871 + 872 + cmos_rtc.rtc->ops = &cmos_rtc_ops; 866 873 867 874 retval = devm_rtc_register_device(cmos_rtc.rtc); 868 875 if (retval)
-290
drivers/rtc/rtc-coh901331.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Copyright (C) 2007-2009 ST-Ericsson AB 4 - * Real Time Clock interface for ST-Ericsson AB COH 901 331 RTC. 5 - * Author: Linus Walleij <linus.walleij@stericsson.com> 6 - * Based on rtc-pl031.c by Deepak Saxena <dsaxena@plexity.net> 7 - * Copyright 2006 (c) MontaVista Software, Inc. 8 - */ 9 - #include <linux/init.h> 10 - #include <linux/module.h> 11 - #include <linux/mod_devicetable.h> 12 - #include <linux/rtc.h> 13 - #include <linux/clk.h> 14 - #include <linux/interrupt.h> 15 - #include <linux/pm.h> 16 - #include <linux/platform_device.h> 17 - #include <linux/io.h> 18 - #include <linux/slab.h> 19 - 20 - /* 21 - * Registers in the COH 901 331 22 - */ 23 - /* Alarm value 32bit (R/W) */ 24 - #define COH901331_ALARM 0x00U 25 - /* Used to set current time 32bit (R/W) */ 26 - #define COH901331_SET_TIME 0x04U 27 - /* Indication if current time is valid 32bit (R/-) */ 28 - #define COH901331_VALID 0x08U 29 - /* Read the current time 32bit (R/-) */ 30 - #define COH901331_CUR_TIME 0x0cU 31 - /* Event register for the "alarm" interrupt */ 32 - #define COH901331_IRQ_EVENT 0x10U 33 - /* Mask register for the "alarm" interrupt */ 34 - #define COH901331_IRQ_MASK 0x14U 35 - /* Force register for the "alarm" interrupt */ 36 - #define COH901331_IRQ_FORCE 0x18U 37 - 38 - /* 39 - * Reference to RTC block clock 40 - * Notice that the frequent clk_enable()/clk_disable() on this 41 - * clock is mainly to be able to turn on/off other clocks in the 42 - * hierarchy as needed, the RTC clock is always on anyway. 43 - */ 44 - struct coh901331_port { 45 - struct rtc_device *rtc; 46 - struct clk *clk; 47 - void __iomem *virtbase; 48 - int irq; 49 - #ifdef CONFIG_PM_SLEEP 50 - u32 irqmaskstore; 51 - #endif 52 - }; 53 - 54 - static irqreturn_t coh901331_interrupt(int irq, void *data) 55 - { 56 - struct coh901331_port *rtap = data; 57 - 58 - clk_enable(rtap->clk); 59 - /* Ack IRQ */ 60 - writel(1, rtap->virtbase + COH901331_IRQ_EVENT); 61 - /* 62 - * Disable the interrupt. This is necessary because 63 - * the RTC lives on a lower-clocked line and will 64 - * not release the IRQ line until after a few (slower) 65 - * clock cycles. The interrupt will be re-enabled when 66 - * a new alarm is set anyway. 67 - */ 68 - writel(0, rtap->virtbase + COH901331_IRQ_MASK); 69 - clk_disable(rtap->clk); 70 - 71 - /* Set alarm flag */ 72 - rtc_update_irq(rtap->rtc, 1, RTC_AF); 73 - 74 - return IRQ_HANDLED; 75 - } 76 - 77 - static int coh901331_read_time(struct device *dev, struct rtc_time *tm) 78 - { 79 - struct coh901331_port *rtap = dev_get_drvdata(dev); 80 - 81 - clk_enable(rtap->clk); 82 - /* Check if the time is valid */ 83 - if (!readl(rtap->virtbase + COH901331_VALID)) { 84 - clk_disable(rtap->clk); 85 - return -EINVAL; 86 - } 87 - 88 - rtc_time64_to_tm(readl(rtap->virtbase + COH901331_CUR_TIME), tm); 89 - clk_disable(rtap->clk); 90 - return 0; 91 - } 92 - 93 - static int coh901331_set_time(struct device *dev, struct rtc_time *tm) 94 - { 95 - struct coh901331_port *rtap = dev_get_drvdata(dev); 96 - 97 - clk_enable(rtap->clk); 98 - writel(rtc_tm_to_time64(tm), rtap->virtbase + COH901331_SET_TIME); 99 - clk_disable(rtap->clk); 100 - 101 - return 0; 102 - } 103 - 104 - static int coh901331_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 105 - { 106 - struct coh901331_port *rtap = dev_get_drvdata(dev); 107 - 108 - clk_enable(rtap->clk); 109 - rtc_time64_to_tm(readl(rtap->virtbase + COH901331_ALARM), &alarm->time); 110 - alarm->pending = readl(rtap->virtbase + COH901331_IRQ_EVENT) & 1U; 111 - alarm->enabled = readl(rtap->virtbase + COH901331_IRQ_MASK) & 1U; 112 - clk_disable(rtap->clk); 113 - 114 - return 0; 115 - } 116 - 117 - static int coh901331_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 118 - { 119 - struct coh901331_port *rtap = dev_get_drvdata(dev); 120 - unsigned long time = rtc_tm_to_time64(&alarm->time); 121 - 122 - clk_enable(rtap->clk); 123 - writel(time, rtap->virtbase + COH901331_ALARM); 124 - writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK); 125 - clk_disable(rtap->clk); 126 - 127 - return 0; 128 - } 129 - 130 - static int coh901331_alarm_irq_enable(struct device *dev, unsigned int enabled) 131 - { 132 - struct coh901331_port *rtap = dev_get_drvdata(dev); 133 - 134 - clk_enable(rtap->clk); 135 - if (enabled) 136 - writel(1, rtap->virtbase + COH901331_IRQ_MASK); 137 - else 138 - writel(0, rtap->virtbase + COH901331_IRQ_MASK); 139 - clk_disable(rtap->clk); 140 - 141 - return 0; 142 - } 143 - 144 - static const struct rtc_class_ops coh901331_ops = { 145 - .read_time = coh901331_read_time, 146 - .set_time = coh901331_set_time, 147 - .read_alarm = coh901331_read_alarm, 148 - .set_alarm = coh901331_set_alarm, 149 - .alarm_irq_enable = coh901331_alarm_irq_enable, 150 - }; 151 - 152 - static int __exit coh901331_remove(struct platform_device *pdev) 153 - { 154 - struct coh901331_port *rtap = platform_get_drvdata(pdev); 155 - 156 - if (rtap) 157 - clk_unprepare(rtap->clk); 158 - 159 - return 0; 160 - } 161 - 162 - 163 - static int __init coh901331_probe(struct platform_device *pdev) 164 - { 165 - int ret; 166 - struct coh901331_port *rtap; 167 - 168 - rtap = devm_kzalloc(&pdev->dev, 169 - sizeof(struct coh901331_port), GFP_KERNEL); 170 - if (!rtap) 171 - return -ENOMEM; 172 - 173 - rtap->virtbase = devm_platform_ioremap_resource(pdev, 0); 174 - if (IS_ERR(rtap->virtbase)) 175 - return PTR_ERR(rtap->virtbase); 176 - 177 - rtap->irq = platform_get_irq(pdev, 0); 178 - if (devm_request_irq(&pdev->dev, rtap->irq, coh901331_interrupt, 0, 179 - "RTC COH 901 331 Alarm", rtap)) 180 - return -EIO; 181 - 182 - rtap->clk = devm_clk_get(&pdev->dev, NULL); 183 - if (IS_ERR(rtap->clk)) { 184 - ret = PTR_ERR(rtap->clk); 185 - dev_err(&pdev->dev, "could not get clock\n"); 186 - return ret; 187 - } 188 - 189 - rtap->rtc = devm_rtc_allocate_device(&pdev->dev); 190 - if (IS_ERR(rtap->rtc)) 191 - return PTR_ERR(rtap->rtc); 192 - 193 - rtap->rtc->ops = &coh901331_ops; 194 - rtap->rtc->range_max = U32_MAX; 195 - 196 - /* We enable/disable the clock only to assure it works */ 197 - ret = clk_prepare_enable(rtap->clk); 198 - if (ret) { 199 - dev_err(&pdev->dev, "could not enable clock\n"); 200 - return ret; 201 - } 202 - clk_disable(rtap->clk); 203 - 204 - platform_set_drvdata(pdev, rtap); 205 - 206 - ret = devm_rtc_register_device(rtap->rtc); 207 - if (ret) 208 - goto out_no_rtc; 209 - 210 - return 0; 211 - 212 - out_no_rtc: 213 - clk_unprepare(rtap->clk); 214 - return ret; 215 - } 216 - 217 - #ifdef CONFIG_PM_SLEEP 218 - static int coh901331_suspend(struct device *dev) 219 - { 220 - struct coh901331_port *rtap = dev_get_drvdata(dev); 221 - 222 - /* 223 - * If this RTC alarm will be used for waking the system up, 224 - * don't disable it of course. Else we just disable the alarm 225 - * and await suspension. 226 - */ 227 - if (device_may_wakeup(dev)) { 228 - enable_irq_wake(rtap->irq); 229 - } else { 230 - clk_enable(rtap->clk); 231 - rtap->irqmaskstore = readl(rtap->virtbase + COH901331_IRQ_MASK); 232 - writel(0, rtap->virtbase + COH901331_IRQ_MASK); 233 - clk_disable(rtap->clk); 234 - } 235 - clk_unprepare(rtap->clk); 236 - return 0; 237 - } 238 - 239 - static int coh901331_resume(struct device *dev) 240 - { 241 - int ret; 242 - struct coh901331_port *rtap = dev_get_drvdata(dev); 243 - 244 - ret = clk_prepare(rtap->clk); 245 - if (ret) 246 - return ret; 247 - 248 - if (device_may_wakeup(dev)) { 249 - disable_irq_wake(rtap->irq); 250 - } else { 251 - clk_enable(rtap->clk); 252 - writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); 253 - clk_disable(rtap->clk); 254 - } 255 - return 0; 256 - } 257 - #endif 258 - 259 - static SIMPLE_DEV_PM_OPS(coh901331_pm_ops, coh901331_suspend, coh901331_resume); 260 - 261 - static void coh901331_shutdown(struct platform_device *pdev) 262 - { 263 - struct coh901331_port *rtap = platform_get_drvdata(pdev); 264 - 265 - clk_enable(rtap->clk); 266 - writel(0, rtap->virtbase + COH901331_IRQ_MASK); 267 - clk_disable_unprepare(rtap->clk); 268 - } 269 - 270 - static const struct of_device_id coh901331_dt_match[] = { 271 - { .compatible = "stericsson,coh901331" }, 272 - {}, 273 - }; 274 - MODULE_DEVICE_TABLE(of, coh901331_dt_match); 275 - 276 - static struct platform_driver coh901331_driver = { 277 - .driver = { 278 - .name = "rtc-coh901331", 279 - .pm = &coh901331_pm_ops, 280 - .of_match_table = coh901331_dt_match, 281 - }, 282 - .remove = __exit_p(coh901331_remove), 283 - .shutdown = coh901331_shutdown, 284 - }; 285 - 286 - module_platform_driver_probe(coh901331_driver, coh901331_probe); 287 - 288 - MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 289 - MODULE_DESCRIPTION("ST-Ericsson AB COH 901 331 RTC Driver"); 290 - MODULE_LICENSE("GPL");
+1 -1
drivers/rtc/rtc-digicolor.c
··· 205 205 return devm_rtc_register_device(rtc->rtc_dev); 206 206 } 207 207 208 - static const struct of_device_id dc_dt_ids[] = { 208 + static const __maybe_unused struct of_device_id dc_dt_ids[] = { 209 209 { .compatible = "cnxt,cx92755-rtc" }, 210 210 { /* sentinel */ } 211 211 };
+2 -3
drivers/rtc/rtc-ds1305.c
··· 435 435 static void ds1305_work(struct work_struct *work) 436 436 { 437 437 struct ds1305 *ds1305 = container_of(work, struct ds1305, work); 438 - struct mutex *lock = &ds1305->rtc->ops_lock; 439 438 struct spi_device *spi = ds1305->spi; 440 439 u8 buf[3]; 441 440 int status; 442 441 443 442 /* lock to protect ds1305->ctrl */ 444 - mutex_lock(lock); 443 + rtc_lock(ds1305->rtc); 445 444 446 445 /* Disable the IRQ, and clear its status ... for now, we "know" 447 446 * that if more than one alarm is active, they're in sync. ··· 458 459 if (status < 0) 459 460 dev_dbg(&spi->dev, "clear irq --> %d\n", status); 460 461 461 - mutex_unlock(lock); 462 + rtc_unlock(ds1305->rtc); 462 463 463 464 if (!test_bit(FLAG_EXITING, &ds1305->flags)) 464 465 enable_irq(spi->irq);
+2 -3
drivers/rtc/rtc-ds1307.c
··· 558 558 static irqreturn_t rx8130_irq(int irq, void *dev_id) 559 559 { 560 560 struct ds1307 *ds1307 = dev_id; 561 - struct mutex *lock = &ds1307->rtc->ops_lock; 562 561 u8 ctl[3]; 563 562 int ret; 564 563 565 - mutex_lock(lock); 564 + rtc_lock(ds1307->rtc); 566 565 567 566 /* Read control registers. */ 568 567 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, ··· 581 582 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 582 583 583 584 out: 584 - mutex_unlock(lock); 585 + rtc_unlock(ds1307->rtc); 585 586 586 587 return IRQ_HANDLED; 587 588 }
+1 -1
drivers/rtc/rtc-ds1672.c
··· 139 139 }; 140 140 MODULE_DEVICE_TABLE(i2c, ds1672_id); 141 141 142 - static const struct of_device_id ds1672_of_match[] = { 142 + static const __maybe_unused struct of_device_id ds1672_of_match[] = { 143 143 { .compatible = "dallas,ds1672" }, 144 144 { } 145 145 };
+2 -4
drivers/rtc/rtc-ds1685.c
··· 658 658 { 659 659 struct platform_device *pdev = dev_id; 660 660 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 661 - struct mutex *rtc_mutex; 662 661 u8 ctrlb, ctrlc; 663 662 unsigned long events = 0; 664 663 u8 num_irqs = 0; ··· 666 667 if (unlikely(!rtc)) 667 668 return IRQ_HANDLED; 668 669 669 - rtc_mutex = &rtc->dev->ops_lock; 670 - mutex_lock(rtc_mutex); 670 + rtc_lock(rtc->dev); 671 671 672 672 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ 673 673 ctrlb = rtc->read(rtc, RTC_CTRL_B); ··· 711 713 } 712 714 } 713 715 rtc_update_irq(rtc->dev, num_irqs, events); 714 - mutex_unlock(rtc_mutex); 716 + rtc_unlock(rtc->dev); 715 717 716 718 return events ? IRQ_HANDLED : IRQ_NONE; 717 719 }
+3 -4
drivers/rtc/rtc-ds3232.c
··· 406 406 { 407 407 struct device *dev = dev_id; 408 408 struct ds3232 *ds3232 = dev_get_drvdata(dev); 409 - struct mutex *lock = &ds3232->rtc->ops_lock; 410 409 int ret; 411 410 int stat, control; 412 411 413 - mutex_lock(lock); 412 + rtc_lock(ds3232->rtc); 414 413 415 414 ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat); 416 415 if (ret) ··· 447 448 } 448 449 449 450 unlock: 450 - mutex_unlock(lock); 451 + rtc_unlock(ds3232->rtc); 451 452 452 453 return IRQ_HANDLED; 453 454 } ··· 592 593 }; 593 594 MODULE_DEVICE_TABLE(i2c, ds3232_id); 594 595 595 - static const struct of_device_id ds3232_of_match[] = { 596 + static const __maybe_unused struct of_device_id ds3232_of_match[] = { 596 597 { .compatible = "dallas,ds3232" }, 597 598 { } 598 599 };
+2 -3
drivers/rtc/rtc-hym8563.c
··· 428 428 { 429 429 struct hym8563 *hym8563 = (struct hym8563 *)dev_id; 430 430 struct i2c_client *client = hym8563->client; 431 - struct mutex *lock = &hym8563->rtc->ops_lock; 432 431 int data, ret; 433 432 434 - mutex_lock(lock); 433 + rtc_lock(hym8563->rtc); 435 434 436 435 /* Clear the alarm flag */ 437 436 ··· 450 451 } 451 452 452 453 out: 453 - mutex_unlock(lock); 454 + rtc_unlock(hym8563->rtc); 454 455 return IRQ_HANDLED; 455 456 } 456 457
+1 -1
drivers/rtc/rtc-isl1208.c
··· 99 99 }; 100 100 MODULE_DEVICE_TABLE(i2c, isl1208_id); 101 101 102 - static const struct of_device_id isl1208_of_match[] = { 102 + static const __maybe_unused struct of_device_id isl1208_of_match[] = { 103 103 { .compatible = "isil,isl1208", .data = &isl1208_configs[TYPE_ISL1208] }, 104 104 { .compatible = "isil,isl1209", .data = &isl1208_configs[TYPE_ISL1209] }, 105 105 { .compatible = "isil,isl1218", .data = &isl1208_configs[TYPE_ISL1218] },
+12 -13
drivers/rtc/rtc-m41t80.c
··· 85 85 }; 86 86 MODULE_DEVICE_TABLE(i2c, m41t80_id); 87 87 88 - static const struct of_device_id m41t80_of_match[] = { 88 + static const __maybe_unused struct of_device_id m41t80_of_match[] = { 89 89 { 90 90 .compatible = "st,m41t62", 91 91 .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT) ··· 158 158 { 159 159 struct i2c_client *client = dev_id; 160 160 struct m41t80_data *m41t80 = i2c_get_clientdata(client); 161 - struct mutex *lock = &m41t80->rtc->ops_lock; 162 161 unsigned long events = 0; 163 162 int flags, flags_afe; 164 163 165 - mutex_lock(lock); 164 + rtc_lock(m41t80->rtc); 166 165 167 166 flags_afe = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); 168 167 if (flags_afe < 0) { 169 - mutex_unlock(lock); 168 + rtc_unlock(m41t80->rtc); 170 169 return IRQ_NONE; 171 170 } 172 171 173 172 flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); 174 173 if (flags <= 0) { 175 - mutex_unlock(lock); 174 + rtc_unlock(m41t80->rtc); 176 175 return IRQ_NONE; 177 176 } 178 177 ··· 188 189 flags_afe); 189 190 } 190 191 191 - mutex_unlock(lock); 192 + rtc_unlock(m41t80->rtc); 192 193 193 194 return IRQ_HANDLED; 194 195 } ··· 396 397 return 0; 397 398 } 398 399 399 - static struct rtc_class_ops m41t80_rtc_ops = { 400 + static const struct rtc_class_ops m41t80_rtc_ops = { 400 401 .read_time = m41t80_rtc_read_time, 401 402 .set_time = m41t80_rtc_set_time, 402 403 .proc = m41t80_rtc_proc, 404 + .read_alarm = m41t80_read_alarm, 405 + .set_alarm = m41t80_set_alarm, 406 + .alarm_irq_enable = m41t80_alarm_irq_enable, 403 407 }; 404 408 405 409 #ifdef CONFIG_PM_SLEEP ··· 915 913 wakeup_source = false; 916 914 } 917 915 } 918 - if (client->irq > 0 || wakeup_source) { 919 - m41t80_rtc_ops.read_alarm = m41t80_read_alarm; 920 - m41t80_rtc_ops.set_alarm = m41t80_set_alarm; 921 - m41t80_rtc_ops.alarm_irq_enable = m41t80_alarm_irq_enable; 922 - /* Enable the wakealarm */ 916 + if (client->irq > 0 || wakeup_source) 923 917 device_init_wakeup(&client->dev, true); 924 - } 918 + else 919 + clear_bit(RTC_FEATURE_ALARM, m41t80_data->rtc->features); 925 920 926 921 m41t80_data->rtc->ops = &m41t80_rtc_ops; 927 922 m41t80_data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
+8 -14
drivers/rtc/rtc-m48t59.c
··· 313 313 .alarm_irq_enable = m48t59_rtc_alarm_irq_enable, 314 314 }; 315 315 316 - static const struct rtc_class_ops m48t02_rtc_ops = { 317 - .read_time = m48t59_rtc_read_time, 318 - .set_time = m48t59_rtc_set_time, 319 - }; 320 - 321 316 static int m48t59_nvram_read(void *priv, unsigned int offset, void *val, 322 317 size_t size) 323 318 { ··· 361 366 struct m48t59_private *m48t59 = NULL; 362 367 struct resource *res; 363 368 int ret = -ENOMEM; 364 - const struct rtc_class_ops *ops; 365 369 struct nvmem_config nvmem_cfg = { 366 370 .name = "m48t59-", 367 371 .word_size = 1, ··· 432 438 if (ret) 433 439 return ret; 434 440 } 441 + 442 + m48t59->rtc = devm_rtc_allocate_device(&pdev->dev); 443 + if (IS_ERR(m48t59->rtc)) 444 + return PTR_ERR(m48t59->rtc); 445 + 435 446 switch (pdata->type) { 436 447 case M48T59RTC_TYPE_M48T59: 437 - ops = &m48t59_rtc_ops; 438 448 pdata->offset = 0x1ff0; 439 449 break; 440 450 case M48T59RTC_TYPE_M48T02: 441 - ops = &m48t02_rtc_ops; 451 + clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features); 442 452 pdata->offset = 0x7f0; 443 453 break; 444 454 case M48T59RTC_TYPE_M48T08: 445 - ops = &m48t02_rtc_ops; 455 + clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features); 446 456 pdata->offset = 0x1ff0; 447 457 break; 448 458 default: ··· 457 459 spin_lock_init(&m48t59->lock); 458 460 platform_set_drvdata(pdev, m48t59); 459 461 460 - m48t59->rtc = devm_rtc_allocate_device(&pdev->dev); 461 - if (IS_ERR(m48t59->rtc)) 462 - return PTR_ERR(m48t59->rtc); 463 - 464 - m48t59->rtc->ops = ops; 462 + m48t59->rtc->ops = &m48t59_rtc_ops; 465 463 466 464 nvmem_cfg.size = pdata->offset; 467 465 ret = devm_rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
+2 -3
drivers/rtc/rtc-mcp795.c
··· 350 350 { 351 351 struct spi_device *spi = data; 352 352 struct rtc_device *rtc = spi_get_drvdata(spi); 353 - struct mutex *lock = &rtc->ops_lock; 354 353 int ret; 355 354 356 - mutex_lock(lock); 355 + rtc_lock(rtc); 357 356 358 357 /* Disable alarm. 359 358 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit, ··· 364 365 "Failed to disable alarm in IRQ (ret=%d)\n", ret); 365 366 rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF); 366 367 367 - mutex_unlock(lock); 368 + rtc_unlock(rtc); 368 369 369 370 return IRQ_HANDLED; 370 371 }
+1 -1
drivers/rtc/rtc-meson.c
··· 380 380 return ret; 381 381 } 382 382 383 - static const struct of_device_id meson_rtc_dt_match[] = { 383 + static const __maybe_unused struct of_device_id meson_rtc_dt_match[] = { 384 384 { .compatible = "amlogic,meson6-rtc", }, 385 385 { .compatible = "amlogic,meson8-rtc", }, 386 386 { .compatible = "amlogic,meson8b-rtc", },
+4 -10
drivers/rtc/rtc-mv.c
··· 200 200 static const struct rtc_class_ops mv_rtc_ops = { 201 201 .read_time = mv_rtc_read_time, 202 202 .set_time = mv_rtc_set_time, 203 - }; 204 - 205 - static const struct rtc_class_ops mv_rtc_alarm_ops = { 206 - .read_time = mv_rtc_read_time, 207 - .set_time = mv_rtc_set_time, 208 203 .read_alarm = mv_rtc_read_alarm, 209 204 .set_alarm = mv_rtc_set_alarm, 210 205 .alarm_irq_enable = mv_rtc_alarm_irq_enable, ··· 263 268 } 264 269 } 265 270 266 - if (pdata->irq >= 0) { 271 + if (pdata->irq >= 0) 267 272 device_init_wakeup(&pdev->dev, 1); 268 - pdata->rtc->ops = &mv_rtc_alarm_ops; 269 - } else { 270 - pdata->rtc->ops = &mv_rtc_ops; 271 - } 273 + else 274 + clear_bit(RTC_FEATURE_ALARM, pdata->rtc->features); 272 275 276 + pdata->rtc->ops = &mv_rtc_ops; 273 277 pdata->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 274 278 pdata->rtc->range_max = RTC_TIMESTAMP_END_2099; 275 279
+2 -3
drivers/rtc/rtc-mxc.c
··· 189 189 struct platform_device *pdev = dev_id; 190 190 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 191 191 void __iomem *ioaddr = pdata->ioaddr; 192 - unsigned long flags; 193 192 u32 status; 194 193 u32 events = 0; 195 194 196 - spin_lock_irqsave(&pdata->rtc->irq_lock, flags); 195 + spin_lock(&pdata->rtc->irq_lock); 197 196 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); 198 197 /* clear interrupt sources */ 199 198 writew(status, ioaddr + RTC_RTCISR); ··· 208 209 events |= (RTC_PF | RTC_IRQF); 209 210 210 211 rtc_update_irq(pdata->rtc, 1, events); 211 - spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags); 212 + spin_unlock(&pdata->rtc->irq_lock); 212 213 213 214 return IRQ_HANDLED; 214 215 }
+3 -4
drivers/rtc/rtc-mxc_v2.c
··· 74 74 struct device *dev = dev_id; 75 75 struct mxc_rtc_data *pdata = dev_get_drvdata(dev); 76 76 void __iomem *ioaddr = pdata->ioaddr; 77 - unsigned long flags; 78 77 u32 lp_status; 79 78 u32 lp_cr; 80 79 81 - spin_lock_irqsave(&pdata->lock, flags); 80 + spin_lock(&pdata->lock); 82 81 if (clk_enable(pdata->clk)) { 83 - spin_unlock_irqrestore(&pdata->lock, flags); 82 + spin_unlock(&pdata->lock); 84 83 return IRQ_NONE; 85 84 } 86 85 ··· 103 104 104 105 mxc_rtc_sync_lp_locked(dev, ioaddr); 105 106 clk_disable(pdata->clk); 106 - spin_unlock_irqrestore(&pdata->lock, flags); 107 + spin_unlock(&pdata->lock); 107 108 return IRQ_HANDLED; 108 109 } 109 110
+16 -13
drivers/rtc/rtc-opal.c
··· 224 224 return enabled ? 0 : opal_set_tpo_time(dev, &alarm); 225 225 } 226 226 227 - static struct rtc_class_ops opal_rtc_ops = { 227 + static const struct rtc_class_ops opal_rtc_ops = { 228 228 .read_time = opal_get_rtc_time, 229 229 .set_time = opal_set_rtc_time, 230 + .read_alarm = opal_get_tpo_time, 231 + .set_alarm = opal_set_tpo_time, 232 + .alarm_irq_enable = opal_tpo_alarm_irq_enable, 230 233 }; 231 234 232 235 static int opal_rtc_probe(struct platform_device *pdev) 233 236 { 234 237 struct rtc_device *rtc; 235 238 236 - if (pdev->dev.of_node && 237 - (of_property_read_bool(pdev->dev.of_node, "wakeup-source") || 238 - of_property_read_bool(pdev->dev.of_node, "has-tpo")/* legacy */)) { 239 - device_set_wakeup_capable(&pdev->dev, true); 240 - opal_rtc_ops.read_alarm = opal_get_tpo_time; 241 - opal_rtc_ops.set_alarm = opal_set_tpo_time; 242 - opal_rtc_ops.alarm_irq_enable = opal_tpo_alarm_irq_enable; 243 - } 244 - 245 - rtc = devm_rtc_device_register(&pdev->dev, DRVNAME, &opal_rtc_ops, 246 - THIS_MODULE); 239 + rtc = devm_rtc_allocate_device(&pdev->dev); 247 240 if (IS_ERR(rtc)) 248 241 return PTR_ERR(rtc); 249 242 243 + if (pdev->dev.of_node && 244 + (of_property_read_bool(pdev->dev.of_node, "wakeup-source") || 245 + of_property_read_bool(pdev->dev.of_node, "has-tpo")/* legacy */)) 246 + device_set_wakeup_capable(&pdev->dev, true); 247 + else 248 + clear_bit(RTC_FEATURE_ALARM, rtc->features); 249 + 250 + rtc->ops = &opal_rtc_ops; 251 + rtc->range_min = RTC_TIMESTAMP_BEGIN_0000; 252 + rtc->range_max = RTC_TIMESTAMP_END_9999; 250 253 rtc->uie_unsupported = 1; 251 254 252 - return 0; 255 + return devm_rtc_register_device(rtc); 253 256 } 254 257 255 258 static const struct of_device_id opal_rtc_match[] = {
+2 -3
drivers/rtc/rtc-pcf2123.c
··· 307 307 static irqreturn_t pcf2123_rtc_irq(int irq, void *dev) 308 308 { 309 309 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev); 310 - struct mutex *lock = &pcf2123->rtc->ops_lock; 311 310 unsigned int val = 0; 312 311 int ret = IRQ_NONE; 313 312 314 - mutex_lock(lock); 313 + rtc_lock(pcf2123->rtc); 315 314 regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val); 316 315 317 316 /* Alarm? */ ··· 323 324 rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF); 324 325 } 325 326 326 - mutex_unlock(lock); 327 + rtc_unlock(pcf2123->rtc); 327 328 328 329 return ret; 329 330 }
+35 -11
drivers/rtc/rtc-pcf2127.c
··· 26 26 27 27 /* Control register 1 */ 28 28 #define PCF2127_REG_CTRL1 0x00 29 + #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 29 30 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 30 31 /* Control register 2 */ 31 32 #define PCF2127_REG_CTRL2 0x01 ··· 58 57 #define PCF2127_REG_ALARM_DM 0x0D 59 58 #define PCF2127_REG_ALARM_DW 0x0E 60 59 #define PCF2127_BIT_ALARM_AE BIT(7) 60 + /* CLKOUT control register */ 61 + #define PCF2127_REG_CLKOUT 0x0f 62 + #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 61 63 /* Watchdog registers */ 62 64 #define PCF2127_REG_WD_CTL 0x10 63 65 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) ··· 228 224 return -ENOIOCTLCMD; 229 225 } 230 226 } 231 - 232 - static const struct rtc_class_ops pcf2127_rtc_ops = { 233 - .ioctl = pcf2127_rtc_ioctl, 234 - .read_time = pcf2127_rtc_read_time, 235 - .set_time = pcf2127_rtc_set_time, 236 - }; 237 227 238 228 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 239 229 void *val, size_t bytes) ··· 457 459 return IRQ_HANDLED; 458 460 } 459 461 460 - static const struct rtc_class_ops pcf2127_rtc_alrm_ops = { 462 + static const struct rtc_class_ops pcf2127_rtc_ops = { 461 463 .ioctl = pcf2127_rtc_ioctl, 462 464 .read_time = pcf2127_rtc_read_time, 463 465 .set_time = pcf2127_rtc_set_time, ··· 558 560 }; 559 561 560 562 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 561 - int alarm_irq, const char *name, bool has_nvmem) 563 + int alarm_irq, const char *name, bool is_pcf2127) 562 564 { 563 565 struct pcf2127 *pcf2127; 564 566 int ret = 0; 567 + unsigned int val; 565 568 566 569 dev_dbg(dev, "%s\n", __func__); 567 570 ··· 583 584 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 584 585 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 585 586 pcf2127->rtc->uie_unsupported = 1; 587 + clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 586 588 587 589 if (alarm_irq > 0) { 588 590 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, ··· 598 598 599 599 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 600 600 device_init_wakeup(dev, true); 601 - pcf2127->rtc->ops = &pcf2127_rtc_alrm_ops; 601 + set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 602 602 } 603 603 604 - if (has_nvmem) { 604 + if (is_pcf2127) { 605 605 struct nvmem_config nvmem_cfg = { 606 606 .priv = pcf2127, 607 607 .reg_read = pcf2127_nvmem_read, ··· 613 613 } 614 614 615 615 /* 616 + * The "Power-On Reset Override" facility prevents the RTC to do a reset 617 + * after power on. For normal operation the PORO must be disabled. 618 + */ 619 + regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 620 + PCF2127_BIT_CTRL1_POR_OVRD); 621 + 622 + ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 623 + if (ret < 0) 624 + return ret; 625 + 626 + if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 627 + ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 628 + PCF2127_BIT_CLKOUT_OTPR); 629 + if (ret < 0) 630 + return ret; 631 + 632 + msleep(100); 633 + } 634 + 635 + /* 616 636 * Watchdog timer enabled and reset pin /RST activated when timed out. 617 637 * Select 1Hz clock source for watchdog timer. 618 638 * Note: Countdown timer disabled and not available. 639 + * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 640 + * of register watchdg_tim_ctl. The bit[6] is labeled 641 + * as T. Bits labeled as T must always be written with 642 + * logic 0. 619 643 */ 620 644 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 621 645 PCF2127_BIT_WD_CTL_CD1 | ··· 647 623 PCF2127_BIT_WD_CTL_TF1 | 648 624 PCF2127_BIT_WD_CTL_TF0, 649 625 PCF2127_BIT_WD_CTL_CD1 | 650 - PCF2127_BIT_WD_CTL_CD0 | 626 + (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 651 627 PCF2127_BIT_WD_CTL_TF1); 652 628 if (ret) { 653 629 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
+21 -28
drivers/rtc/rtc-pcf85063.c
··· 311 311 .set_time = pcf85063_rtc_set_time, 312 312 .read_offset = pcf85063_read_offset, 313 313 .set_offset = pcf85063_set_offset, 314 - .ioctl = pcf85063_ioctl, 315 - }; 316 - 317 - static const struct rtc_class_ops pcf85063_rtc_ops_alarm = { 318 - .read_time = pcf85063_rtc_read_time, 319 - .set_time = pcf85063_rtc_set_time, 320 - .read_offset = pcf85063_read_offset, 321 - .set_offset = pcf85063_set_offset, 322 314 .read_alarm = pcf85063_rtc_read_alarm, 323 315 .set_alarm = pcf85063_rtc_set_alarm, 324 316 .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable, ··· 501 509 } 502 510 #endif 503 511 504 - static const struct pcf85063_config pcf85063a_config = { 505 - .regmap = { 506 - .reg_bits = 8, 507 - .val_bits = 8, 508 - .max_register = 0x11, 509 - }, 510 - .has_alarms = 1, 511 - }; 512 - 513 512 static const struct pcf85063_config pcf85063tp_config = { 514 513 .regmap = { 515 514 .reg_bits = 8, 516 515 .val_bits = 8, 517 516 .max_register = 0x0a, 518 517 }, 519 - }; 520 - 521 - static const struct pcf85063_config rv8263_config = { 522 - .regmap = { 523 - .reg_bits = 8, 524 - .val_bits = 8, 525 - .max_register = 0x11, 526 - }, 527 - .has_alarms = 1, 528 - .force_cap_7000 = 1, 529 518 }; 530 519 531 520 static int pcf85063_probe(struct i2c_client *client) ··· 560 587 pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 561 588 pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099; 562 589 pcf85063->rtc->uie_unsupported = 1; 590 + clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features); 563 591 564 592 if (config->has_alarms && client->irq > 0) { 565 593 err = devm_request_threaded_irq(&client->dev, client->irq, ··· 571 597 dev_warn(&pcf85063->rtc->dev, 572 598 "unable to request IRQ, alarms disabled\n"); 573 599 } else { 574 - pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm; 600 + set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features); 575 601 device_init_wakeup(&client->dev, true); 576 602 err = dev_pm_set_wake_irq(&client->dev, client->irq); 577 603 if (err) ··· 592 618 } 593 619 594 620 #ifdef CONFIG_OF 621 + static const struct pcf85063_config pcf85063a_config = { 622 + .regmap = { 623 + .reg_bits = 8, 624 + .val_bits = 8, 625 + .max_register = 0x11, 626 + }, 627 + .has_alarms = 1, 628 + }; 629 + 630 + static const struct pcf85063_config rv8263_config = { 631 + .regmap = { 632 + .reg_bits = 8, 633 + .val_bits = 8, 634 + .max_register = 0x11, 635 + }, 636 + .has_alarms = 1, 637 + .force_cap_7000 = 1, 638 + }; 639 + 595 640 static const struct of_device_id pcf85063_of_match[] = { 596 641 { .compatible = "nxp,pcf85063", .data = &pcf85063tp_config }, 597 642 { .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
+3 -7
drivers/rtc/rtc-pcf85363.c
··· 285 285 static const struct rtc_class_ops rtc_ops = { 286 286 .read_time = pcf85363_rtc_read_time, 287 287 .set_time = pcf85363_rtc_set_time, 288 - }; 289 - 290 - static const struct rtc_class_ops rtc_ops_alarm = { 291 - .read_time = pcf85363_rtc_read_time, 292 - .set_time = pcf85363_rtc_set_time, 293 288 .read_alarm = pcf85363_rtc_read_alarm, 294 289 .set_alarm = pcf85363_rtc_set_alarm, 295 290 .alarm_irq_enable = pcf85363_rtc_alarm_irq_enable, ··· 398 403 pcf85363->rtc->ops = &rtc_ops; 399 404 pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 400 405 pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099; 406 + clear_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features); 401 407 402 408 if (client->irq > 0) { 403 409 regmap_write(pcf85363->regmap, CTRL_FLAGS, 0); ··· 411 415 if (ret) 412 416 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); 413 417 else 414 - pcf85363->rtc->ops = &rtc_ops_alarm; 418 + set_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features); 415 419 } 416 420 417 421 ret = devm_rtc_register_device(pcf85363->rtc); ··· 424 428 return ret; 425 429 } 426 430 427 - static const struct of_device_id dev_ids[] = { 431 + static const __maybe_unused struct of_device_id dev_ids[] = { 428 432 { .compatible = "nxp,pcf85263", .data = &pcf_85263_config }, 429 433 { .compatible = "nxp,pcf85363", .data = &pcf_85363_config }, 430 434 { /* sentinel */ }
+2
drivers/rtc/rtc-pcf8563.c
··· 597 597 static const struct i2c_device_id pcf8563_id[] = { 598 598 { "pcf8563", 0 }, 599 599 { "rtc8564", 0 }, 600 + { "pca8565", 0 }, 600 601 { } 601 602 }; 602 603 MODULE_DEVICE_TABLE(i2c, pcf8563_id); ··· 607 606 { .compatible = "nxp,pcf8563" }, 608 607 { .compatible = "epson,rtc8564" }, 609 608 { .compatible = "microcrystal,rv8564" }, 609 + { .compatible = "nxp,pca8565" }, 610 610 {} 611 611 }; 612 612 MODULE_DEVICE_TABLE(of, pcf8563_of_match);
+2 -6
drivers/rtc/rtc-pl031.c
··· 352 352 } 353 353 } 354 354 355 - if (!adev->irq[0]) { 356 - /* When there's no interrupt, no point in exposing the alarm */ 357 - ops->read_alarm = NULL; 358 - ops->set_alarm = NULL; 359 - ops->alarm_irq_enable = NULL; 360 - } 355 + if (!adev->irq[0]) 356 + clear_bit(RTC_FEATURE_ALARM, ldata->rtc->features); 361 357 362 358 device_init_wakeup(&adev->dev, true); 363 359 ldata->rtc = devm_rtc_allocate_device(&adev->dev);
+13 -5
drivers/rtc/rtc-pm8xxx.c
··· 20 20 /* RTC_CTRL register bit fields */ 21 21 #define PM8xxx_RTC_ENABLE BIT(7) 22 22 #define PM8xxx_RTC_ALARM_CLEAR BIT(0) 23 + #define PM8xxx_RTC_ALARM_ENABLE BIT(7) 23 24 24 25 #define NUM_8_BIT_RTC_REGS 0x4 25 26 ··· 266 265 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 267 266 { 268 267 int rc; 268 + unsigned int ctrl_reg; 269 269 u8 value[NUM_8_BIT_RTC_REGS]; 270 270 unsigned long secs; 271 271 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); ··· 283 281 ((unsigned long)value[3] << 24); 284 282 285 283 rtc_time64_to_tm(secs, &alarm->time); 284 + 285 + rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 286 + if (rc) { 287 + dev_err(dev, "Read from RTC alarm control register failed\n"); 288 + return rc; 289 + } 290 + alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE); 286 291 287 292 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n", 288 293 &alarm->time, &alarm->time); ··· 352 343 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 353 344 unsigned int ctrl_reg; 354 345 int rc; 355 - unsigned long irq_flags; 356 346 357 347 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); 358 348 359 - spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 349 + spin_lock(&rtc_dd->ctrl_reg_lock); 360 350 361 351 /* Clear the alarm enable bit */ 362 352 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 363 353 if (rc) { 364 - spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 354 + spin_unlock(&rtc_dd->ctrl_reg_lock); 365 355 goto rtc_alarm_handled; 366 356 } 367 357 ··· 368 360 369 361 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 370 362 if (rc) { 371 - spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 363 + spin_unlock(&rtc_dd->ctrl_reg_lock); 372 364 dev_err(rtc_dd->rtc_dev, 373 365 "Write to alarm control register failed\n"); 374 366 goto rtc_alarm_handled; 375 367 } 376 368 377 - spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 369 + spin_unlock(&rtc_dd->ctrl_reg_lock); 378 370 379 371 /* Clear RTC alarm register */ 380 372 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
+2 -3
drivers/rtc/rtc-r7301.c
··· 320 320 { 321 321 struct rtc_device *rtc = dev_id; 322 322 struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent); 323 - unsigned long flags; 324 323 irqreturn_t ret = IRQ_NONE; 325 324 u8 alrm_ctrl; 326 325 327 - spin_lock_irqsave(&priv->lock, flags); 326 + spin_lock(&priv->lock); 328 327 329 328 rtc7301_select_bank(priv, 1); 330 329 ··· 334 335 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF); 335 336 } 336 337 337 - spin_unlock_irqrestore(&priv->lock, flags); 338 + spin_unlock(&priv->lock); 338 339 339 340 return ret; 340 341 }
+1 -1
drivers/rtc/rtc-rs5c372.c
··· 83 83 }; 84 84 MODULE_DEVICE_TABLE(i2c, rs5c372_id); 85 85 86 - static const struct of_device_id rs5c372_of_match[] = { 86 + static const __maybe_unused struct of_device_id rs5c372_of_match[] = { 87 87 { 88 88 .compatible = "ricoh,r2025sd", 89 89 .data = (void *)rtc_r2025sd
+9 -14
drivers/rtc/rtc-rv3028.c
··· 265 265 return IRQ_NONE; 266 266 } 267 267 268 - if (status & RV3028_STATUS_PORF) 269 - dev_warn(&rv3028->rtc->dev, "Voltage low, data loss detected.\n"); 268 + status &= ~RV3028_STATUS_PORF; 270 269 271 270 if (status & RV3028_STATUS_TF) { 272 271 status |= RV3028_STATUS_TF; ··· 310 311 if (ret < 0) 311 312 return ret; 312 313 313 - if (status & RV3028_STATUS_PORF) { 314 - dev_warn(dev, "Voltage low, data is invalid.\n"); 314 + if (status & RV3028_STATUS_PORF) 315 315 return -EINVAL; 316 - } 317 316 318 317 ret = regmap_bulk_read(rv3028->regmap, RV3028_SEC, date, sizeof(date)); 319 318 if (ret) ··· 767 770 } 768 771 #endif 769 772 770 - static struct rtc_class_ops rv3028_rtc_ops = { 773 + static const struct rtc_class_ops rv3028_rtc_ops = { 771 774 .read_time = rv3028_get_time, 772 775 .set_time = rv3028_set_time, 776 + .read_alarm = rv3028_get_alarm, 777 + .set_alarm = rv3028_set_alarm, 778 + .alarm_irq_enable = rv3028_alarm_irq_enable, 773 779 .read_offset = rv3028_read_offset, 774 780 .set_offset = rv3028_set_offset, 775 781 .ioctl = rv3028_ioctl, ··· 823 823 if (ret < 0) 824 824 return ret; 825 825 826 - if (status & RV3028_STATUS_PORF) 827 - dev_warn(&client->dev, "Voltage low, data loss detected.\n"); 828 - 829 826 if (status & RV3028_STATUS_AF) 830 827 dev_warn(&client->dev, "An alarm may have been missed.\n"); 831 828 ··· 838 841 if (ret) { 839 842 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); 840 843 client->irq = 0; 841 - } else { 842 - rv3028_rtc_ops.read_alarm = rv3028_get_alarm; 843 - rv3028_rtc_ops.set_alarm = rv3028_set_alarm; 844 - rv3028_rtc_ops.alarm_irq_enable = rv3028_alarm_irq_enable; 845 844 } 846 845 } 846 + if (!client->irq) 847 + clear_bit(RTC_FEATURE_ALARM, rv3028->rtc->features); 847 848 848 849 ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1, 849 850 RV3028_CTRL1_WADA, RV3028_CTRL1_WADA); ··· 898 903 return 0; 899 904 } 900 905 901 - static const struct of_device_id rv3028_of_match[] = { 906 + static const __maybe_unused struct of_device_id rv3028_of_match[] = { 902 907 { .compatible = "microcrystal,rv3028", }, 903 908 { } 904 909 };
+11 -11
drivers/rtc/rtc-rv3029c2.c
··· 265 265 { 266 266 struct device *dev = dev_id; 267 267 struct rv3029_data *rv3029 = dev_get_drvdata(dev); 268 - struct mutex *lock = &rv3029->rtc->ops_lock; 269 268 unsigned int flags, controls; 270 269 unsigned long events = 0; 271 270 int ret; 272 271 273 - mutex_lock(lock); 272 + rtc_lock(rv3029->rtc); 274 273 275 274 ret = regmap_read(rv3029->regmap, RV3029_IRQ_CTRL, &controls); 276 275 if (ret) { 277 276 dev_warn(dev, "Read IRQ Control Register error %d\n", ret); 278 - mutex_unlock(lock); 277 + rtc_unlock(rv3029->rtc); 279 278 return IRQ_NONE; 280 279 } 281 280 282 281 ret = regmap_read(rv3029->regmap, RV3029_IRQ_FLAGS, &flags); 283 282 if (ret) { 284 283 dev_warn(dev, "Read IRQ Flags Register error %d\n", ret); 285 - mutex_unlock(lock); 284 + rtc_unlock(rv3029->rtc); 286 285 return IRQ_NONE; 287 286 } 288 287 ··· 296 297 regmap_write(rv3029->regmap, RV3029_IRQ_FLAGS, flags); 297 298 regmap_write(rv3029->regmap, RV3029_IRQ_CTRL, controls); 298 299 } 299 - mutex_unlock(lock); 300 + rtc_unlock(rv3029->rtc); 300 301 301 302 return IRQ_HANDLED; 302 303 } ··· 693 694 694 695 #endif /* CONFIG_RTC_DRV_RV3029_HWMON */ 695 696 696 - static struct rtc_class_ops rv3029_rtc_ops = { 697 + static const struct rtc_class_ops rv3029_rtc_ops = { 697 698 .read_time = rv3029_read_time, 698 699 .set_time = rv3029_set_time, 699 700 .ioctl = rv3029_ioctl, 701 + .read_alarm = rv3029_read_alarm, 702 + .set_alarm = rv3029_set_alarm, 703 + .alarm_irq_enable = rv3029_alarm_irq_enable, 700 704 }; 701 705 702 706 static int rv3029_probe(struct device *dev, struct regmap *regmap, int irq, ··· 741 739 if (rc) { 742 740 dev_warn(dev, "unable to request IRQ, alarms disabled\n"); 743 741 rv3029->irq = 0; 744 - } else { 745 - rv3029_rtc_ops.read_alarm = rv3029_read_alarm; 746 - rv3029_rtc_ops.set_alarm = rv3029_set_alarm; 747 - rv3029_rtc_ops.alarm_irq_enable = rv3029_alarm_irq_enable; 748 742 } 749 743 } 744 + if (!rv3029->irq) 745 + clear_bit(RTC_FEATURE_ALARM, rv3029->rtc->features); 750 746 751 747 rv3029->rtc->ops = &rv3029_rtc_ops; 752 748 rv3029->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; ··· 808 808 }; 809 809 MODULE_DEVICE_TABLE(i2c, rv3029_id); 810 810 811 - static const struct of_device_id rv3029_of_match[] = { 811 + static const __maybe_unused struct of_device_id rv3029_of_match[] = { 812 812 { .compatible = "microcrystal,rv3029" }, 813 813 { } 814 814 };
+7 -6
drivers/rtc/rtc-rv3032.c
··· 804 804 devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL); 805 805 } 806 806 807 - static struct rtc_class_ops rv3032_rtc_ops = { 807 + static const struct rtc_class_ops rv3032_rtc_ops = { 808 808 .read_time = rv3032_get_time, 809 809 .set_time = rv3032_set_time, 810 810 .read_offset = rv3032_read_offset, 811 811 .set_offset = rv3032_set_offset, 812 812 .ioctl = rv3032_ioctl, 813 + .read_alarm = rv3032_get_alarm, 814 + .set_alarm = rv3032_set_alarm, 815 + .alarm_irq_enable = rv3032_alarm_irq_enable, 813 816 }; 814 817 815 818 static const struct regmap_config regmap_config = { ··· 871 868 if (ret) { 872 869 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); 873 870 client->irq = 0; 874 - } else { 875 - rv3032_rtc_ops.read_alarm = rv3032_get_alarm; 876 - rv3032_rtc_ops.set_alarm = rv3032_set_alarm; 877 - rv3032_rtc_ops.alarm_irq_enable = rv3032_alarm_irq_enable; 878 871 } 879 872 } 873 + if (!client->irq) 874 + clear_bit(RTC_FEATURE_ALARM, rv3032->rtc->features); 880 875 881 876 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1, 882 877 RV3032_CTRL1_WADA, RV3032_CTRL1_WADA); ··· 906 905 return 0; 907 906 } 908 907 909 - static const struct of_device_id rv3032_of_match[] = { 908 + static const __maybe_unused struct of_device_id rv3032_of_match[] = { 910 909 { .compatible = "microcrystal,rv3032", }, 911 910 { } 912 911 };
+7 -6
drivers/rtc/rtc-rv8803.c
··· 471 471 return 0; 472 472 } 473 473 474 - static struct rtc_class_ops rv8803_rtc_ops = { 474 + static const struct rtc_class_ops rv8803_rtc_ops = { 475 475 .read_time = rv8803_get_time, 476 476 .set_time = rv8803_set_time, 477 477 .ioctl = rv8803_ioctl, 478 + .read_alarm = rv8803_get_alarm, 479 + .set_alarm = rv8803_set_alarm, 480 + .alarm_irq_enable = rv8803_alarm_irq_enable, 478 481 }; 479 482 480 483 static int rx8900_trickle_charger_init(struct rv8803_data *rv8803) ··· 570 567 if (err) { 571 568 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); 572 569 client->irq = 0; 573 - } else { 574 - rv8803_rtc_ops.read_alarm = rv8803_get_alarm; 575 - rv8803_rtc_ops.set_alarm = rv8803_set_alarm; 576 - rv8803_rtc_ops.alarm_irq_enable = rv8803_alarm_irq_enable; 577 570 } 578 571 } 572 + if (!client->irq) 573 + clear_bit(RTC_FEATURE_ALARM, rv8803->rtc->features); 579 574 580 575 err = rv8803_write_reg(rv8803->client, RV8803_EXT, RV8803_EXT_WADA); 581 576 if (err) ··· 607 606 }; 608 607 MODULE_DEVICE_TABLE(i2c, rv8803_id); 609 608 610 - static const struct of_device_id rv8803_of_match[] = { 609 + static const __maybe_unused struct of_device_id rv8803_of_match[] = { 611 610 { 612 611 .compatible = "microcrystal,rv8803", 613 612 .data = (void *)rv_8803
+2 -2
drivers/rtc/rtc-rx6110.c
··· 331 331 return 0; 332 332 } 333 333 334 - #ifdef CONFIG_SPI_MASTER 334 + #if IS_ENABLED(CONFIG_SPI_MASTER) 335 335 static struct regmap_config regmap_spi_config = { 336 336 .reg_bits = 8, 337 337 .val_bits = 8, ··· 411 411 } 412 412 #endif /* CONFIG_SPI_MASTER */ 413 413 414 - #ifdef CONFIG_I2C 414 + #if IS_ENABLED(CONFIG_I2C) 415 415 static struct regmap_config regmap_i2c_config = { 416 416 .reg_bits = 8, 417 417 .val_bits = 8,
+7 -14
drivers/rtc/rtc-rx8010.c
··· 55 55 }; 56 56 MODULE_DEVICE_TABLE(i2c, rx8010_id); 57 57 58 - static const struct of_device_id rx8010_of_match[] = { 58 + static const __maybe_unused struct of_device_id rx8010_of_match[] = { 59 59 { .compatible = "epson,rx8010" }, 60 60 { } 61 61 }; ··· 73 73 struct rx8010_data *rx8010 = i2c_get_clientdata(client); 74 74 int flagreg, err; 75 75 76 - mutex_lock(&rx8010->rtc->ops_lock); 76 + rtc_lock(rx8010->rtc); 77 77 78 78 err = regmap_read(rx8010->regs, RX8010_FLAG, &flagreg); 79 79 if (err) { 80 - mutex_unlock(&rx8010->rtc->ops_lock); 80 + rtc_unlock(rx8010->rtc); 81 81 return IRQ_NONE; 82 82 } 83 83 ··· 100 100 } 101 101 102 102 err = regmap_write(rx8010->regs, RX8010_FLAG, flagreg); 103 - mutex_unlock(&rx8010->rtc->ops_lock); 103 + rtc_unlock(rx8010->rtc); 104 104 return err ? IRQ_NONE : IRQ_HANDLED; 105 105 } 106 106 ··· 354 354 } 355 355 } 356 356 357 - static const struct rtc_class_ops rx8010_rtc_ops_default = { 358 - .read_time = rx8010_get_time, 359 - .set_time = rx8010_set_time, 360 - .ioctl = rx8010_ioctl, 361 - }; 362 - 363 - static const struct rtc_class_ops rx8010_rtc_ops_alarm = { 357 + static const struct rtc_class_ops rx8010_rtc_ops = { 364 358 .read_time = rx8010_get_time, 365 359 .set_time = rx8010_set_time, 366 360 .ioctl = rx8010_ioctl, ··· 403 409 dev_err(dev, "unable to request IRQ\n"); 404 410 return err; 405 411 } 406 - 407 - rx8010->rtc->ops = &rx8010_rtc_ops_alarm; 408 412 } else { 409 - rx8010->rtc->ops = &rx8010_rtc_ops_default; 413 + clear_bit(RTC_FEATURE_ALARM, rx8010->rtc->features); 410 414 } 411 415 416 + rx8010->rtc->ops = &rx8010_rtc_ops; 412 417 rx8010->rtc->max_user_freq = 1; 413 418 rx8010->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 414 419 rx8010->rtc->range_max = RTC_TIMESTAMP_END_2099;
+2 -3
drivers/rtc/rtc-rx8025.c
··· 142 142 { 143 143 struct i2c_client *client = dev_id; 144 144 struct rx8025_data *rx8025 = i2c_get_clientdata(client); 145 - struct mutex *lock = &rx8025->rtc->ops_lock; 146 145 int status; 147 146 148 - mutex_lock(lock); 147 + rtc_lock(rx8025->rtc); 149 148 status = rx8025_read_reg(client, RX8025_REG_CTRL2); 150 149 if (status < 0) 151 150 goto out; ··· 169 170 } 170 171 171 172 out: 172 - mutex_unlock(lock); 173 + rtc_unlock(rx8025->rtc); 173 174 174 175 return IRQ_HANDLED; 175 176 }
+1 -1
drivers/rtc/rtc-rx8581.c
··· 314 314 }; 315 315 MODULE_DEVICE_TABLE(i2c, rx8581_id); 316 316 317 - static const struct of_device_id rx8581_of_match[] = { 317 + static const __maybe_unused struct of_device_id rx8581_of_match[] = { 318 318 { .compatible = "epson,rx8571", .data = &rx8571_config }, 319 319 { .compatible = "epson,rx8581", .data = &rx8581_config }, 320 320 { /* sentinel */ }
+1 -1
drivers/rtc/rtc-s35390a.c
··· 55 55 }; 56 56 MODULE_DEVICE_TABLE(i2c, s35390a_id); 57 57 58 - static const struct of_device_id s35390a_of_match[] = { 58 + static const __maybe_unused struct of_device_id s35390a_of_match[] = { 59 59 { .compatible = "s35390a" }, 60 60 { .compatible = "sii,s35390a" }, 61 61 { }
+1 -16
drivers/rtc/rtc-s3c.c
··· 382 382 static int s3c_rtc_probe(struct platform_device *pdev) 383 383 { 384 384 struct s3c_rtc *info = NULL; 385 - struct rtc_time rtc_tm; 386 385 int ret; 387 386 388 387 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); ··· 446 447 readw(info->base + S3C2410_RTCCON)); 447 448 448 449 device_init_wakeup(&pdev->dev, 1); 449 - 450 - /* Check RTC Time */ 451 - if (s3c_rtc_gettime(&pdev->dev, &rtc_tm)) { 452 - rtc_tm.tm_year = 100; 453 - rtc_tm.tm_mon = 0; 454 - rtc_tm.tm_mday = 1; 455 - rtc_tm.tm_hour = 0; 456 - rtc_tm.tm_min = 0; 457 - rtc_tm.tm_sec = 0; 458 - 459 - s3c_rtc_settime(&pdev->dev, &rtc_tm); 460 - 461 - dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); 462 - } 463 450 464 451 /* register RTC and exit */ 465 452 info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, ··· 558 573 .disable = s3c6410_rtc_disable, 559 574 }; 560 575 561 - static const struct of_device_id s3c_rtc_dt_match[] = { 576 + static const __maybe_unused struct of_device_id s3c_rtc_dt_match[] = { 562 577 { 563 578 .compatible = "samsung,s3c2410-rtc", 564 579 .data = &s3c2410_rtc_data,
+9 -24
drivers/rtc/rtc-s5m.c
··· 760 760 return -ENODEV; 761 761 } 762 762 763 - info->i2c = i2c_new_dummy_device(s5m87xx->i2c->adapter, RTC_I2C_ADDR); 763 + info->i2c = devm_i2c_new_dummy_device(&pdev->dev, s5m87xx->i2c->adapter, 764 + RTC_I2C_ADDR); 764 765 if (IS_ERR(info->i2c)) { 765 766 dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n"); 766 767 return PTR_ERR(info->i2c); ··· 772 771 ret = PTR_ERR(info->regmap); 773 772 dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n", 774 773 ret); 775 - goto err; 774 + return ret; 776 775 } 777 776 778 777 info->dev = &pdev->dev; ··· 782 781 if (s5m87xx->irq_data) { 783 782 info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); 784 783 if (info->irq <= 0) { 785 - ret = -EINVAL; 786 784 dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", 787 785 alarm_irq); 788 - goto err; 786 + return -EINVAL; 789 787 } 790 788 } 791 789 792 790 platform_set_drvdata(pdev, info); 793 791 794 792 ret = s5m8767_rtc_init_reg(info); 793 + if (ret) 794 + return ret; 795 795 796 796 device_init_wakeup(&pdev->dev, 1); 797 797 798 798 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc", 799 799 &s5m_rtc_ops, THIS_MODULE); 800 800 801 - if (IS_ERR(info->rtc_dev)) { 802 - ret = PTR_ERR(info->rtc_dev); 803 - goto err; 804 - } 801 + if (IS_ERR(info->rtc_dev)) 802 + return PTR_ERR(info->rtc_dev); 805 803 806 804 if (!info->irq) { 807 805 dev_info(&pdev->dev, "Alarm IRQ not available\n"); ··· 813 813 if (ret < 0) { 814 814 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", 815 815 info->irq, ret); 816 - goto err; 816 + return ret; 817 817 } 818 - 819 - return 0; 820 - 821 - err: 822 - i2c_unregister_device(info->i2c); 823 - 824 - return ret; 825 - } 826 - 827 - static int s5m_rtc_remove(struct platform_device *pdev) 828 - { 829 - struct s5m_rtc_info *info = platform_get_drvdata(pdev); 830 - 831 - i2c_unregister_device(info->i2c); 832 818 833 819 return 0; 834 820 } ··· 860 874 .pm = &s5m_rtc_pm_ops, 861 875 }, 862 876 .probe = s5m_rtc_probe, 863 - .remove = s5m_rtc_remove, 864 877 .id_table = s5m_rtc_id, 865 878 }; 866 879
+1 -1
drivers/rtc/rtc-sd3078.c
··· 207 207 }; 208 208 MODULE_DEVICE_TABLE(i2c, sd3078_id); 209 209 210 - static const struct of_device_id rtc_dt_match[] = { 210 + static const __maybe_unused struct of_device_id rtc_dt_match[] = { 211 211 { .compatible = "whwave,sd3078" }, 212 212 {}, 213 213 };
-446
drivers/rtc/rtc-sirfsoc.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * SiRFSoC Real Time Clock interface for Linux 4 - * 5 - * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company. 6 - */ 7 - 8 - #include <linux/module.h> 9 - #include <linux/err.h> 10 - #include <linux/rtc.h> 11 - #include <linux/platform_device.h> 12 - #include <linux/slab.h> 13 - #include <linux/io.h> 14 - #include <linux/of.h> 15 - #include <linux/regmap.h> 16 - #include <linux/rtc/sirfsoc_rtciobrg.h> 17 - 18 - 19 - #define RTC_CN 0x00 20 - #define RTC_ALARM0 0x04 21 - #define RTC_ALARM1 0x18 22 - #define RTC_STATUS 0x08 23 - #define RTC_SW_VALUE 0x40 24 - #define SIRFSOC_RTC_AL1E (1<<6) 25 - #define SIRFSOC_RTC_AL1 (1<<4) 26 - #define SIRFSOC_RTC_HZE (1<<3) 27 - #define SIRFSOC_RTC_AL0E (1<<2) 28 - #define SIRFSOC_RTC_HZ (1<<1) 29 - #define SIRFSOC_RTC_AL0 (1<<0) 30 - #define RTC_DIV 0x0c 31 - #define RTC_DEEP_CTRL 0x14 32 - #define RTC_CLOCK_SWITCH 0x1c 33 - #define SIRFSOC_RTC_CLK 0x03 /* others are reserved */ 34 - 35 - /* Refer to RTC DIV switch */ 36 - #define RTC_HZ 16 37 - 38 - /* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */ 39 - #define RTC_SHIFT 4 40 - 41 - #define INTR_SYSRTC_CN 0x48 42 - 43 - struct sirfsoc_rtc_drv { 44 - struct rtc_device *rtc; 45 - u32 rtc_base; 46 - u32 irq; 47 - unsigned irq_wake; 48 - /* Overflow for every 8 years extra time */ 49 - u32 overflow_rtc; 50 - spinlock_t lock; 51 - struct regmap *regmap; 52 - #ifdef CONFIG_PM 53 - u32 saved_counter; 54 - u32 saved_overflow_rtc; 55 - #endif 56 - }; 57 - 58 - static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset) 59 - { 60 - u32 val; 61 - 62 - regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val); 63 - return val; 64 - } 65 - 66 - static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv, 67 - u32 offset, u32 val) 68 - { 69 - regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val); 70 - } 71 - 72 - static int sirfsoc_rtc_read_alarm(struct device *dev, 73 - struct rtc_wkalrm *alrm) 74 - { 75 - unsigned long rtc_alarm, rtc_count; 76 - struct sirfsoc_rtc_drv *rtcdrv; 77 - 78 - rtcdrv = dev_get_drvdata(dev); 79 - 80 - spin_lock_irq(&rtcdrv->lock); 81 - 82 - rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 83 - 84 - rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0); 85 - memset(alrm, 0, sizeof(struct rtc_wkalrm)); 86 - 87 - /* 88 - * assume alarm interval not beyond one round counter overflow_rtc: 89 - * 0->0xffffffff 90 - */ 91 - /* if alarm is in next overflow cycle */ 92 - if (rtc_count > rtc_alarm) 93 - rtc_time64_to_tm((rtcdrv->overflow_rtc + 1) 94 - << (BITS_PER_LONG - RTC_SHIFT) 95 - | rtc_alarm >> RTC_SHIFT, &alrm->time); 96 - else 97 - rtc_time64_to_tm(rtcdrv->overflow_rtc 98 - << (BITS_PER_LONG - RTC_SHIFT) 99 - | rtc_alarm >> RTC_SHIFT, &alrm->time); 100 - if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E) 101 - alrm->enabled = 1; 102 - 103 - spin_unlock_irq(&rtcdrv->lock); 104 - 105 - return 0; 106 - } 107 - 108 - static int sirfsoc_rtc_set_alarm(struct device *dev, 109 - struct rtc_wkalrm *alrm) 110 - { 111 - unsigned long rtc_status_reg, rtc_alarm; 112 - struct sirfsoc_rtc_drv *rtcdrv; 113 - rtcdrv = dev_get_drvdata(dev); 114 - 115 - if (alrm->enabled) { 116 - rtc_alarm = rtc_tm_to_time64(&alrm->time); 117 - 118 - spin_lock_irq(&rtcdrv->lock); 119 - 120 - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 121 - if (rtc_status_reg & SIRFSOC_RTC_AL0E) { 122 - /* 123 - * An ongoing alarm in progress - ingore it and not 124 - * to return EBUSY 125 - */ 126 - dev_info(dev, "An old alarm was set, will be replaced by a new one\n"); 127 - } 128 - 129 - sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT); 130 - rtc_status_reg &= ~0x07; /* mask out the lower status bits */ 131 - /* 132 - * This bit RTC_AL sets it as a wake-up source for Sleep Mode 133 - * Writing 1 into this bit will clear it 134 - */ 135 - rtc_status_reg |= SIRFSOC_RTC_AL0; 136 - /* enable the RTC alarm interrupt */ 137 - rtc_status_reg |= SIRFSOC_RTC_AL0E; 138 - sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 139 - 140 - spin_unlock_irq(&rtcdrv->lock); 141 - } else { 142 - /* 143 - * if this function was called with enabled=0 144 - * then it could mean that the application is 145 - * trying to cancel an ongoing alarm 146 - */ 147 - spin_lock_irq(&rtcdrv->lock); 148 - 149 - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 150 - if (rtc_status_reg & SIRFSOC_RTC_AL0E) { 151 - /* clear the RTC status register's alarm bit */ 152 - rtc_status_reg &= ~0x07; 153 - /* write 1 into SIRFSOC_RTC_AL0 to force a clear */ 154 - rtc_status_reg |= (SIRFSOC_RTC_AL0); 155 - /* Clear the Alarm enable bit */ 156 - rtc_status_reg &= ~(SIRFSOC_RTC_AL0E); 157 - 158 - sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, 159 - rtc_status_reg); 160 - } 161 - 162 - spin_unlock_irq(&rtcdrv->lock); 163 - } 164 - 165 - return 0; 166 - } 167 - 168 - static int sirfsoc_rtc_read_time(struct device *dev, 169 - struct rtc_time *tm) 170 - { 171 - unsigned long tmp_rtc = 0; 172 - struct sirfsoc_rtc_drv *rtcdrv; 173 - rtcdrv = dev_get_drvdata(dev); 174 - /* 175 - * This patch is taken from WinCE - Need to validate this for 176 - * correctness. To work around sirfsoc RTC counter double sync logic 177 - * fail, read several times to make sure get stable value. 178 - */ 179 - do { 180 - tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 181 - cpu_relax(); 182 - } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN)); 183 - 184 - rtc_time64_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) 185 - | tmp_rtc >> RTC_SHIFT, tm); 186 - return 0; 187 - } 188 - 189 - static int sirfsoc_rtc_set_time(struct device *dev, 190 - struct rtc_time *tm) 191 - { 192 - unsigned long rtc_time; 193 - struct sirfsoc_rtc_drv *rtcdrv; 194 - rtcdrv = dev_get_drvdata(dev); 195 - 196 - rtc_time = rtc_tm_to_time64(tm); 197 - 198 - rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT); 199 - 200 - sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc); 201 - sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT); 202 - 203 - return 0; 204 - } 205 - 206 - static int sirfsoc_rtc_alarm_irq_enable(struct device *dev, 207 - unsigned int enabled) 208 - { 209 - unsigned long rtc_status_reg = 0x0; 210 - struct sirfsoc_rtc_drv *rtcdrv; 211 - 212 - rtcdrv = dev_get_drvdata(dev); 213 - 214 - spin_lock_irq(&rtcdrv->lock); 215 - 216 - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 217 - if (enabled) 218 - rtc_status_reg |= SIRFSOC_RTC_AL0E; 219 - else 220 - rtc_status_reg &= ~SIRFSOC_RTC_AL0E; 221 - 222 - sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 223 - 224 - spin_unlock_irq(&rtcdrv->lock); 225 - 226 - return 0; 227 - 228 - } 229 - 230 - static const struct rtc_class_ops sirfsoc_rtc_ops = { 231 - .read_time = sirfsoc_rtc_read_time, 232 - .set_time = sirfsoc_rtc_set_time, 233 - .read_alarm = sirfsoc_rtc_read_alarm, 234 - .set_alarm = sirfsoc_rtc_set_alarm, 235 - .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable 236 - }; 237 - 238 - static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata) 239 - { 240 - struct sirfsoc_rtc_drv *rtcdrv = pdata; 241 - unsigned long rtc_status_reg = 0x0; 242 - unsigned long events = 0x0; 243 - 244 - spin_lock(&rtcdrv->lock); 245 - 246 - rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 247 - /* this bit will be set ONLY if an alarm was active 248 - * and it expired NOW 249 - * So this is being used as an ASSERT 250 - */ 251 - if (rtc_status_reg & SIRFSOC_RTC_AL0) { 252 - /* 253 - * clear the RTC status register's alarm bit 254 - * mask out the lower status bits 255 - */ 256 - rtc_status_reg &= ~0x07; 257 - /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */ 258 - rtc_status_reg |= (SIRFSOC_RTC_AL0); 259 - /* Clear the Alarm enable bit */ 260 - rtc_status_reg &= ~(SIRFSOC_RTC_AL0E); 261 - } 262 - 263 - sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 264 - 265 - spin_unlock(&rtcdrv->lock); 266 - 267 - /* this should wake up any apps polling/waiting on the read 268 - * after setting the alarm 269 - */ 270 - events |= RTC_IRQF | RTC_AF; 271 - rtc_update_irq(rtcdrv->rtc, 1, events); 272 - 273 - return IRQ_HANDLED; 274 - } 275 - 276 - static const struct of_device_id sirfsoc_rtc_of_match[] = { 277 - { .compatible = "sirf,prima2-sysrtc"}, 278 - {}, 279 - }; 280 - 281 - static const struct regmap_config sysrtc_regmap_config = { 282 - .reg_bits = 32, 283 - .val_bits = 32, 284 - .fast_io = true, 285 - }; 286 - 287 - MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match); 288 - 289 - static int sirfsoc_rtc_probe(struct platform_device *pdev) 290 - { 291 - int err; 292 - unsigned long rtc_div; 293 - struct sirfsoc_rtc_drv *rtcdrv; 294 - struct device_node *np = pdev->dev.of_node; 295 - 296 - rtcdrv = devm_kzalloc(&pdev->dev, 297 - sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL); 298 - if (rtcdrv == NULL) 299 - return -ENOMEM; 300 - 301 - spin_lock_init(&rtcdrv->lock); 302 - 303 - err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base); 304 - if (err) { 305 - dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n"); 306 - return err; 307 - } 308 - 309 - platform_set_drvdata(pdev, rtcdrv); 310 - 311 - /* Register rtc alarm as a wakeup source */ 312 - device_init_wakeup(&pdev->dev, 1); 313 - 314 - rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev, 315 - &sysrtc_regmap_config); 316 - if (IS_ERR(rtcdrv->regmap)) { 317 - err = PTR_ERR(rtcdrv->regmap); 318 - dev_err(&pdev->dev, "Failed to allocate register map: %d\n", 319 - err); 320 - return err; 321 - } 322 - 323 - /* 324 - * Set SYS_RTC counter in RTC_HZ HZ Units 325 - * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1 326 - * If 16HZ, therefore RTC_DIV = 1023; 327 - */ 328 - rtc_div = ((32768 / RTC_HZ) / 2) - 1; 329 - sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div); 330 - 331 - /* 0x3 -> RTC_CLK */ 332 - sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK); 333 - 334 - /* reset SYS RTC ALARM0 */ 335 - sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0); 336 - 337 - /* reset SYS RTC ALARM1 */ 338 - sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0); 339 - 340 - /* Restore RTC Overflow From Register After Command Reboot */ 341 - rtcdrv->overflow_rtc = 342 - sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE); 343 - 344 - rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev); 345 - if (IS_ERR(rtcdrv->rtc)) 346 - return PTR_ERR(rtcdrv->rtc); 347 - 348 - rtcdrv->rtc->ops = &sirfsoc_rtc_ops; 349 - rtcdrv->rtc->range_max = (1ULL << 60) - 1; 350 - 351 - rtcdrv->irq = platform_get_irq(pdev, 0); 352 - err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler, 353 - IRQF_SHARED, pdev->name, rtcdrv); 354 - if (err) { 355 - dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n"); 356 - return err; 357 - } 358 - 359 - return devm_rtc_register_device(rtcdrv->rtc); 360 - } 361 - 362 - #ifdef CONFIG_PM_SLEEP 363 - static int sirfsoc_rtc_suspend(struct device *dev) 364 - { 365 - struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); 366 - rtcdrv->overflow_rtc = 367 - sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE); 368 - 369 - rtcdrv->saved_counter = 370 - sirfsoc_rtc_readl(rtcdrv, RTC_CN); 371 - rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc; 372 - if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq)) 373 - rtcdrv->irq_wake = 1; 374 - 375 - return 0; 376 - } 377 - 378 - static int sirfsoc_rtc_resume(struct device *dev) 379 - { 380 - u32 tmp; 381 - struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); 382 - 383 - /* 384 - * if resume from snapshot and the rtc power is lost, 385 - * restroe the rtc settings 386 - */ 387 - if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) { 388 - u32 rtc_div; 389 - /* 0x3 -> RTC_CLK */ 390 - sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK); 391 - /* 392 - * Set SYS_RTC counter in RTC_HZ HZ Units 393 - * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1 394 - * If 16HZ, therefore RTC_DIV = 1023; 395 - */ 396 - rtc_div = ((32768 / RTC_HZ) / 2) - 1; 397 - 398 - sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div); 399 - 400 - /* reset SYS RTC ALARM0 */ 401 - sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0); 402 - 403 - /* reset SYS RTC ALARM1 */ 404 - sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0); 405 - } 406 - rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc; 407 - 408 - /* 409 - * if current counter is small than previous, 410 - * it means overflow in sleep 411 - */ 412 - tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 413 - if (tmp <= rtcdrv->saved_counter) 414 - rtcdrv->overflow_rtc++; 415 - /* 416 - *PWRC Value Be Changed When Suspend, Restore Overflow 417 - * In Memory To Register 418 - */ 419 - sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc); 420 - 421 - if (device_may_wakeup(dev) && rtcdrv->irq_wake) { 422 - disable_irq_wake(rtcdrv->irq); 423 - rtcdrv->irq_wake = 0; 424 - } 425 - 426 - return 0; 427 - } 428 - #endif 429 - 430 - static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops, 431 - sirfsoc_rtc_suspend, sirfsoc_rtc_resume); 432 - 433 - static struct platform_driver sirfsoc_rtc_driver = { 434 - .driver = { 435 - .name = "sirfsoc-rtc", 436 - .pm = &sirfsoc_rtc_pm_ops, 437 - .of_match_table = sirfsoc_rtc_of_match, 438 - }, 439 - .probe = sirfsoc_rtc_probe, 440 - }; 441 - module_platform_driver(sirfsoc_rtc_driver); 442 - 443 - MODULE_DESCRIPTION("SiRF SoC rtc driver"); 444 - MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>"); 445 - MODULE_LICENSE("GPL v2"); 446 - MODULE_ALIAS("platform:sirfsoc-rtc");
+2 -2
drivers/rtc/rtc-stm32.c
··· 209 209 const struct stm32_rtc_events *evts = &rtc->data->events; 210 210 unsigned int status, cr; 211 211 212 - mutex_lock(&rtc->rtc_dev->ops_lock); 212 + rtc_lock(rtc->rtc_dev); 213 213 214 214 status = readl_relaxed(rtc->base + regs->sr); 215 215 cr = readl_relaxed(rtc->base + regs->cr); ··· 226 226 stm32_rtc_clear_event_flags(rtc, evts->alra); 227 227 } 228 228 229 - mutex_unlock(&rtc->rtc_dev->ops_lock); 229 + rtc_unlock(rtc->rtc_dev); 230 230 231 231 return IRQ_HANDLED; 232 232 }
+3 -3
drivers/rtc/rtc-tegra.c
··· 232 232 { 233 233 struct device *dev = data; 234 234 struct tegra_rtc_info *info = dev_get_drvdata(dev); 235 - unsigned long events = 0, flags; 235 + unsigned long events = 0; 236 236 u32 status; 237 237 238 238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); ··· 240 240 /* clear the interrupt masks and status on any IRQ */ 241 241 tegra_rtc_wait_while_busy(dev); 242 242 243 - spin_lock_irqsave(&info->lock, flags); 243 + spin_lock(&info->lock); 244 244 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); 245 245 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS); 246 - spin_unlock_irqrestore(&info->lock, flags); 246 + spin_unlock(&info->lock); 247 247 } 248 248 249 249 /* check if alarm */
+8 -11
drivers/rtc/rtc-tps65910.c
··· 361 361 .set_offset = tps65910_set_offset, 362 362 }; 363 363 364 - static const struct rtc_class_ops tps65910_rtc_ops_noirq = { 365 - .read_time = tps65910_rtc_read_time, 366 - .set_time = tps65910_rtc_set_time, 367 - .read_offset = tps65910_read_offset, 368 - .set_offset = tps65910_set_offset, 369 - }; 370 - 371 364 static int tps65910_rtc_probe(struct platform_device *pdev) 372 365 { 373 366 struct tps65910 *tps65910 = NULL; ··· 419 426 420 427 tps_rtc->irq = irq; 421 428 if (irq != -1) { 422 - device_set_wakeup_capable(&pdev->dev, 1); 423 - tps_rtc->rtc->ops = &tps65910_rtc_ops; 424 - } else 425 - tps_rtc->rtc->ops = &tps65910_rtc_ops_noirq; 429 + if (device_property_present(tps65910->dev, "wakeup-source")) 430 + device_init_wakeup(&pdev->dev, 1); 431 + else 432 + device_set_wakeup_capable(&pdev->dev, 1); 433 + } else { 434 + clear_bit(RTC_FEATURE_ALARM, tps_rtc->rtc->features); 435 + } 426 436 437 + tps_rtc->rtc->ops = &tps65910_rtc_ops; 427 438 tps_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 428 439 tps_rtc->rtc->range_max = RTC_TIMESTAMP_END_2099; 429 440
-303
drivers/rtc/rtc-tx4939.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * TX4939 internal RTC driver 4 - * Based on RBTX49xx patch from CELF patch archive. 5 - * 6 - * (C) Copyright TOSHIBA CORPORATION 2005-2007 7 - */ 8 - #include <linux/rtc.h> 9 - #include <linux/platform_device.h> 10 - #include <linux/interrupt.h> 11 - #include <linux/module.h> 12 - #include <linux/io.h> 13 - #include <linux/gfp.h> 14 - 15 - #define TX4939_RTCCTL_ALME 0x00000080 16 - #define TX4939_RTCCTL_ALMD 0x00000040 17 - #define TX4939_RTCCTL_BUSY 0x00000020 18 - 19 - #define TX4939_RTCCTL_COMMAND 0x00000007 20 - #define TX4939_RTCCTL_COMMAND_NOP 0x00000000 21 - #define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001 22 - #define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002 23 - #define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003 24 - #define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004 25 - 26 - #define TX4939_RTCTBC_PM 0x00000080 27 - #define TX4939_RTCTBC_COMP 0x0000007f 28 - 29 - #define TX4939_RTC_REG_RAMSIZE 0x00000100 30 - #define TX4939_RTC_REG_RWBSIZE 0x00000006 31 - 32 - struct tx4939_rtc_reg { 33 - __u32 ctl; 34 - __u32 adr; 35 - __u32 dat; 36 - __u32 tbc; 37 - }; 38 - 39 - struct tx4939rtc_plat_data { 40 - struct rtc_device *rtc; 41 - struct tx4939_rtc_reg __iomem *rtcreg; 42 - spinlock_t lock; 43 - }; 44 - 45 - static int tx4939_rtc_cmd(struct tx4939_rtc_reg __iomem *rtcreg, int cmd) 46 - { 47 - int i = 0; 48 - 49 - __raw_writel(cmd, &rtcreg->ctl); 50 - /* This might take 30us (next 32.768KHz clock) */ 51 - while (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_BUSY) { 52 - /* timeout on approx. 100us (@ GBUS200MHz) */ 53 - if (i++ > 200 * 100) 54 - return -EBUSY; 55 - cpu_relax(); 56 - } 57 - return 0; 58 - } 59 - 60 - static int tx4939_rtc_set_time(struct device *dev, struct rtc_time *tm) 61 - { 62 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); 63 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 64 - unsigned long secs = rtc_tm_to_time64(tm); 65 - int i, ret; 66 - unsigned char buf[6]; 67 - 68 - buf[0] = 0; 69 - buf[1] = 0; 70 - buf[2] = secs; 71 - buf[3] = secs >> 8; 72 - buf[4] = secs >> 16; 73 - buf[5] = secs >> 24; 74 - spin_lock_irq(&pdata->lock); 75 - __raw_writel(0, &rtcreg->adr); 76 - for (i = 0; i < 6; i++) 77 - __raw_writel(buf[i], &rtcreg->dat); 78 - ret = tx4939_rtc_cmd(rtcreg, 79 - TX4939_RTCCTL_COMMAND_SETTIME | 80 - (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 81 - spin_unlock_irq(&pdata->lock); 82 - return ret; 83 - } 84 - 85 - static int tx4939_rtc_read_time(struct device *dev, struct rtc_time *tm) 86 - { 87 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); 88 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 89 - int i, ret; 90 - unsigned long sec; 91 - unsigned char buf[6]; 92 - 93 - spin_lock_irq(&pdata->lock); 94 - ret = tx4939_rtc_cmd(rtcreg, 95 - TX4939_RTCCTL_COMMAND_GETTIME | 96 - (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 97 - if (ret) { 98 - spin_unlock_irq(&pdata->lock); 99 - return ret; 100 - } 101 - __raw_writel(2, &rtcreg->adr); 102 - for (i = 2; i < 6; i++) 103 - buf[i] = __raw_readl(&rtcreg->dat); 104 - spin_unlock_irq(&pdata->lock); 105 - sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) | 106 - (buf[3] << 8) | buf[2]; 107 - rtc_time64_to_tm(sec, tm); 108 - return 0; 109 - } 110 - 111 - static int tx4939_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 112 - { 113 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); 114 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 115 - int i, ret; 116 - unsigned long sec; 117 - unsigned char buf[6]; 118 - 119 - sec = rtc_tm_to_time64(&alrm->time); 120 - buf[0] = 0; 121 - buf[1] = 0; 122 - buf[2] = sec; 123 - buf[3] = sec >> 8; 124 - buf[4] = sec >> 16; 125 - buf[5] = sec >> 24; 126 - spin_lock_irq(&pdata->lock); 127 - __raw_writel(0, &rtcreg->adr); 128 - for (i = 0; i < 6; i++) 129 - __raw_writel(buf[i], &rtcreg->dat); 130 - ret = tx4939_rtc_cmd(rtcreg, TX4939_RTCCTL_COMMAND_SETALARM | 131 - (alrm->enabled ? TX4939_RTCCTL_ALME : 0)); 132 - spin_unlock_irq(&pdata->lock); 133 - return ret; 134 - } 135 - 136 - static int tx4939_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 137 - { 138 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); 139 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 140 - int i, ret; 141 - unsigned long sec; 142 - unsigned char buf[6]; 143 - u32 ctl; 144 - 145 - spin_lock_irq(&pdata->lock); 146 - ret = tx4939_rtc_cmd(rtcreg, 147 - TX4939_RTCCTL_COMMAND_GETALARM | 148 - (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 149 - if (ret) { 150 - spin_unlock_irq(&pdata->lock); 151 - return ret; 152 - } 153 - __raw_writel(2, &rtcreg->adr); 154 - for (i = 2; i < 6; i++) 155 - buf[i] = __raw_readl(&rtcreg->dat); 156 - ctl = __raw_readl(&rtcreg->ctl); 157 - alrm->enabled = (ctl & TX4939_RTCCTL_ALME) ? 1 : 0; 158 - alrm->pending = (ctl & TX4939_RTCCTL_ALMD) ? 1 : 0; 159 - spin_unlock_irq(&pdata->lock); 160 - sec = ((unsigned long)buf[5] << 24) | (buf[4] << 16) | 161 - (buf[3] << 8) | buf[2]; 162 - rtc_time64_to_tm(sec, &alrm->time); 163 - return rtc_valid_tm(&alrm->time); 164 - } 165 - 166 - static int tx4939_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 167 - { 168 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev); 169 - 170 - spin_lock_irq(&pdata->lock); 171 - tx4939_rtc_cmd(pdata->rtcreg, 172 - TX4939_RTCCTL_COMMAND_NOP | 173 - (enabled ? TX4939_RTCCTL_ALME : 0)); 174 - spin_unlock_irq(&pdata->lock); 175 - return 0; 176 - } 177 - 178 - static irqreturn_t tx4939_rtc_interrupt(int irq, void *dev_id) 179 - { 180 - struct tx4939rtc_plat_data *pdata = dev_get_drvdata(dev_id); 181 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 182 - unsigned long events = RTC_IRQF; 183 - 184 - spin_lock(&pdata->lock); 185 - if (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALMD) { 186 - events |= RTC_AF; 187 - tx4939_rtc_cmd(rtcreg, TX4939_RTCCTL_COMMAND_NOP); 188 - } 189 - spin_unlock(&pdata->lock); 190 - rtc_update_irq(pdata->rtc, 1, events); 191 - 192 - return IRQ_HANDLED; 193 - } 194 - 195 - static const struct rtc_class_ops tx4939_rtc_ops = { 196 - .read_time = tx4939_rtc_read_time, 197 - .read_alarm = tx4939_rtc_read_alarm, 198 - .set_alarm = tx4939_rtc_set_alarm, 199 - .set_time = tx4939_rtc_set_time, 200 - .alarm_irq_enable = tx4939_rtc_alarm_irq_enable, 201 - }; 202 - 203 - static int tx4939_nvram_read(void *priv, unsigned int pos, void *val, 204 - size_t bytes) 205 - { 206 - struct tx4939rtc_plat_data *pdata = priv; 207 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 208 - u8 *buf = val; 209 - 210 - spin_lock_irq(&pdata->lock); 211 - for (; bytes; bytes--) { 212 - __raw_writel(pos++, &rtcreg->adr); 213 - *buf++ = __raw_readl(&rtcreg->dat); 214 - } 215 - spin_unlock_irq(&pdata->lock); 216 - return 0; 217 - } 218 - 219 - static int tx4939_nvram_write(void *priv, unsigned int pos, void *val, 220 - size_t bytes) 221 - { 222 - struct tx4939rtc_plat_data *pdata = priv; 223 - struct tx4939_rtc_reg __iomem *rtcreg = pdata->rtcreg; 224 - u8 *buf = val; 225 - 226 - spin_lock_irq(&pdata->lock); 227 - for (; bytes; bytes--) { 228 - __raw_writel(pos++, &rtcreg->adr); 229 - __raw_writel(*buf++, &rtcreg->dat); 230 - } 231 - spin_unlock_irq(&pdata->lock); 232 - return 0; 233 - } 234 - 235 - static int __init tx4939_rtc_probe(struct platform_device *pdev) 236 - { 237 - struct rtc_device *rtc; 238 - struct tx4939rtc_plat_data *pdata; 239 - int irq, ret; 240 - struct nvmem_config nvmem_cfg = { 241 - .name = "tx4939_nvram", 242 - .size = TX4939_RTC_REG_RAMSIZE, 243 - .reg_read = tx4939_nvram_read, 244 - .reg_write = tx4939_nvram_write, 245 - }; 246 - 247 - irq = platform_get_irq(pdev, 0); 248 - if (irq < 0) 249 - return -ENODEV; 250 - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 251 - if (!pdata) 252 - return -ENOMEM; 253 - platform_set_drvdata(pdev, pdata); 254 - 255 - pdata->rtcreg = devm_platform_ioremap_resource(pdev, 0); 256 - if (IS_ERR(pdata->rtcreg)) 257 - return PTR_ERR(pdata->rtcreg); 258 - 259 - spin_lock_init(&pdata->lock); 260 - tx4939_rtc_cmd(pdata->rtcreg, TX4939_RTCCTL_COMMAND_NOP); 261 - if (devm_request_irq(&pdev->dev, irq, tx4939_rtc_interrupt, 262 - 0, pdev->name, &pdev->dev) < 0) 263 - return -EBUSY; 264 - rtc = devm_rtc_allocate_device(&pdev->dev); 265 - if (IS_ERR(rtc)) 266 - return PTR_ERR(rtc); 267 - 268 - rtc->ops = &tx4939_rtc_ops; 269 - rtc->range_max = U32_MAX; 270 - 271 - pdata->rtc = rtc; 272 - 273 - nvmem_cfg.priv = pdata; 274 - ret = devm_rtc_nvmem_register(rtc, &nvmem_cfg); 275 - if (ret) 276 - return ret; 277 - 278 - return devm_rtc_register_device(rtc); 279 - } 280 - 281 - static int __exit tx4939_rtc_remove(struct platform_device *pdev) 282 - { 283 - struct tx4939rtc_plat_data *pdata = platform_get_drvdata(pdev); 284 - 285 - spin_lock_irq(&pdata->lock); 286 - tx4939_rtc_cmd(pdata->rtcreg, TX4939_RTCCTL_COMMAND_NOP); 287 - spin_unlock_irq(&pdata->lock); 288 - return 0; 289 - } 290 - 291 - static struct platform_driver tx4939_rtc_driver = { 292 - .remove = __exit_p(tx4939_rtc_remove), 293 - .driver = { 294 - .name = "tx4939rtc", 295 - }, 296 - }; 297 - 298 - module_platform_driver_probe(tx4939_rtc_driver, tx4939_rtc_probe); 299 - 300 - MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>"); 301 - MODULE_DESCRIPTION("TX4939 internal RTC driver"); 302 - MODULE_LICENSE("GPL v2"); 303 - MODULE_ALIAS("platform:tx4939rtc");
+2
include/linux/rtc.h
··· 141 141 */ 142 142 unsigned long set_offset_nsec; 143 143 144 + unsigned long features[BITS_TO_LONGS(RTC_FEATURE_CNT)]; 145 + 144 146 time64_t range_min; 145 147 timeu64_t range_max; 146 148 time64_t start_secs;
-21
include/linux/rtc/sirfsoc_rtciobrg.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * RTC I/O Bridge interfaces for CSR SiRFprimaII 4 - * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module 5 - * 6 - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 7 - */ 8 - #ifndef _SIRFSOC_RTC_IOBRG_H_ 9 - #define _SIRFSOC_RTC_IOBRG_H_ 10 - 11 - struct regmap_config; 12 - 13 - extern void sirfsoc_rtc_iobrg_besyncing(void); 14 - 15 - extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); 16 - 17 - extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); 18 - struct regmap *devm_regmap_init_iobg(struct device *dev, 19 - const struct regmap_config *config); 20 - 21 - #endif
+5
include/uapi/linux/rtc.h
··· 110 110 #define RTC_AF 0x20 /* Alarm interrupt */ 111 111 #define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ 112 112 113 + /* feature list */ 114 + #define RTC_FEATURE_ALARM 0 115 + #define RTC_FEATURE_ALARM_RES_MINUTE 1 116 + #define RTC_FEATURE_NEED_WEEK_DAY 2 117 + #define RTC_FEATURE_CNT 3 113 118 114 119 #define RTC_MAX_FREQ 8192 115 120