Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2022-09-08 (e1000e, igc)

This series contains updates to e1000e and igc drivers.

Li Zhong adds checking and handling for failed PHY register reads for
e1000e.

Sasha removes an unused define for igc.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

+17 -4
+17 -3
drivers/net/ethernet/intel/e1000e/phy.c
··· 2697 2697 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2698 2698 { 2699 2699 u16 mii_reg = 0; 2700 + int ret; 2700 2701 2701 2702 /* The PHY will retain its settings across a power down/up cycle */ 2702 - e1e_rphy(hw, MII_BMCR, &mii_reg); 2703 + ret = e1e_rphy(hw, MII_BMCR, &mii_reg); 2704 + if (ret) { 2705 + e_dbg("Error reading PHY register\n"); 2706 + return; 2707 + } 2703 2708 mii_reg &= ~BMCR_PDOWN; 2704 2709 e1e_wphy(hw, MII_BMCR, mii_reg); 2705 2710 } ··· 2720 2715 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2721 2716 { 2722 2717 u16 mii_reg = 0; 2718 + int ret; 2723 2719 2724 2720 /* The PHY will retain its settings across a power down/up cycle */ 2725 - e1e_rphy(hw, MII_BMCR, &mii_reg); 2721 + ret = e1e_rphy(hw, MII_BMCR, &mii_reg); 2722 + if (ret) { 2723 + e_dbg("Error reading PHY register\n"); 2724 + return; 2725 + } 2726 2726 mii_reg |= BMCR_PDOWN; 2727 2727 e1e_wphy(hw, MII_BMCR, mii_reg); 2728 2728 usleep_range(1000, 2000); ··· 3047 3037 return 0; 3048 3038 3049 3039 /* Do not apply workaround if in PHY loopback bit 14 set */ 3050 - e1e_rphy(hw, MII_BMCR, &data); 3040 + ret_val = e1e_rphy(hw, MII_BMCR, &data); 3041 + if (ret_val) { 3042 + e_dbg("Error reading PHY register\n"); 3043 + return ret_val; 3044 + } 3051 3045 if (data & BMCR_LOOPBACK) 3052 3046 return 0; 3053 3047
-1
drivers/net/ethernet/intel/igc/igc_defines.h
··· 610 610 #define IGC_MDIC_OP_WRITE 0x04000000 611 611 #define IGC_MDIC_OP_READ 0x08000000 612 612 #define IGC_MDIC_READY 0x10000000 613 - #define IGC_MDIC_INT_EN 0x20000000 614 613 #define IGC_MDIC_ERROR 0x40000000 615 614 616 615 #define IGC_N0_QUEUE -1