tjh.dev / kernel
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octeontx2-pf: Fix coverity and klockwork issues in octeon PF driver

Fix unintended sign extension and klockwork issues. These are not real
issue but for sanity checks.

Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
Signed-off-by: Suman Ghosh <sumang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Ratheesh Kannoth and committed by
David S. Miller 02ea3120 f4b91c1d

+35 -35
+5 -5
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
··· 648 648 } else if (lvl == NIX_TXSCH_LVL_TL4) { 649 649 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 650 650 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 651 - req->regval[0] = parent << 16; 651 + req->regval[0] = (u64)parent << 16; 652 652 req->num_regs++; 653 653 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 654 654 req->regval[1] = dwrr_val; 655 655 } else if (lvl == NIX_TXSCH_LVL_TL3) { 656 656 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 657 657 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 658 - req->regval[0] = parent << 16; 658 + req->regval[0] = (u64)parent << 16; 659 659 req->num_regs++; 660 660 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 661 661 req->regval[1] = dwrr_val; ··· 670 670 } else if (lvl == NIX_TXSCH_LVL_TL2) { 671 671 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 672 672 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 673 - req->regval[0] = parent << 16; 673 + req->regval[0] = (u64)parent << 16; 674 674 675 675 req->num_regs++; 676 676 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 677 - req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 677 + req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val; 678 678 679 679 if (lvl == hw->txschq_link_cfg_lvl) { 680 680 req->num_regs++; ··· 698 698 699 699 req->num_regs++; 700 700 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 701 - req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 701 + req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1; 702 702 703 703 req->num_regs++; 704 704 req->reg[2] = NIX_AF_TL1X_CIR(schq);
+28 -27
drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h
··· 139 139 #define NIX_LF_CINTX_ENA_W1C(a) (NIX_LFBASE | 0xD50 | (a) << 12) 140 140 141 141 /* NIX AF transmit scheduler registers */ 142 - #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) 143 - #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) 144 - #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) 145 - #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) 146 - #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) 147 - #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) 148 - #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16) 149 - #define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16) 150 - #define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16) 151 - #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) 152 - #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) 153 - #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16) 154 - #define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16) 155 - #define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16) 156 - #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16) 157 - #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) 158 - #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) 159 - #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16) 160 - #define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16) 161 - #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) 162 - #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16) 163 - #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) 164 - #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16) 165 - #define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16) 166 - #define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16) 167 - #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) 168 - #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) 142 + #define NIX_AF_SMQX_CFG(a) (0x700 | (u64)(a) << 16) 143 + #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (u64)(a) << 16) 144 + #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (u64)(a) << 16) 145 + #define NIX_AF_TL1X_CIR(a) (0xC20 | (u64)(a) << 16) 146 + #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (u64)(a) << 16) 147 + #define NIX_AF_TL2X_PARENT(a) (0xE88 | (u64)(a) << 16) 148 + #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (u64)(a) << 16) 149 + #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (u64)(a) << 16) 150 + #define NIX_AF_TL2X_CIR(a) (0xE20 | (u64)(a) << 16) 151 + #define NIX_AF_TL2X_PIR(a) (0xE30 | (u64)(a) << 16) 152 + #define NIX_AF_TL3X_PARENT(a) (0x1088 | (u64)(a) << 16) 153 + #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (u64)(a) << 16) 154 + #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (u64)(a) << 16) 155 + #define NIX_AF_TL3X_CIR(a) (0x1020 | (u64)(a) << 16) 156 + #define NIX_AF_TL3X_PIR(a) (0x1030 | (u64)(a) << 16) 157 + #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (u64)(a) << 16) 158 + #define NIX_AF_TL4X_PARENT(a) (0x1288 | (u64)(a) << 16) 159 + #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (u64)(a) << 16) 160 + #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (u64)(a) << 16) 161 + #define NIX_AF_TL4X_CIR(a) (0x1220 | (u64)(a) << 16) 162 + #define NIX_AF_TL4X_PIR(a) (0x1230 | (u64)(a) << 16) 163 + #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (u64)(a) << 16) 164 + #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (u64)(a) << 16) 165 + #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (u64)(a) << 16) 166 + #define NIX_AF_MDQX_CIR(a) (0x1420 | (u64)(a) << 16) 167 + #define NIX_AF_MDQX_PIR(a) (0x1430 | (u64)(a) << 16) 168 + #define NIX_AF_MDQX_PARENT(a) (0x1480 | (u64)(a) << 16) 169 + #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (u64)(a) << 16 | (b) << 3) 169 170 170 171 /* LMT LF registers */ 171 172 #define LMT_LFBASE BIT_ULL(RVU_FUNC_BLKADDR_SHIFT)
+1 -1
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
··· 513 513 514 514 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll) 515 515 { 516 - struct dim_sample dim_sample; 516 + struct dim_sample dim_sample = { 0 }; 517 517 u64 rx_frames, rx_bytes; 518 518 u64 tx_frames, tx_bytes; 519 519
+1 -2
drivers/net/ethernet/marvell/octeontx2/nic/qos.c
··· 153 153 num_regs++; 154 154 155 155 otx2_config_sched_shaping(pfvf, node, cfg, &num_regs); 156 - 157 156 } else if (level == NIX_TXSCH_LVL_TL4) { 158 157 otx2_config_sched_shaping(pfvf, node, cfg, &num_regs); 159 158 } else if (level == NIX_TXSCH_LVL_TL3) { ··· 175 176 /* check if node is root */ 176 177 if (node->qid == OTX2_QOS_QID_INNER && !node->parent) { 177 178 cfg->reg[num_regs] = NIX_AF_TL2X_SCHEDULE(node->schq); 178 - cfg->regval[num_regs] = TXSCH_TL1_DFLT_RR_PRIO << 24 | 179 + cfg->regval[num_regs] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | 179 180 mtu_to_dwrr_weight(pfvf, 180 181 pfvf->tx_max_pktlen); 181 182 num_regs++;