+10
-10
drivers/gpu/drm/radeon/radeon_cursor.c
+10
-10
drivers/gpu/drm/radeon/radeon_cursor.c
···
215
}
216
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
217
218
-
if (x < 0)
219
xorigin = min(-x, CURSOR_WIDTH - 1);
220
-
if (y < 0)
221
yorigin = min(-y, CURSOR_HEIGHT - 1);
222
223
if (ASIC_IS_AVIVO(rdev)) {
224
int i = 0;
···
255
256
radeon_lock_cursor(crtc, true);
257
if (ASIC_IS_DCE4(rdev)) {
258
-
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
259
-
((xorigin ? 0 : x) << 16) |
260
-
(yorigin ? 0 : y));
261
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
262
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
263
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
264
} else if (ASIC_IS_AVIVO(rdev)) {
265
-
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
266
-
((xorigin ? 0 : x) << 16) |
267
-
(yorigin ? 0 : y));
268
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
269
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
270
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
···
274
| yorigin));
275
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
276
(RADEON_CUR_LOCK
277
-
| ((xorigin ? 0 : x) << 16)
278
-
| (yorigin ? 0 : y)));
279
/* offset is from DISP(2)_BASE_ADDRESS */
280
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
281
(yorigin * 256)));
···
215
}
216
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
217
218
+
if (x < 0) {
219
xorigin = min(-x, CURSOR_WIDTH - 1);
220
+
x = 0;
221
+
}
222
+
if (y < 0) {
223
yorigin = min(-y, CURSOR_HEIGHT - 1);
224
+
y = 0;
225
+
}
226
227
if (ASIC_IS_AVIVO(rdev)) {
228
int i = 0;
···
251
252
radeon_lock_cursor(crtc, true);
253
if (ASIC_IS_DCE4(rdev)) {
254
+
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
255
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
256
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
257
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
258
} else if (ASIC_IS_AVIVO(rdev)) {
259
+
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
260
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
261
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
262
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
···
274
| yorigin));
275
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
276
(RADEON_CUR_LOCK
277
+
| (x << 16)
278
+
| y));
279
/* offset is from DISP(2)_BASE_ADDRESS */
280
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
281
(yorigin * 256)));