tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'topic/nouveau-ampere-modeset-2021-01-15' of git://anongit.freedesktop.org/drm/drm
Pull drm nouveau ampere display support from Dave Airlie:
"Ben has requested if we can include Ampere modesetting support under
fixes, it's for new GPUs and shouldn't affect existing hardware.
It's a bit bigger than just adding a PCI ID, but It has no effect on
older GPUs"
* tag 'topic/nouveau-ampere-modeset-2021-01-15' of git://anongit.freedesktop.org/drm/drm:
drm/nouveau/disp/ga10[24]: initial support
drm/nouveau/dmaobj/ga10[24]: initial support
drm/nouveau/i2c/ga10[024]: initial support
drm/nouveau/gpio/ga10[024]: initial support
drm/nouveau/bar/ga10[024]: initial support
drm/nouveau/mmu/ga10[024]: initial support
drm/nouveau/timer/ga10[024]: initial support
drm/nouveau/fb/ga10[024]: initial support
drm/nouveau/imem/ga10[024]: initial support
drm/nouveau/privring/ga10[024]: initial support
drm/nouveau/mc/ga10[024]: initial support
drm/nouveau/devinit/ga10[024]: initial support
drm/nouveau/bios/ga10[024]: initial support
drm/nouveau/pci/ga10[024]: initial support
drm/nouveau/core: recognise GA10[024]
+892
-18
+1
drivers/gpu/drm/nouveau/dispnv50/Kbuild
+1
drivers/gpu/drm/nouveau/dispnv50/Kbuild
+1
drivers/gpu/drm/nouveau/dispnv50/core.c
+1
drivers/gpu/drm/nouveau/dispnv50/core.c
···
42
42
int version;
43
43
int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
44
44
} cores[] = {
45
+
{ GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
45
46
{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
46
47
{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
47
48
{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
+1
drivers/gpu/drm/nouveau/dispnv50/curs.c
+1
drivers/gpu/drm/nouveau/dispnv50/curs.c
+1
drivers/gpu/drm/nouveau/dispnv50/wimm.c
+1
drivers/gpu/drm/nouveau/dispnv50/wimm.c
···
31
31
int version;
32
32
int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
33
33
} wimms[] = {
34
+
{ GA102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
34
35
{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
35
36
{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
36
37
{}
+1
drivers/gpu/drm/nouveau/dispnv50/wndw.c
+1
drivers/gpu/drm/nouveau/dispnv50/wndw.c
···
784
784
int (*new)(struct nouveau_drm *, enum drm_plane_type,
785
785
int, s32, struct nv50_wndw **);
786
786
} wndws[] = {
787
+
{ GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
787
788
{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
788
789
{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
789
790
{}
+8
drivers/gpu/drm/nouveau/dispnv50/wndw.h
+8
drivers/gpu/drm/nouveau/dispnv50/wndw.h
···
129
129
130
130
int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
131
131
struct nv50_wndw **);
132
+
bool wndwc57e_ilut(struct nv50_wndw *, struct nv50_wndw_atom *, int);
133
+
int wndwc57e_ilut_set(struct nv50_wndw *, struct nv50_wndw_atom *);
134
+
int wndwc57e_ilut_clr(struct nv50_wndw *);
135
+
int wndwc57e_csc_set(struct nv50_wndw *, struct nv50_wndw_atom *);
136
+
int wndwc57e_csc_clr(struct nv50_wndw *);
137
+
138
+
int wndwc67e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
139
+
struct nv50_wndw **);
132
140
133
141
int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,
134
142
struct nv50_wndw **);
+5
-5
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
+5
-5
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
···
80
80
return 0;
81
81
}
82
82
83
-
static int
83
+
int
84
84
wndwc57e_csc_clr(struct nv50_wndw *wndw)
85
85
{
86
86
struct nvif_push *push = wndw->wndw.push;
···
98
98
return 0;
99
99
}
100
100
101
-
static int
101
+
int
102
102
wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
103
103
{
104
104
struct nvif_push *push = wndw->wndw.push;
···
111
111
return 0;
112
112
}
113
113
114
-
static int
114
+
int
115
115
wndwc57e_ilut_clr(struct nv50_wndw *wndw)
116
116
{
117
117
struct nvif_push *push = wndw->wndw.push;
···
124
124
return 0;
125
125
}
126
126
127
-
static int
127
+
int
128
128
wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
129
129
{
130
130
struct nvif_push *push = wndw->wndw.push;
···
179
179
writew(readw(mem - 4), mem + 4);
180
180
}
181
181
182
-
static bool
182
+
bool
183
183
wndwc57e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
184
184
{
185
185
if (size = size ? size : 1024, size != 256 && size != 1024)
+106
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
+106
drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "wndw.h"
23
+
#include "atom.h"
24
+
25
+
#include <nvif/pushc37b.h>
26
+
27
+
#include <nvhw/class/clc57e.h>
28
+
29
+
static int
30
+
wndwc67e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
31
+
{
32
+
struct nvif_push *push = wndw->wndw.push;
33
+
int ret;
34
+
35
+
if ((ret = PUSH_WAIT(push, 17)))
36
+
return ret;
37
+
38
+
PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
39
+
NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
40
+
NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
41
+
NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
42
+
43
+
PUSH_MTHD(push, NVC57E, SET_SIZE,
44
+
NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) |
45
+
NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h),
46
+
47
+
SET_STORAGE,
48
+
NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
49
+
50
+
SET_PARAMS,
51
+
NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) |
52
+
NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
53
+
NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) |
54
+
NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
55
+
56
+
SET_PLANAR_STORAGE(0),
57
+
NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
58
+
NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
59
+
60
+
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
61
+
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
62
+
63
+
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
64
+
NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
65
+
NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
66
+
67
+
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
68
+
NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
69
+
NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
70
+
71
+
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
72
+
NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
73
+
NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
74
+
return 0;
75
+
}
76
+
77
+
static const struct nv50_wndw_func
78
+
wndwc67e = {
79
+
.acquire = wndwc37e_acquire,
80
+
.release = wndwc37e_release,
81
+
.sema_set = wndwc37e_sema_set,
82
+
.sema_clr = wndwc37e_sema_clr,
83
+
.ntfy_set = wndwc37e_ntfy_set,
84
+
.ntfy_clr = wndwc37e_ntfy_clr,
85
+
.ntfy_reset = corec37d_ntfy_init,
86
+
.ntfy_wait_begun = base507c_ntfy_wait_begun,
87
+
.ilut = wndwc57e_ilut,
88
+
.ilut_identity = true,
89
+
.ilut_size = 1024,
90
+
.xlut_set = wndwc57e_ilut_set,
91
+
.xlut_clr = wndwc57e_ilut_clr,
92
+
.csc = base907c_csc,
93
+
.csc_set = wndwc57e_csc_set,
94
+
.csc_clr = wndwc57e_csc_clr,
95
+
.image_set = wndwc67e_image_set,
96
+
.image_clr = wndwc37e_image_clr,
97
+
.blend_set = wndwc37e_blend_set,
98
+
.update = wndwc37e_update,
99
+
};
100
+
101
+
int
102
+
wndwc67e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
103
+
s32 oclass, struct nv50_wndw **pwndw)
104
+
{
105
+
return wndwc37e_new_(&wndwc67e, drm, type, index, oclass, BIT(index >> 1), pwndw);
106
+
}
+1
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+1
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+5
drivers/gpu/drm/nouveau/include/nvif/class.h
+5
drivers/gpu/drm/nouveau/include/nvif/class.h
···
88
88
#define GP102_DISP /* cl5070.h */ 0x00009870
89
89
#define GV100_DISP /* cl5070.h */ 0x0000c370
90
90
#define TU102_DISP /* cl5070.h */ 0x0000c570
91
+
#define GA102_DISP /* cl5070.h */ 0x0000c670
91
92
92
93
#define GV100_DISP_CAPS 0x0000c373
93
94
···
104
103
#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
105
104
#define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a
106
105
#define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a
106
+
#define GA102_DISP_CURSOR /* cl507a.h */ 0x0000c67a
107
107
108
108
#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
109
109
#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
···
114
112
115
113
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b
116
114
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b
115
+
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c67b
117
116
118
117
#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
119
118
#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
···
138
135
#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
139
136
#define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d
140
137
#define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d
138
+
#define GA102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c67d
141
139
142
140
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
143
141
#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
···
149
145
150
146
#define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e
151
147
#define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e
148
+
#define GA102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c67e
152
149
153
150
#define NV50_TESLA 0x00005097
154
151
#define G82_TESLA 0x00008297
+1
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+1
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+1
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
+1
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
···
37
37
int gp102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
38
38
int gv100_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
39
39
int tu102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
40
+
int ga102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
40
41
#endif
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
···
32
32
int gm200_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
33
33
int gv100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
34
34
int tu102_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
35
+
int ga100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
35
36
#endif
+2
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+2
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
···
86
86
int gp102_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
87
87
int gp10b_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
88
88
int gv100_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
89
+
int ga100_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
90
+
int ga102_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
89
91
90
92
#include <subdev/bios.h>
91
93
#include <subdev/bios/ramcfg.h>
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
···
37
37
int g94_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
38
38
int gf119_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
39
39
int gk104_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
40
+
int ga102_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **);
40
41
#endif
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
+1
drivers/gpu/drm/nouveau/nouveau_backlight.c
+1
drivers/gpu/drm/nouveau/nouveau_backlight.c
+1
drivers/gpu/drm/nouveau/nvif/disp.c
+1
drivers/gpu/drm/nouveau/nvif/disp.c
+72
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+72
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
···
2652
2652
.sec2 = tu102_sec2_new,
2653
2653
};
2654
2654
2655
+
static const struct nvkm_device_chip
2656
+
nv170_chipset = {
2657
+
.name = "GA100",
2658
+
.bar = tu102_bar_new,
2659
+
.bios = nvkm_bios_new,
2660
+
.devinit = ga100_devinit_new,
2661
+
.fb = ga100_fb_new,
2662
+
.gpio = gk104_gpio_new,
2663
+
.i2c = gm200_i2c_new,
2664
+
.ibus = gm200_ibus_new,
2665
+
.imem = nv50_instmem_new,
2666
+
.mc = ga100_mc_new,
2667
+
.mmu = tu102_mmu_new,
2668
+
.pci = gp100_pci_new,
2669
+
.timer = gk20a_timer_new,
2670
+
};
2671
+
2672
+
static const struct nvkm_device_chip
2673
+
nv172_chipset = {
2674
+
.name = "GA102",
2675
+
.bar = tu102_bar_new,
2676
+
.bios = nvkm_bios_new,
2677
+
.devinit = ga100_devinit_new,
2678
+
.fb = ga102_fb_new,
2679
+
.gpio = ga102_gpio_new,
2680
+
.i2c = gm200_i2c_new,
2681
+
.ibus = gm200_ibus_new,
2682
+
.imem = nv50_instmem_new,
2683
+
.mc = ga100_mc_new,
2684
+
.mmu = tu102_mmu_new,
2685
+
.pci = gp100_pci_new,
2686
+
.timer = gk20a_timer_new,
2687
+
.disp = ga102_disp_new,
2688
+
.dma = gv100_dma_new,
2689
+
};
2690
+
2691
+
static const struct nvkm_device_chip
2692
+
nv174_chipset = {
2693
+
.name = "GA104",
2694
+
.bar = tu102_bar_new,
2695
+
.bios = nvkm_bios_new,
2696
+
.devinit = ga100_devinit_new,
2697
+
.fb = ga102_fb_new,
2698
+
.gpio = ga102_gpio_new,
2699
+
.i2c = gm200_i2c_new,
2700
+
.ibus = gm200_ibus_new,
2701
+
.imem = nv50_instmem_new,
2702
+
.mc = ga100_mc_new,
2703
+
.mmu = tu102_mmu_new,
2704
+
.pci = gp100_pci_new,
2705
+
.timer = gk20a_timer_new,
2706
+
.disp = ga102_disp_new,
2707
+
.dma = gv100_dma_new,
2708
+
};
2709
+
2655
2710
static int
2656
2711
nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
2657
2712
struct nvkm_notify *notify)
···
3118
3063
case 0x130: device->card_type = GP100; break;
3119
3064
case 0x140: device->card_type = GV100; break;
3120
3065
case 0x160: device->card_type = TU100; break;
3066
+
case 0x170: device->card_type = GA100; break;
3121
3067
default:
3122
3068
break;
3123
3069
}
···
3216
3160
case 0x166: device->chip = &nv166_chipset; break;
3217
3161
case 0x167: device->chip = &nv167_chipset; break;
3218
3162
case 0x168: device->chip = &nv168_chipset; break;
3163
+
case 0x172: device->chip = &nv172_chipset; break;
3164
+
case 0x174: device->chip = &nv174_chipset; break;
3219
3165
default:
3220
-
nvdev_error(device, "unknown chipset (%08x)\n", boot0);
3221
-
ret = -ENODEV;
3222
-
goto done;
3166
+
if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3167
+
switch (device->chipset) {
3168
+
case 0x170: device->chip = &nv170_chipset; break;
3169
+
default:
3170
+
break;
3171
+
}
3172
+
}
3173
+
3174
+
if (!device->chip) {
3175
+
nvdev_error(device, "unknown chipset (%08x)\n", boot0);
3176
+
ret = -ENODEV;
3177
+
goto done;
3178
+
}
3179
+
break;
3223
3180
}
3224
3181
3225
3182
nvdev_info(device, "NVIDIA %s (%08x)\n",
+1
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+1
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
···
176
176
case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;
177
177
case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;
178
178
case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;
179
+
case GA100: args->v0.family = NV_DEVICE_INFO_V0_AMPERE; break;
179
180
default:
180
181
args->v0.family = 0;
181
182
break;
+3
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
+3
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
···
17
17
nvkm-y += nvkm/engine/disp/gp102.o
18
18
nvkm-y += nvkm/engine/disp/gv100.o
19
19
nvkm-y += nvkm/engine/disp/tu102.o
20
+
nvkm-y += nvkm/engine/disp/ga102.o
20
21
nvkm-y += nvkm/engine/disp/vga.o
21
22
22
23
nvkm-y += nvkm/engine/disp/head.o
···
43
42
nvkm-y += nvkm/engine/disp/sorgp100.o
44
43
nvkm-y += nvkm/engine/disp/sorgv100.o
45
44
nvkm-y += nvkm/engine/disp/sortu102.o
45
+
nvkm-y += nvkm/engine/disp/sorga102.o
46
46
47
47
nvkm-y += nvkm/engine/disp/outp.o
48
48
nvkm-y += nvkm/engine/disp/dp.o
···
77
75
nvkm-y += nvkm/engine/disp/rootgp102.o
78
76
nvkm-y += nvkm/engine/disp/rootgv100.o
79
77
nvkm-y += nvkm/engine/disp/roottu102.o
78
+
nvkm-y += nvkm/engine/disp/rootga102.o
80
79
81
80
nvkm-y += nvkm/engine/disp/capsgv100.o
82
81
+27
-6
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
+27
-6
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
···
33
33
34
34
#include <nvif/event.h>
35
35
36
+
/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for
37
+
* the x86 option ROM. However, the relevant VBIOS table versions weren't modified,
38
+
* so we're unable to detect this in a nice way.
39
+
*/
40
+
#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
41
+
36
42
struct lt_state {
37
43
struct nvkm_dp *dp;
38
44
u8 stat[6];
···
244
238
dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
245
239
lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
246
240
241
+
if (AMPERE_IED_HACK(disp) && (lnkcmp = lt.dp->info.script[0])) {
242
+
/* Execute BeforeLinkTraining script from DP Info table. */
243
+
while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
244
+
lnkcmp += 3;
245
+
lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
246
+
247
+
nvbios_init(&dp->outp.disp->engine.subdev, lnkcmp,
248
+
init.outp = &dp->outp.info;
249
+
init.or = ior->id;
250
+
init.link = ior->asy.link;
251
+
);
252
+
}
253
+
247
254
/* Set desired link configuration on the source. */
248
255
if ((lnkcmp = lt.dp->info.lnkcmp)) {
249
256
if (dp->version < 0x30) {
···
335
316
);
336
317
}
337
318
338
-
/* Execute BeforeLinkTraining script from DP Info table. */
339
-
nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
340
-
init.outp = &dp->outp.info;
341
-
init.or = dp->outp.ior->id;
342
-
init.link = dp->outp.ior->asy.link;
343
-
);
319
+
if (!AMPERE_IED_HACK(dp->outp.disp)) {
320
+
/* Execute BeforeLinkTraining script from DP Info table. */
321
+
nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
322
+
init.outp = &dp->outp.info;
323
+
init.or = dp->outp.ior->id;
324
+
init.link = dp->outp.ior->asy.link;
325
+
);
326
+
}
344
327
}
345
328
346
329
static const struct dp_rates {
+46
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
+46
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "nv50.h"
23
+
#include "head.h"
24
+
#include "ior.h"
25
+
#include "channv50.h"
26
+
#include "rootnv50.h"
27
+
28
+
static const struct nv50_disp_func
29
+
ga102_disp = {
30
+
.init = tu102_disp_init,
31
+
.fini = gv100_disp_fini,
32
+
.intr = gv100_disp_intr,
33
+
.uevent = &gv100_disp_chan_uevent,
34
+
.super = gv100_disp_super,
35
+
.root = &ga102_disp_root_oclass,
36
+
.wndw = { .cnt = gv100_disp_wndw_cnt },
37
+
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
38
+
.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
39
+
.ramht_size = 0x2000,
40
+
};
41
+
42
+
int
43
+
ga102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
44
+
{
45
+
return nv50_disp_new_(&ga102_disp, device, index, pdisp);
46
+
}
+4
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+4
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
···
150
150
void gv100_sor_dp_audio_sym(struct nvkm_ior *, int, u16, u32);
151
151
void gv100_sor_dp_watermark(struct nvkm_ior *, int, u8);
152
152
153
+
void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16);
154
+
153
155
void g84_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
154
156
void gt215_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
155
157
void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
···
209
207
int gv100_sor_new(struct nvkm_disp *, int);
210
208
211
209
int tu102_sor_new(struct nvkm_disp *, int);
210
+
211
+
int ga102_sor_new(struct nvkm_disp *, int);
212
212
#endif
+2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
+2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
···
86
86
void gv100_disp_super(struct work_struct *);
87
87
int gv100_disp_wndw_cnt(struct nvkm_disp *, unsigned long *);
88
88
89
+
int tu102_disp_init(struct nv50_disp *);
90
+
89
91
void nv50_disp_dptmds_war_2(struct nv50_disp *, struct dcb_output *);
90
92
void nv50_disp_dptmds_war_3(struct nv50_disp *, struct dcb_output *);
91
93
void nv50_disp_update_sppll1(struct nv50_disp *);
+52
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c
+52
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "rootnv50.h"
23
+
#include "channv50.h"
24
+
25
+
#include <nvif/class.h>
26
+
27
+
static const struct nv50_disp_root_func
28
+
ga102_disp_root = {
29
+
.user = {
30
+
{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
31
+
{{0,0,GA102_DISP_CURSOR }, gv100_disp_curs_new },
32
+
{{0,0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
33
+
{{0,0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
34
+
{{0,0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
35
+
{}
36
+
},
37
+
};
38
+
39
+
static int
40
+
ga102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
41
+
void *data, u32 size, struct nvkm_object **pobject)
42
+
{
43
+
return nv50_disp_root_new_(&ga102_disp_root, disp, oclass, data, size, pobject);
44
+
}
45
+
46
+
const struct nvkm_disp_oclass
47
+
ga102_disp_root_oclass = {
48
+
.base.oclass = GA102_DISP,
49
+
.base.minver = -1,
50
+
.base.maxver = -1,
51
+
.ctor = ga102_disp_root_new,
52
+
};
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
+140
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c
+140
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "ior.h"
23
+
24
+
#include <subdev/timer.h>
25
+
26
+
static int
27
+
ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
28
+
{
29
+
struct nvkm_device *device = sor->disp->engine.subdev.device;
30
+
const u32 soff = nv50_ior_base(sor);
31
+
const u32 loff = nv50_sor_link(sor);
32
+
u32 dpctrl = 0x00000000;
33
+
u32 clksor = 0x00000000;
34
+
35
+
switch (sor->dp.bw) {
36
+
case 0x06: clksor |= 0x00000000; break;
37
+
case 0x0a: clksor |= 0x00040000; break;
38
+
case 0x14: clksor |= 0x00080000; break;
39
+
case 0x1e: clksor |= 0x000c0000; break;
40
+
default:
41
+
WARN_ON(1);
42
+
return -EINVAL;
43
+
}
44
+
45
+
dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
46
+
if (sor->dp.mst)
47
+
dpctrl |= 0x40000000;
48
+
if (sor->dp.ef)
49
+
dpctrl |= 0x00004000;
50
+
51
+
nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
52
+
53
+
/*XXX*/
54
+
nvkm_msec(device, 40, NVKM_DELAY);
55
+
nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
56
+
nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
57
+
58
+
nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
59
+
return 0;
60
+
}
61
+
62
+
static void
63
+
ga102_sor_clock(struct nvkm_ior *sor)
64
+
{
65
+
struct nvkm_device *device = sor->disp->engine.subdev.device;
66
+
u32 div2 = 0;
67
+
if (sor->asy.proto == TMDS) {
68
+
if (sor->tmds.high_speed)
69
+
div2 = 1;
70
+
}
71
+
nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
72
+
nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
73
+
}
74
+
75
+
static const struct nvkm_ior_func
76
+
ga102_sor_hda = {
77
+
.route = {
78
+
.get = gm200_sor_route_get,
79
+
.set = gm200_sor_route_set,
80
+
},
81
+
.state = gv100_sor_state,
82
+
.power = nv50_sor_power,
83
+
.clock = ga102_sor_clock,
84
+
.hdmi = {
85
+
.ctrl = gv100_hdmi_ctrl,
86
+
.scdc = gm200_hdmi_scdc,
87
+
},
88
+
.dp = {
89
+
.lanes = { 0, 1, 2, 3 },
90
+
.links = ga102_sor_dp_links,
91
+
.power = g94_sor_dp_power,
92
+
.pattern = gm107_sor_dp_pattern,
93
+
.drive = gm200_sor_dp_drive,
94
+
.vcpi = tu102_sor_dp_vcpi,
95
+
.audio = gv100_sor_dp_audio,
96
+
.audio_sym = gv100_sor_dp_audio_sym,
97
+
.watermark = gv100_sor_dp_watermark,
98
+
},
99
+
.hda = {
100
+
.hpd = gf119_hda_hpd,
101
+
.eld = gf119_hda_eld,
102
+
.device_entry = gv100_hda_device_entry,
103
+
},
104
+
};
105
+
106
+
static const struct nvkm_ior_func
107
+
ga102_sor = {
108
+
.route = {
109
+
.get = gm200_sor_route_get,
110
+
.set = gm200_sor_route_set,
111
+
},
112
+
.state = gv100_sor_state,
113
+
.power = nv50_sor_power,
114
+
.clock = ga102_sor_clock,
115
+
.hdmi = {
116
+
.ctrl = gv100_hdmi_ctrl,
117
+
.scdc = gm200_hdmi_scdc,
118
+
},
119
+
.dp = {
120
+
.lanes = { 0, 1, 2, 3 },
121
+
.links = ga102_sor_dp_links,
122
+
.power = g94_sor_dp_power,
123
+
.pattern = gm107_sor_dp_pattern,
124
+
.drive = gm200_sor_dp_drive,
125
+
.vcpi = tu102_sor_dp_vcpi,
126
+
.audio = gv100_sor_dp_audio,
127
+
.audio_sym = gv100_sor_dp_audio_sym,
128
+
.watermark = gv100_sor_dp_watermark,
129
+
},
130
+
};
131
+
132
+
int
133
+
ga102_sor_new(struct nvkm_disp *disp, int id)
134
+
{
135
+
struct nvkm_device *device = disp->engine.subdev.device;
136
+
u32 hda = nvkm_rd32(device, 0x08a15c);
137
+
if (hda & BIT(id))
138
+
return nvkm_ior_new_(&ga102_sor_hda, disp, SOR, id);
139
+
return nvkm_ior_new_(&ga102_sor, disp, SOR, id);
140
+
}
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
+3
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
+3
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
···
64
64
return NULL;
65
65
66
66
/* we can't get the bios image pointer without PDISP */
67
+
if (device->card_type >= GA100)
68
+
addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */
69
+
else
67
70
if (device->card_type >= GM100)
68
71
addr = nvkm_rd32(device, 0x021c04);
69
72
else
+1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
+1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
+76
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
+76
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "nv50.h"
23
+
24
+
#include <subdev/bios.h>
25
+
#include <subdev/bios/pll.h>
26
+
#include <subdev/clk/pll.h>
27
+
28
+
static int
29
+
ga100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
30
+
{
31
+
struct nvkm_subdev *subdev = &init->subdev;
32
+
struct nvkm_device *device = subdev->device;
33
+
struct nvbios_pll info;
34
+
int head = type - PLL_VPLL0;
35
+
int N, fN, M, P;
36
+
int ret;
37
+
38
+
ret = nvbios_pll_parse(device->bios, type, &info);
39
+
if (ret)
40
+
return ret;
41
+
42
+
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
43
+
if (ret < 0)
44
+
return ret;
45
+
46
+
switch (info.type) {
47
+
case PLL_VPLL0:
48
+
case PLL_VPLL1:
49
+
case PLL_VPLL2:
50
+
case PLL_VPLL3:
51
+
nvkm_wr32(device, 0x00ef00 + (head * 0x40), 0x02080004);
52
+
nvkm_wr32(device, 0x00ef18 + (head * 0x40), (N << 16) | fN);
53
+
nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | M);
54
+
nvkm_wr32(device, 0x00e9c0 + (head * 0x04), 0x00000001);
55
+
break;
56
+
default:
57
+
nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq);
58
+
ret = -EINVAL;
59
+
break;
60
+
}
61
+
62
+
return ret;
63
+
}
64
+
65
+
static const struct nvkm_devinit_func
66
+
ga100_devinit = {
67
+
.init = nv50_devinit_init,
68
+
.post = tu102_devinit_post,
69
+
.pll_set = ga100_devinit_pll_set,
70
+
};
71
+
72
+
int
73
+
ga100_devinit_new(struct nvkm_device *device, int index, struct nvkm_devinit **pinit)
74
+
{
75
+
return nv50_devinit_new_(&ga100_devinit, device, index, pinit);
76
+
}
+1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
+3
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
+3
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
···
32
32
nvkm-y += nvkm/subdev/fb/gp102.o
33
33
nvkm-y += nvkm/subdev/fb/gp10b.o
34
34
nvkm-y += nvkm/subdev/fb/gv100.o
35
+
nvkm-y += nvkm/subdev/fb/ga100.o
36
+
nvkm-y += nvkm/subdev/fb/ga102.o
35
37
36
38
nvkm-y += nvkm/subdev/fb/ram.o
37
39
nvkm-y += nvkm/subdev/fb/ramnv04.o
···
54
52
nvkm-y += nvkm/subdev/fb/ramgm107.o
55
53
nvkm-y += nvkm/subdev/fb/ramgm200.o
56
54
nvkm-y += nvkm/subdev/fb/ramgp100.o
55
+
nvkm-y += nvkm/subdev/fb/ramga102.o
57
56
nvkm-y += nvkm/subdev/fb/sddr2.o
58
57
nvkm-y += nvkm/subdev/fb/sddr3.o
59
58
nvkm-y += nvkm/subdev/fb/gddr3.o
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "gf100.h"
23
+
#include "ram.h"
24
+
25
+
static const struct nvkm_fb_func
26
+
ga100_fb = {
27
+
.dtor = gf100_fb_dtor,
28
+
.oneinit = gf100_fb_oneinit,
29
+
.init = gp100_fb_init,
30
+
.init_page = gv100_fb_init_page,
31
+
.init_unkn = gp100_fb_init_unkn,
32
+
.ram_new = gp100_ram_new,
33
+
.default_bigpage = 16,
34
+
};
35
+
36
+
int
37
+
ga100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
38
+
{
39
+
return gp102_fb_new_(&ga100_fb, device, index, pfb);
40
+
}
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "gf100.h"
23
+
#include "ram.h"
24
+
25
+
static const struct nvkm_fb_func
26
+
ga102_fb = {
27
+
.dtor = gf100_fb_dtor,
28
+
.oneinit = gf100_fb_oneinit,
29
+
.init = gp100_fb_init,
30
+
.init_page = gv100_fb_init_page,
31
+
.init_unkn = gp100_fb_init_unkn,
32
+
.ram_new = ga102_ram_new,
33
+
.default_bigpage = 16,
34
+
};
35
+
36
+
int
37
+
ga102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
38
+
{
39
+
return gp102_fb_new_(&ga102_fb, device, index, pfb);
40
+
}
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c
+40
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "ram.h"
23
+
24
+
#include <subdev/bios.h>
25
+
#include <subdev/bios/init.h>
26
+
#include <subdev/bios/rammap.h>
27
+
28
+
static const struct nvkm_ram_func
29
+
ga102_ram = {
30
+
};
31
+
32
+
int
33
+
ga102_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
34
+
{
35
+
struct nvkm_device *device = fb->subdev.device;
36
+
enum nvkm_ram_type type = nvkm_fb_bios_memtype(device->bios);
37
+
u32 size = nvkm_rd32(device, 0x1183a4);
38
+
39
+
return nvkm_ram_new_(&ga102_ram, fb, type, (u64)size << 20, pram);
40
+
}
+1
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
+1
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
+118
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c
+118
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "priv.h"
23
+
24
+
static void
25
+
ga102_gpio_reset(struct nvkm_gpio *gpio, u8 match)
26
+
{
27
+
struct nvkm_device *device = gpio->subdev.device;
28
+
struct nvkm_bios *bios = device->bios;
29
+
u8 ver, len;
30
+
u16 entry;
31
+
int ent = -1;
32
+
33
+
while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
34
+
u32 data = nvbios_rd32(bios, entry);
35
+
u8 line = (data & 0x0000003f);
36
+
u8 defs = !!(data & 0x00000080);
37
+
u8 func = (data & 0x0000ff00) >> 8;
38
+
u8 unk0 = (data & 0x00ff0000) >> 16;
39
+
u8 unk1 = (data & 0x1f000000) >> 24;
40
+
41
+
if ( func == DCB_GPIO_UNUSED ||
42
+
(match != DCB_GPIO_UNUSED && match != func))
43
+
continue;
44
+
45
+
nvkm_gpio_set(gpio, 0, func, line, defs);
46
+
47
+
nvkm_mask(device, 0x021200 + (line * 4), 0xff, unk0);
48
+
if (unk1--)
49
+
nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line);
50
+
}
51
+
}
52
+
53
+
static int
54
+
ga102_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
55
+
{
56
+
struct nvkm_device *device = gpio->subdev.device;
57
+
u32 data = ((dir ^ 1) << 13) | (out << 12);
58
+
nvkm_mask(device, 0x021200 + (line * 4), 0x00003000, data);
59
+
nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */
60
+
return 0;
61
+
}
62
+
63
+
static int
64
+
ga102_gpio_sense(struct nvkm_gpio *gpio, int line)
65
+
{
66
+
struct nvkm_device *device = gpio->subdev.device;
67
+
return !!(nvkm_rd32(device, 0x021200 + (line * 4)) & 0x00004000);
68
+
}
69
+
70
+
static void
71
+
ga102_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
72
+
{
73
+
struct nvkm_device *device = gpio->subdev.device;
74
+
u32 intr0 = nvkm_rd32(device, 0x021640);
75
+
u32 intr1 = nvkm_rd32(device, 0x02164c);
76
+
u32 stat0 = nvkm_rd32(device, 0x021648) & intr0;
77
+
u32 stat1 = nvkm_rd32(device, 0x021654) & intr1;
78
+
*lo = (stat1 & 0xffff0000) | (stat0 >> 16);
79
+
*hi = (stat1 << 16) | (stat0 & 0x0000ffff);
80
+
nvkm_wr32(device, 0x021640, intr0);
81
+
nvkm_wr32(device, 0x02164c, intr1);
82
+
}
83
+
84
+
static void
85
+
ga102_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
86
+
{
87
+
struct nvkm_device *device = gpio->subdev.device;
88
+
u32 inte0 = nvkm_rd32(device, 0x021648);
89
+
u32 inte1 = nvkm_rd32(device, 0x021654);
90
+
if (type & NVKM_GPIO_LO)
91
+
inte0 = (inte0 & ~(mask << 16)) | (data << 16);
92
+
if (type & NVKM_GPIO_HI)
93
+
inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
94
+
mask >>= 16;
95
+
data >>= 16;
96
+
if (type & NVKM_GPIO_LO)
97
+
inte1 = (inte1 & ~(mask << 16)) | (data << 16);
98
+
if (type & NVKM_GPIO_HI)
99
+
inte1 = (inte1 & ~mask) | data;
100
+
nvkm_wr32(device, 0x021648, inte0);
101
+
nvkm_wr32(device, 0x021654, inte1);
102
+
}
103
+
104
+
static const struct nvkm_gpio_func
105
+
ga102_gpio = {
106
+
.lines = 32,
107
+
.intr_stat = ga102_gpio_intr_stat,
108
+
.intr_mask = ga102_gpio_intr_mask,
109
+
.drive = ga102_gpio_drive,
110
+
.sense = ga102_gpio_sense,
111
+
.reset = ga102_gpio_reset,
112
+
};
113
+
114
+
int
115
+
ga102_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio)
116
+
{
117
+
return nvkm_gpio_new_(&ga102_gpio, device, index, pgpio);
118
+
}
+1
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
+1
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
+74
drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c
+74
drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c
···
1
+
/*
2
+
* Copyright 2021 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "priv.h"
23
+
24
+
static void
25
+
ga100_mc_intr_unarm(struct nvkm_mc *mc)
26
+
{
27
+
nvkm_wr32(mc->subdev.device, 0xb81610, 0x00000004);
28
+
}
29
+
30
+
static void
31
+
ga100_mc_intr_rearm(struct nvkm_mc *mc)
32
+
{
33
+
nvkm_wr32(mc->subdev.device, 0xb81608, 0x00000004);
34
+
}
35
+
36
+
static void
37
+
ga100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 intr)
38
+
{
39
+
nvkm_wr32(mc->subdev.device, 0xb81210, mask & intr );
40
+
nvkm_wr32(mc->subdev.device, 0xb81410, mask & ~(mask & intr));
41
+
}
42
+
43
+
static u32
44
+
ga100_mc_intr_stat(struct nvkm_mc *mc)
45
+
{
46
+
u32 intr_top = nvkm_rd32(mc->subdev.device, 0xb81600), intr = 0x00000000;
47
+
if (intr_top & 0x00000004)
48
+
intr = nvkm_mask(mc->subdev.device, 0xb81010, 0x00000000, 0x00000000);
49
+
return intr;
50
+
}
51
+
52
+
static void
53
+
ga100_mc_init(struct nvkm_mc *mc)
54
+
{
55
+
nv50_mc_init(mc);
56
+
nvkm_wr32(mc->subdev.device, 0xb81210, 0xffffffff);
57
+
}
58
+
59
+
static const struct nvkm_mc_func
60
+
ga100_mc = {
61
+
.init = ga100_mc_init,
62
+
.intr = gp100_mc_intr,
63
+
.intr_unarm = ga100_mc_intr_unarm,
64
+
.intr_rearm = ga100_mc_intr_rearm,
65
+
.intr_mask = ga100_mc_intr_mask,
66
+
.intr_stat = ga100_mc_intr_stat,
67
+
.reset = gk104_mc_reset,
68
+
};
69
+
70
+
int
71
+
ga100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
72
+
{
73
+
return nvkm_mc_new_(&ga100_mc, device, index, pmc);
74
+
}