···117117 if (r)118118 return r;119119120120- /* programm the VCPU memory controller bits 0-27 */120120+ /* program the VCPU memory controller bits 0-27 */121121 addr = (rdev->uvd.gpu_addr >> 3) + 16;122122 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;123123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);···360360 /* Set the write pointer delay */361361 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);362362363363- /* programm the 4GB memory segment for rptr and ring buffer */363363+ /* program the 4GB memory segment for rptr and ring buffer */364364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |365365 (0x7 << 16) | (0x1 << 31));366366
+1-1
drivers/gpu/drm/radeon/uvd_v2_2.c
···109109 if (r)110110 return r;111111112112- /* programm the VCPU memory controller bits 0-27 */112112+ /* program the VCPU memory controller bits 0-27 */113113 addr = rdev->uvd.gpu_addr >> 3;114114 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;115115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
+1-1
drivers/gpu/drm/radeon/uvd_v4_2.c
···4040 uint64_t addr;4141 uint32_t size;42424343- /* programm the VCPU memory controller bits 0-27 */4343+ /* program the VCPU memory controller bits 0-27 */44444545 /* skip over the header of the new firmware format */4646 if (rdev->uvd.fw_header_present)