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dt-bindings: media: camss: Add qcom,sdm670-camss
As found in the Pixel 3a, the Snapdragon 670 has a camera subsystem with
3 CSIDs and 3 VFEs (including 1 VFE lite). Add this camera subsystem to
the bindings.
Adapted from SC8280XP camera subsystem.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
authored by
Richard Acayan
and committed by
Hans Verkuil
0274ea59
bb77ddc4
+318
+318
Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
+318
Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM670 Camera Subsystem (CAMSS)
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maintainers:
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- Richard Acayan <mailingradian@gmail.com>
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description:
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sdm670-camss
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reg:
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maxItems: 9
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reg-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite
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interrupts:
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maxItems: 9
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite
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clocks:
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maxItems: 22
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clock-names:
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items:
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- const: camnoc_axi
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- const: cpas_ahb
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- const: csi0
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- const: csi1
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- const: csi2
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: gcc_camera_ahb
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- const: gcc_camera_axi
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- const: soc_ahb
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- const: vfe0
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- const: vfe0_axi
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- const: vfe0_cphy_rx
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- const: vfe1
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- const: vfe1_axi
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- const: vfe1_cphy_rx
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- const: vfe_lite
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- const: vfe_lite_cphy_rx
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iommus:
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maxItems: 4
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power-domains:
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items:
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- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: ife0
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- const: ife1
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- const: top
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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vdda-pll-supply:
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description:
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Phandle to 1.8V regulator supply to PHY refclk pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data from CSIPHY0.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data from CSIPHY1.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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+
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required:
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- clock-lanes
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- data-lanes
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port@2:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data from CSIPHY2.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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maxItems: 1
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- clock-lanes
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- data-lanes
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- iommus
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- power-domains
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- power-domain-names
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- vdda-phy-supply
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- vdda-pll-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,camcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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isp@acb3000 {
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compatible = "qcom,sdm670-camss";
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reg = <0 0x0acb3000 0 0x1000>,
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<0 0x0acba000 0 0x1000>,
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<0 0x0acc8000 0 0x1000>,
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<0 0x0ac65000 0 0x1000>,
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<0 0x0ac66000 0 0x1000>,
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<0 0x0ac67000 0 0x1000>,
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<0 0x0acaf000 0 0x4000>,
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<0 0x0acb6000 0 0x4000>,
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<0 0x0acc4000 0 0x4000>;
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reg-names = "csid0",
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"csid1",
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"csid2",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"vfe0",
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"vfe1",
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"vfe_lite";
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interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csid0",
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"csid1",
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"csid2",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"vfe0",
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"vfe1",
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"vfe_lite";
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_CSID_CLK>,
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<&camcc CAM_CC_IFE_1_CSID_CLK>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>,
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<&gcc GCC_CAMERA_AXI_CLK>,
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<&camcc CAM_CC_SOC_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_AXI_CLK>,
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<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_AXI_CLK>,
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<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_CLK>,
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"csi0",
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"csi1",
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"csi2",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"gcc_camera_ahb",
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"gcc_camera_axi",
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"soc_ahb",
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"vfe0",
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"vfe0_axi",
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"vfe0_cphy_rx",
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"vfe1",
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"vfe1_axi",
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"vfe1_cphy_rx",
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"vfe_lite",
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"vfe_lite_cphy_rx";
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+
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iommus = <&apps_smmu 0x808 0x0>,
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<&apps_smmu 0x810 0x8>,
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<&apps_smmu 0xc08 0x0>,
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<&apps_smmu 0xc10 0x8>;
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+
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power-domains = <&camcc IFE_0_GDSC>,
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<&camcc IFE_1_GDSC>,
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<&camcc TITAN_TOP_GDSC>;
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power-domain-names = "ife0",
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"ife1",
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"top";
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vdda-phy-supply = <&vreg_l1a_1p225>;
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vdda-pll-supply = <&vreg_l8a_1p8>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csiphy_ep0: endpoint {
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clock-lanes = <7>;
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data-lanes = <0 1 2 3>;
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remote-endpoint = <&front_sensor_ep>;
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};
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};
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};
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};
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};