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arcmsr: Split dma resource allocation to a new function

Split dma resource allocation and io register assignment from get_config
to a new function arcmsr_alloc_io_queue.

Signed-off-by: Ching Huang <ching2048@areca.com.tw>
Reviewed-by: Tomas Henzl <thenzl@redhat.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

authored by

Ching Huang and committed by
Martin K. Petersen 02040670 f75ab39a

+93 -82
+93 -82
drivers/scsi/arcmsr/arcmsr_hba.c
··· 498 498 } 499 499 } 500 500 501 + static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb) 502 + { 503 + bool rtn = true; 504 + void *dma_coherent; 505 + dma_addr_t dma_coherent_handle; 506 + struct pci_dev *pdev = acb->pdev; 507 + 508 + switch (acb->adapter_type) { 509 + case ACB_ADAPTER_TYPE_B: { 510 + struct MessageUnit_B *reg; 511 + acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32); 512 + dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize, 513 + &dma_coherent_handle, GFP_KERNEL); 514 + if (!dma_coherent) { 515 + pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 516 + return false; 517 + } 518 + acb->dma_coherent_handle2 = dma_coherent_handle; 519 + acb->dma_coherent2 = dma_coherent; 520 + reg = (struct MessageUnit_B *)dma_coherent; 521 + acb->pmuB = reg; 522 + if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 523 + reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 524 + reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 525 + reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 526 + reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 527 + } else { 528 + reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 529 + reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 530 + reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 531 + reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 532 + } 533 + reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 534 + reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 535 + reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 536 + } 537 + break; 538 + case ACB_ADAPTER_TYPE_D: { 539 + struct MessageUnit_D *reg; 540 + 541 + acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32); 542 + dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize, 543 + &dma_coherent_handle, GFP_KERNEL); 544 + if (!dma_coherent) { 545 + pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 546 + return false; 547 + } 548 + acb->dma_coherent_handle2 = dma_coherent_handle; 549 + acb->dma_coherent2 = dma_coherent; 550 + reg = (struct MessageUnit_D *)dma_coherent; 551 + acb->pmuD = reg; 552 + reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 553 + reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 554 + reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 555 + reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 556 + reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 557 + reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 558 + reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 559 + reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 560 + reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 561 + reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 562 + reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 563 + reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 564 + reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 565 + reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 566 + reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 567 + reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 568 + reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 569 + reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 570 + reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 571 + reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 572 + reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 573 + reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 574 + reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 575 + reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 576 + reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 577 + reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 578 + } 579 + break; 580 + default: 581 + break; 582 + } 583 + return rtn; 584 + } 585 + 501 586 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb) 502 587 { 503 588 struct pci_dev *pdev = acb->pdev; ··· 827 742 if(!error){ 828 743 goto pci_release_regs; 829 744 } 745 + error = arcmsr_alloc_io_queue(acb); 746 + if (!error) 747 + goto unmap_pci_region; 830 748 error = arcmsr_get_firmware_spec(acb); 831 749 if(!error){ 832 - goto unmap_pci_region; 750 + goto free_hbb_mu; 833 751 } 834 752 error = arcmsr_alloc_ccb_pool(acb); 835 753 if(error){ ··· 2712 2624 } 2713 2625 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb) 2714 2626 { 2715 - struct MessageUnit_B *reg; 2716 - struct pci_dev *pdev = acb->pdev; 2717 - void *dma_coherent; 2718 - dma_addr_t dma_coherent_handle; 2627 + struct MessageUnit_B *reg = acb->pmuB; 2719 2628 char *acb_firm_model = acb->firm_model; 2720 2629 char *acb_firm_version = acb->firm_version; 2721 2630 char *acb_device_map = acb->device_map; ··· 2724 2639 /*firm_version,21,84-99*/ 2725 2640 int count; 2726 2641 2727 - acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32); 2728 - dma_coherent = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize, 2729 - &dma_coherent_handle, GFP_KERNEL); 2730 - if (!dma_coherent){ 2731 - printk(KERN_NOTICE 2732 - "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", 2733 - acb->host->host_no); 2734 - return false; 2735 - } 2736 - acb->dma_coherent_handle2 = dma_coherent_handle; 2737 - acb->dma_coherent2 = dma_coherent; 2738 - reg = (struct MessageUnit_B *)dma_coherent; 2739 - acb->pmuB = reg; 2740 - if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 2741 - reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 2742 - reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 2743 - reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 2744 - reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 2745 - } else { 2746 - reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 2747 - reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 2748 - reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 2749 - reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 2750 - } 2751 - reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 2752 - reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 2753 - reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 2754 2642 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/ 2755 2643 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/ 2756 2644 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/ ··· 2732 2674 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 2733 2675 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 2734 2676 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no); 2735 - goto err_free_dma; 2677 + return false; 2736 2678 } 2737 2679 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 2738 2680 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 2739 2681 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 2740 2682 miscellaneous data' timeout \n", acb->host->host_no); 2741 - goto err_free_dma; 2683 + return false; 2742 2684 } 2743 2685 count = 8; 2744 2686 while (count){ ··· 2781 2723 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/ 2782 2724 /*firm_ide_channels,4,16-19*/ 2783 2725 return true; 2784 - err_free_dma: 2785 - dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize, 2786 - acb->dma_coherent2, acb->dma_coherent_handle2); 2787 - return false; 2788 2726 } 2789 2727 2790 2728 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB) ··· 2851 2797 char __iomem *iop_firm_version; 2852 2798 char __iomem *iop_device_map; 2853 2799 u32 count; 2854 - struct MessageUnit_D *reg; 2855 - void *dma_coherent2; 2856 - dma_addr_t dma_coherent_handle2; 2857 - struct pci_dev *pdev = acb->pdev; 2800 + struct MessageUnit_D *reg = acb->pmuD; 2858 2801 2859 - acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32); 2860 - dma_coherent2 = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize, 2861 - &dma_coherent_handle2, GFP_KERNEL); 2862 - if (!dma_coherent2) { 2863 - pr_notice("DMA allocation failed...\n"); 2864 - return false; 2865 - } 2866 - memset(dma_coherent2, 0, acb->roundup_ccbsize); 2867 - acb->dma_coherent_handle2 = dma_coherent_handle2; 2868 - acb->dma_coherent2 = dma_coherent2; 2869 - reg = (struct MessageUnit_D *)dma_coherent2; 2870 - acb->pmuD = reg; 2871 - reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 2872 - reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 2873 - reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 2874 - reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 2875 - reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 2876 - reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 2877 - reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 2878 - reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 2879 - reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 2880 - reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 2881 - reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 2882 - reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 2883 - reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 2884 - reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 2885 - reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 2886 - reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 2887 - reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 2888 - reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 2889 - reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 2890 - reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 2891 - reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 2892 - reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 2893 - reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 2894 - reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 2895 - reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 2896 - reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 2897 2802 iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); 2898 2803 iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); 2899 2804 iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]); ··· 2867 2854 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 2868 2855 pr_notice("arcmsr%d: wait get adapter firmware " 2869 2856 "miscellaneous data timeout\n", acb->host->host_no); 2870 - dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize, 2871 - acb->dma_coherent2, acb->dma_coherent_handle2); 2872 2857 return false; 2873 2858 } 2874 2859 count = 8;