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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: zynqmp: Use DT header for firmware constants
Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it. That's why copy header
to platform folder (align macro) and use it locally.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c3f011812597f4c3095448726f5924b2334c7da1.1738600745.git.michal.simek@amd.com
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arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h
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arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Zynq MPSoC Firmware layer
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*
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* Copyright (C) 2014-2018 Xilinx, Inc.
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*
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*/
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#ifndef _XLNX_ZYNQMP_CLK_H
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#define _XLNX_ZYNQMP_CLK_H
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#define IOPLL 0
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#define RPLL 1
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#define APLL 2
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#define DPLL 3
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#define VPLL 4
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#define IOPLL_TO_FPD 5
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#define RPLL_TO_FPD 6
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#define APLL_TO_LPD 7
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#define DPLL_TO_LPD 8
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#define VPLL_TO_LPD 9
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#define ACPU 10
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#define ACPU_HALF 11
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#define DBF_FPD 12
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#define DBF_LPD 13
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#define DBG_TRACE 14
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#define DBG_TSTMP 15
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#define DP_VIDEO_REF 16
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#define DP_AUDIO_REF 17
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#define DP_STC_REF 18
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#define GDMA_REF 19
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#define DPDMA_REF 20
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#define DDR_REF 21
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#define SATA_REF 22
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#define PCIE_REF 23
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#define GPU_REF 24
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#define GPU_PP0_REF 25
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#define GPU_PP1_REF 26
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#define TOPSW_MAIN 27
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#define TOPSW_LSBUS 28
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#define GTGREF0_REF 29
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#define LPD_SWITCH 30
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#define LPD_LSBUS 31
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#define USB0_BUS_REF 32
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#define USB1_BUS_REF 33
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#define USB3_DUAL_REF 34
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#define USB0 35
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#define USB1 36
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#define CPU_R5 37
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#define CPU_R5_CORE 38
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#define CSU_SPB 39
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#define CSU_PLL 40
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#define PCAP 41
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#define IOU_SWITCH 42
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#define GEM_TSU_REF 43
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#define GEM_TSU 44
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#define GEM0_TX 45
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#define GEM1_TX 46
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#define GEM2_TX 47
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#define GEM3_TX 48
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#define GEM0_RX 49
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#define GEM1_RX 50
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#define GEM2_RX 51
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#define GEM3_RX 52
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#define QSPI_REF 53
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#define SDIO0_REF 54
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#define SDIO1_REF 55
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#define UART0_REF 56
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#define UART1_REF 57
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#define SPI0_REF 58
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#define SPI1_REF 59
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#define NAND_REF 60
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#define I2C0_REF 61
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#define I2C1_REF 62
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#define CAN0_REF 63
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#define CAN1_REF 64
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#define CAN0 65
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#define CAN1 66
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#define DLL_REF 67
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#define ADMA_REF 68
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#define TIMESTAMP_REF 69
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#define AMS_REF 70
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#define PL0_REF 71
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#define PL1_REF 72
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#define PL2_REF 73
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#define PL3_REF 74
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#define WDT 75
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#define IOPLL_INT 76
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#define IOPLL_PRE_SRC 77
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#define IOPLL_HALF 78
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#define IOPLL_INT_MUX 79
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#define IOPLL_POST_SRC 80
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#define RPLL_INT 81
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#define RPLL_PRE_SRC 82
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#define RPLL_HALF 83
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#define RPLL_INT_MUX 84
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#define RPLL_POST_SRC 85
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#define APLL_INT 86
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#define APLL_PRE_SRC 87
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#define APLL_HALF 88
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#define APLL_INT_MUX 89
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#define APLL_POST_SRC 90
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#define DPLL_INT 91
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#define DPLL_PRE_SRC 92
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#define DPLL_HALF 93
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#define DPLL_INT_MUX 94
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#define DPLL_POST_SRC 95
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#define VPLL_INT 96
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#define VPLL_PRE_SRC 97
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#define VPLL_HALF 98
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#define VPLL_INT_MUX 99
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#define VPLL_POST_SRC 100
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#define CAN0_MIO 101
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#define CAN1_MIO 102
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#define ACPU_FULL 103
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#define GEM0_REF 104
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#define GEM1_REF 105
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#define GEM2_REF 106
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#define GEM3_REF 107
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#define GEM0_REF_UNG 108
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#define GEM1_REF_UNG 109
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#define GEM2_REF_UNG 110
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#define GEM3_REF_UNG 111
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#define LPD_WDT 112
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#endif /* _XLNX_ZYNQMP_CLK_H */