Revert "drm/amd/display: Add Underflow Asserts to dc"

This reverts commit 9ed43ef84d9d1e668acdf43c95510fb7b11f8d71.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <[e-mail]>

drivers/gpu/drm/amd/display/dc/dc.h

···
 	int sr_exit_time_ns;
 	int sr_enter_plus_exit_time_ns;
 	int urgent_latency_ns;
-	uint32_t underflow_assert_delay_us;
 	int percent_of_ideal_drambw;
 	int dram_clock_change_latency_ns;
 	bool optimized_watermark;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

···
 	DTN_INFO_END();
 }
 
-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
-{
-	struct hubp *hubp = pipe_ctx->plane_res.hubp;
-	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
-	if (tg->funcs->is_optc_underflow_occurred(tg)) {
-		tg->funcs->clear_optc_underflow(tg);
-		return true;
-	}
-
-	if (hubp->funcs->hubp_get_underflow_status(hubp)) {
-		hubp->funcs->hubp_clear_underflow(hubp);
-		return true;
-	}
-	return false;
-}
-
 static void enable_power_gating_plane(
 	struct dce_hwseq *hws,
 	bool enable)
···
 {
 	int i;
 	struct timing_generator *tg;
-	uint32_t underflow_check_delay_us;
 	bool removed_pipe[4] = { false };
 	bool interdependent_update = false;
 	struct pipe_ctx *top_pipe_to_program =
···
 	interdependent_update = top_pipe_to_program->plane_state &&
 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
 
-	underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
-
-	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
-		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
-
 	if (interdependent_update)
 		lock_all_pipes(dc, context, true);
 	else
 		dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
-
-	if (underflow_check_delay_us != 0xFFFFFFFF)
-		udelay(underflow_check_delay_us);
-
-	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
-		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
 
 	if (num_planes == 0) {
 		/* OTG blank before remove all front end */
···
 	.disable_stream_gating = NULL,
 	.enable_stream_gating = NULL,
 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
-	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
-	.did_underflow_occur = dcn10_did_underflow_occur
+	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
 };
 
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

···
 		struct pipe_ctx *pipe_ctx,
 		struct tg_color *color);
 
-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
-
 void update_dchubp_dpp(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

···
 		.az_endpoint_mute_only = true,
 		.recovery_enabled = false, /*enable this by default after testing.*/
 		.max_downscale_src_width = 3840,
-		.underflow_assert_delay_us = 0xFFFFFFFF,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
···
 		.clock_trace = true,
 		.disable_stutter = true,
 		.disable_pplib_clock_request = true,
-		.disable_pplib_wm_range = true,
-		.underflow_assert_delay_us = 0xFFFFFFFF,
+		.disable_pplib_wm_range = true
 };
 
 static void dcn10_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

···
 
 	void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
-	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 
 };