···107107 }108108}109109110110-/* Enable / disable direct write to memory by the Camera Sensor Interface */110110+/* Enable direct write to memory by the Camera Sensor Interface */111111static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)112112{113113 uint32_t ic_conf, mask;···126126 idmac_write_icreg(ipu, ic_conf, IC_CONF);127127}128128129129+/* Called under spin_lock_irqsave(&ipu_data.lock) */129130static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)130131{131132 uint32_t ic_conf, mask;···423422 break;424423 default:425424 dev_err(ipu_data.dev,426426- "mxc ipu: unimplemented pixel format %d\n", pixel_fmt);425425+ "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);427426 break;428427 }429428···434433 uint16_t burst_pixels)435434{436435 params->pp.npb = burst_pixels - 1;437437-};436436+}438437439438static void ipu_ch_param_set_buffer(union chan_param_mem *params,440439 dma_addr_t buf0, dma_addr_t buf1)441440{442441 params->pp.eba0 = buf0;443442 params->pp.eba1 = buf1;444444-};443443+}445444446445static void ipu_ch_param_set_rotation(union chan_param_mem *params,447446 enum ipu_rotate_mode rotate)448447{449448 params->pp.bam = rotate;450450-};449449+}451450452451static void ipu_write_param_mem(uint32_t addr, uint32_t *data,453452 uint32_t num_words)···572571{573572 /* Channel Parameter Memory */574573 return 0x10000 | (dma_ch << 4);575575-};574574+}576575577576static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,578577 bool prio)···612611613612/**614613 * ipu_enable_channel() - enable an IPU channel.615615- * @channel: channel ID.614614+ * @idmac: IPU DMAC context.615615+ * @ichan: IDMAC channel.616616 * @return: 0 on success or negative error code on failure.617617 */618618static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)···651649652650/**653651 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.654654- * @channel: channel ID.652652+ * @ichan: IDMAC channel.655653 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.656654 * @width: width of buffer in pixels.657655 * @height: height of buffer in pixels.···689687 }690688691689 /* IC channel's stride must be a multiple of 8 pixels */692692- if ((channel <= 13) && (stride % 8)) {690690+ if ((channel <= IDMAC_IC_13) && (stride % 8)) {693691 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");694692 return -EINVAL;695693 }···754752755753/**756754 * ipu_update_channel_buffer() - update physical address of a channel buffer.757757- * @channel: channel ID.755755+ * @ichan: IDMAC channel.758756 * @buffer_n: buffer number to update.759757 * 0 or 1 are the only valid values.760758 * @phyaddr: buffer physical address.···13431341 }13441342}1345134313461346-/*13471347- * At the time .device_alloc_chan_resources() method is called, we cannot know,13481348- * whether the client will accept the channel. Thus we must only check, if we13491349- * can satisfy client's request but the only real criterion to verify, whether13501350- * the client has accepted our offer is the client_count. That's why we have to13511351- * perform the rest of our allocation tasks on the first call to this function.13521352- */13441344+/* Allocate and initialise a transfer descriptor. */13531345static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,13541346 struct scatterlist *sgl, unsigned int sg_len,13551347 enum dma_data_direction direction, unsigned long tx_flags)···14281432 struct idmac_tx_desc *desc = ichan->desc + i;14291433 if (list_empty(&desc->list))14301434 /* Descriptor was prepared, but not submitted */14311431- list_add(&desc->list,14321432- &ichan->free_list);14351435+ list_add(&desc->list, &ichan->free_list);1433143614341437 async_tx_clear_ack(&desc->txd);14351438 }