Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15

+98

Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 8 + 9 + maintainers: 10 + - Bjorn Andersson <andersson@kernel.org> 11 + - Anusha Rao <quic_anusha@quicinc.com> 12 + 13 + description: | 14 + Qualcomm networking sub system clock control module provides the clocks, 15 + resets on IPQ9574 16 + 17 + See also:: 18 + include/dt-bindings/clock/qcom,ipq9574-nsscc.h 19 + include/dt-bindings/reset/qcom,ipq9574-nsscc.h 20 + 21 + properties: 22 + compatible: 23 + const: qcom,ipq9574-nsscc 24 + 25 + clocks: 26 + items: 27 + - description: Board XO source 28 + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source 29 + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source 30 + - description: GCC GPLL0 OUT AUX clock source 31 + - description: Uniphy0 NSS Rx clock source 32 + - description: Uniphy0 NSS Tx clock source 33 + - description: Uniphy1 NSS Rx clock source 34 + - description: Uniphy1 NSS Tx clock source 35 + - description: Uniphy2 NSS Rx clock source 36 + - description: Uniphy2 NSS Tx clock source 37 + - description: GCC NSSCC clock source 38 + 39 + '#interconnect-cells': 40 + const: 1 41 + 42 + clock-names: 43 + items: 44 + - const: xo 45 + - const: nss_1200 46 + - const: ppe_353 47 + - const: gpll0_out 48 + - const: uniphy0_rx 49 + - const: uniphy0_tx 50 + - const: uniphy1_rx 51 + - const: uniphy1_tx 52 + - const: uniphy2_rx 53 + - const: uniphy2_tx 54 + - const: bus 55 + 56 + required: 57 + - compatible 58 + - clocks 59 + - clock-names 60 + 61 + allOf: 62 + - $ref: qcom,gcc.yaml# 63 + 64 + unevaluatedProperties: false 65 + 66 + examples: 67 + - | 68 + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 69 + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 70 + clock-controller@39b00000 { 71 + compatible = "qcom,ipq9574-nsscc"; 72 + reg = <0x39b00000 0x80000>; 73 + clocks = <&xo_board_clk>, 74 + <&cmn_pll NSS_1200MHZ_CLK>, 75 + <&cmn_pll PPE_353MHZ_CLK>, 76 + <&gcc GPLL0_OUT_AUX>, 77 + <&uniphy 0>, 78 + <&uniphy 1>, 79 + <&uniphy 2>, 80 + <&uniphy 3>, 81 + <&uniphy 4>, 82 + <&uniphy 5>, 83 + <&gcc GCC_NSSCC_CLK>; 84 + clock-names = "xo", 85 + "nss_1200", 86 + "ppe_353", 87 + "gpll0_out", 88 + "uniphy0_rx", 89 + "uniphy0_tx", 90 + "uniphy1_rx", 91 + "uniphy1_tx", 92 + "uniphy2_rx", 93 + "uniphy2_tx", 94 + "bus"; 95 + #clock-cells = <1>; 96 + #reset-cells = <1>; 97 + }; 98 + ...

+1

include/dt-bindings/clock/qcom,ipq9574-gcc.h

··· 202 202 #define GCC_PCIE1_PIPE_CLK 211 203 203 #define GCC_PCIE2_PIPE_CLK 212 204 204 #define GCC_PCIE3_PIPE_CLK 213 205 + #define GPLL0_OUT_AUX 214 205 206 #endif

+152

include/dt-bindings/clock/qcom,ipq9574-nsscc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H 7 + #define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H 8 + 9 + #define NSS_CC_CE_APB_CLK 0 10 + #define NSS_CC_CE_AXI_CLK 1 11 + #define NSS_CC_CE_CLK_SRC 2 12 + #define NSS_CC_CFG_CLK_SRC 3 13 + #define NSS_CC_CLC_AXI_CLK 4 14 + #define NSS_CC_CLC_CLK_SRC 5 15 + #define NSS_CC_CRYPTO_CLK 6 16 + #define NSS_CC_CRYPTO_CLK_SRC 7 17 + #define NSS_CC_CRYPTO_PPE_CLK 8 18 + #define NSS_CC_HAQ_AHB_CLK 9 19 + #define NSS_CC_HAQ_AXI_CLK 10 20 + #define NSS_CC_HAQ_CLK_SRC 11 21 + #define NSS_CC_IMEM_AHB_CLK 12 22 + #define NSS_CC_IMEM_CLK_SRC 13 23 + #define NSS_CC_IMEM_QSB_CLK 14 24 + #define NSS_CC_INT_CFG_CLK_SRC 15 25 + #define NSS_CC_NSS_CSR_CLK 16 26 + #define NSS_CC_NSSNOC_CE_APB_CLK 17 27 + #define NSS_CC_NSSNOC_CE_AXI_CLK 18 28 + #define NSS_CC_NSSNOC_CLC_AXI_CLK 19 29 + #define NSS_CC_NSSNOC_CRYPTO_CLK 20 30 + #define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 31 + #define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 32 + #define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 33 + #define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 34 + #define NSS_CC_NSSNOC_NSS_CSR_CLK 25 35 + #define NSS_CC_NSSNOC_PPE_CFG_CLK 26 36 + #define NSS_CC_NSSNOC_PPE_CLK 27 37 + #define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 38 + #define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 39 + #define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 40 + #define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 41 + #define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 42 + #define NSS_CC_PORT1_MAC_CLK 33 43 + #define NSS_CC_PORT1_RX_CLK 34 44 + #define NSS_CC_PORT1_RX_CLK_SRC 35 45 + #define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 46 + #define NSS_CC_PORT1_TX_CLK 37 47 + #define NSS_CC_PORT1_TX_CLK_SRC 38 48 + #define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 49 + #define NSS_CC_PORT2_MAC_CLK 40 50 + #define NSS_CC_PORT2_RX_CLK 41 51 + #define NSS_CC_PORT2_RX_CLK_SRC 42 52 + #define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 53 + #define NSS_CC_PORT2_TX_CLK 44 54 + #define NSS_CC_PORT2_TX_CLK_SRC 45 55 + #define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 56 + #define NSS_CC_PORT3_MAC_CLK 47 57 + #define NSS_CC_PORT3_RX_CLK 48 58 + #define NSS_CC_PORT3_RX_CLK_SRC 49 59 + #define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 60 + #define NSS_CC_PORT3_TX_CLK 51 61 + #define NSS_CC_PORT3_TX_CLK_SRC 52 62 + #define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 63 + #define NSS_CC_PORT4_MAC_CLK 54 64 + #define NSS_CC_PORT4_RX_CLK 55 65 + #define NSS_CC_PORT4_RX_CLK_SRC 56 66 + #define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 67 + #define NSS_CC_PORT4_TX_CLK 58 68 + #define NSS_CC_PORT4_TX_CLK_SRC 59 69 + #define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 70 + #define NSS_CC_PORT5_MAC_CLK 61 71 + #define NSS_CC_PORT5_RX_CLK 62 72 + #define NSS_CC_PORT5_RX_CLK_SRC 63 73 + #define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 74 + #define NSS_CC_PORT5_TX_CLK 65 75 + #define NSS_CC_PORT5_TX_CLK_SRC 66 76 + #define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 77 + #define NSS_CC_PORT6_MAC_CLK 68 78 + #define NSS_CC_PORT6_RX_CLK 69 79 + #define NSS_CC_PORT6_RX_CLK_SRC 70 80 + #define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 81 + #define NSS_CC_PORT6_TX_CLK 72 82 + #define NSS_CC_PORT6_TX_CLK_SRC 73 83 + #define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 84 + #define NSS_CC_PPE_CLK_SRC 75 85 + #define NSS_CC_PPE_EDMA_CFG_CLK 76 86 + #define NSS_CC_PPE_EDMA_CLK 77 87 + #define NSS_CC_PPE_SWITCH_BTQ_CLK 78 88 + #define NSS_CC_PPE_SWITCH_CFG_CLK 79 89 + #define NSS_CC_PPE_SWITCH_CLK 80 90 + #define NSS_CC_PPE_SWITCH_IPE_CLK 81 91 + #define NSS_CC_UBI0_CLK_SRC 82 92 + #define NSS_CC_UBI0_DIV_CLK_SRC 83 93 + #define NSS_CC_UBI1_CLK_SRC 84 94 + #define NSS_CC_UBI1_DIV_CLK_SRC 85 95 + #define NSS_CC_UBI2_CLK_SRC 86 96 + #define NSS_CC_UBI2_DIV_CLK_SRC 87 97 + #define NSS_CC_UBI32_AHB0_CLK 88 98 + #define NSS_CC_UBI32_AHB1_CLK 89 99 + #define NSS_CC_UBI32_AHB2_CLK 90 100 + #define NSS_CC_UBI32_AHB3_CLK 91 101 + #define NSS_CC_UBI32_AXI0_CLK 92 102 + #define NSS_CC_UBI32_AXI1_CLK 93 103 + #define NSS_CC_UBI32_AXI2_CLK 94 104 + #define NSS_CC_UBI32_AXI3_CLK 95 105 + #define NSS_CC_UBI32_CORE0_CLK 96 106 + #define NSS_CC_UBI32_CORE1_CLK 97 107 + #define NSS_CC_UBI32_CORE2_CLK 98 108 + #define NSS_CC_UBI32_CORE3_CLK 99 109 + #define NSS_CC_UBI32_INTR0_AHB_CLK 100 110 + #define NSS_CC_UBI32_INTR1_AHB_CLK 101 111 + #define NSS_CC_UBI32_INTR2_AHB_CLK 102 112 + #define NSS_CC_UBI32_INTR3_AHB_CLK 103 113 + #define NSS_CC_UBI32_NC_AXI0_CLK 104 114 + #define NSS_CC_UBI32_NC_AXI1_CLK 105 115 + #define NSS_CC_UBI32_NC_AXI2_CLK 106 116 + #define NSS_CC_UBI32_NC_AXI3_CLK 107 117 + #define NSS_CC_UBI32_UTCM0_CLK 108 118 + #define NSS_CC_UBI32_UTCM1_CLK 109 119 + #define NSS_CC_UBI32_UTCM2_CLK 110 120 + #define NSS_CC_UBI32_UTCM3_CLK 111 121 + #define NSS_CC_UBI3_CLK_SRC 112 122 + #define NSS_CC_UBI3_DIV_CLK_SRC 113 123 + #define NSS_CC_UBI_AXI_CLK_SRC 114 124 + #define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 125 + #define NSS_CC_UNIPHY_PORT1_RX_CLK 116 126 + #define NSS_CC_UNIPHY_PORT1_TX_CLK 117 127 + #define NSS_CC_UNIPHY_PORT2_RX_CLK 118 128 + #define NSS_CC_UNIPHY_PORT2_TX_CLK 119 129 + #define NSS_CC_UNIPHY_PORT3_RX_CLK 120 130 + #define NSS_CC_UNIPHY_PORT3_TX_CLK 121 131 + #define NSS_CC_UNIPHY_PORT4_RX_CLK 122 132 + #define NSS_CC_UNIPHY_PORT4_TX_CLK 123 133 + #define NSS_CC_UNIPHY_PORT5_RX_CLK 124 134 + #define NSS_CC_UNIPHY_PORT5_TX_CLK 125 135 + #define NSS_CC_UNIPHY_PORT6_RX_CLK 126 136 + #define NSS_CC_UNIPHY_PORT6_TX_CLK 127 137 + #define NSS_CC_XGMAC0_PTP_REF_CLK 128 138 + #define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 139 + #define NSS_CC_XGMAC1_PTP_REF_CLK 130 140 + #define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 141 + #define NSS_CC_XGMAC2_PTP_REF_CLK 132 142 + #define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 143 + #define NSS_CC_XGMAC3_PTP_REF_CLK 134 144 + #define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 145 + #define NSS_CC_XGMAC4_PTP_REF_CLK 136 146 + #define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 147 + #define NSS_CC_XGMAC5_PTP_REF_CLK 138 148 + #define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 149 + #define UBI32_PLL 140 150 + #define UBI32_PLL_MAIN 141 151 + 152 + #endif

+134

include/dt-bindings/reset/qcom,ipq9574-nsscc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H 7 + #define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H 8 + 9 + #define EDMA_HW_RESET 0 10 + #define NSS_CC_CE_BCR 1 11 + #define NSS_CC_CLC_BCR 2 12 + #define NSS_CC_EIP197_BCR 3 13 + #define NSS_CC_HAQ_BCR 4 14 + #define NSS_CC_IMEM_BCR 5 15 + #define NSS_CC_MAC_BCR 6 16 + #define NSS_CC_PPE_BCR 7 17 + #define NSS_CC_UBI_BCR 8 18 + #define NSS_CC_UNIPHY_BCR 9 19 + #define UBI3_CLKRST_CLAMP_ENABLE 10 20 + #define UBI3_CORE_CLAMP_ENABLE 11 21 + #define UBI2_CLKRST_CLAMP_ENABLE 12 22 + #define UBI2_CORE_CLAMP_ENABLE 13 23 + #define UBI1_CLKRST_CLAMP_ENABLE 14 24 + #define UBI1_CORE_CLAMP_ENABLE 15 25 + #define UBI0_CLKRST_CLAMP_ENABLE 16 26 + #define UBI0_CORE_CLAMP_ENABLE 17 27 + #define NSSNOC_NSS_CSR_ARES 18 28 + #define NSS_CSR_ARES 19 29 + #define PPE_BTQ_ARES 20 30 + #define PPE_IPE_ARES 21 31 + #define PPE_ARES 22 32 + #define PPE_CFG_ARES 23 33 + #define PPE_EDMA_ARES 24 34 + #define PPE_EDMA_CFG_ARES 25 35 + #define CRY_PPE_ARES 26 36 + #define NSSNOC_PPE_ARES 27 37 + #define NSSNOC_PPE_CFG_ARES 28 38 + #define PORT1_MAC_ARES 29 39 + #define PORT2_MAC_ARES 30 40 + #define PORT3_MAC_ARES 31 41 + #define PORT4_MAC_ARES 32 42 + #define PORT5_MAC_ARES 33 43 + #define PORT6_MAC_ARES 34 44 + #define XGMAC0_PTP_REF_ARES 35 45 + #define XGMAC1_PTP_REF_ARES 36 46 + #define XGMAC2_PTP_REF_ARES 37 47 + #define XGMAC3_PTP_REF_ARES 38 48 + #define XGMAC4_PTP_REF_ARES 39 49 + #define XGMAC5_PTP_REF_ARES 40 50 + #define HAQ_AHB_ARES 41 51 + #define HAQ_AXI_ARES 42 52 + #define NSSNOC_HAQ_AHB_ARES 43 53 + #define NSSNOC_HAQ_AXI_ARES 44 54 + #define CE_APB_ARES 45 55 + #define CE_AXI_ARES 46 56 + #define NSSNOC_CE_APB_ARES 47 57 + #define NSSNOC_CE_AXI_ARES 48 58 + #define CRYPTO_ARES 49 59 + #define NSSNOC_CRYPTO_ARES 50 60 + #define NSSNOC_NC_AXI0_1_ARES 51 61 + #define UBI0_CORE_ARES 52 62 + #define UBI1_CORE_ARES 53 63 + #define UBI2_CORE_ARES 54 64 + #define UBI3_CORE_ARES 55 65 + #define NC_AXI0_ARES 56 66 + #define UTCM0_ARES 57 67 + #define NC_AXI1_ARES 58 68 + #define UTCM1_ARES 59 69 + #define NC_AXI2_ARES 60 70 + #define UTCM2_ARES 61 71 + #define NC_AXI3_ARES 62 72 + #define UTCM3_ARES 63 73 + #define NSSNOC_NC_AXI0_ARES 64 74 + #define AHB0_ARES 65 75 + #define INTR0_AHB_ARES 66 76 + #define AHB1_ARES 67 77 + #define INTR1_AHB_ARES 68 78 + #define AHB2_ARES 69 79 + #define INTR2_AHB_ARES 70 80 + #define AHB3_ARES 71 81 + #define INTR3_AHB_ARES 72 82 + #define NSSNOC_AHB0_ARES 73 83 + #define NSSNOC_INT0_AHB_ARES 74 84 + #define AXI0_ARES 75 85 + #define AXI1_ARES 76 86 + #define AXI2_ARES 77 87 + #define AXI3_ARES 78 88 + #define NSSNOC_AXI0_ARES 79 89 + #define IMEM_QSB_ARES 80 90 + #define NSSNOC_IMEM_QSB_ARES 81 91 + #define IMEM_AHB_ARES 82 92 + #define NSSNOC_IMEM_AHB_ARES 83 93 + #define UNIPHY_PORT1_RX_ARES 84 94 + #define UNIPHY_PORT1_TX_ARES 85 95 + #define UNIPHY_PORT2_RX_ARES 86 96 + #define UNIPHY_PORT2_TX_ARES 87 97 + #define UNIPHY_PORT3_RX_ARES 88 98 + #define UNIPHY_PORT3_TX_ARES 89 99 + #define UNIPHY_PORT4_RX_ARES 90 100 + #define UNIPHY_PORT4_TX_ARES 91 101 + #define UNIPHY_PORT5_RX_ARES 92 102 + #define UNIPHY_PORT5_TX_ARES 93 103 + #define UNIPHY_PORT6_RX_ARES 94 104 + #define UNIPHY_PORT6_TX_ARES 95 105 + #define PORT1_RX_ARES 96 106 + #define PORT1_TX_ARES 97 107 + #define PORT2_RX_ARES 98 108 + #define PORT2_TX_ARES 99 109 + #define PORT3_RX_ARES 100 110 + #define PORT3_TX_ARES 101 111 + #define PORT4_RX_ARES 102 112 + #define PORT4_TX_ARES 103 113 + #define PORT5_RX_ARES 104 114 + #define PORT5_TX_ARES 105 115 + #define PORT6_RX_ARES 106 116 + #define PORT6_TX_ARES 107 117 + #define PPE_FULL_RESET 108 118 + #define UNIPHY0_SOFT_RESET 109 119 + #define UNIPHY1_SOFT_RESET 110 120 + #define UNIPHY2_SOFT_RESET 111 121 + #define UNIPHY_PORT1_ARES 112 122 + #define UNIPHY_PORT2_ARES 113 123 + #define UNIPHY_PORT3_ARES 114 124 + #define UNIPHY_PORT4_ARES 115 125 + #define UNIPHY_PORT5_ARES 116 126 + #define UNIPHY_PORT6_ARES 117 127 + #define NSSPORT1_RESET 118 128 + #define NSSPORT2_RESET 119 129 + #define NSSPORT3_RESET 120 130 + #define NSSPORT4_RESET 121 131 + #define NSSPORT5_RESET 122 132 + #define NSSPORT6_RESET 123 133 + 134 + #endif