tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu: support nbio_7_2_1 for yellow carp

This patch adds nbio_7_2_1 support yellow carp.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Aaron Liu and committed by
Alex Deucher 011b514f bf9d4e88

+103 -37
+103 -37
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
··· 28 28 #include "nbio/nbio_7_2_0_sh_mask.h" 29 29 #include <uapi/linux/kfd_ioctl.h> 30 30 31 + #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015 32 + #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2 33 + #define regBIF_BX0_BIF_FB_EN_YC 0x0100 34 + #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2 35 + #define regBIF1_PCIE_MST_CTRL_3 0x4601c6 36 + #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5 37 + #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \ 38 + 0x1b 39 + #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \ 40 + 0x1c 41 + #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \ 42 + 0x08000000L 43 + #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \ 44 + 0x30000000L 45 + #define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187 46 + #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5 47 + #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L 48 + #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L 49 + 31 50 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) 32 51 { 33 52 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, ··· 57 38 58 39 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) 59 40 { 60 - u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 41 + u32 tmp; 42 + 43 + if (adev->asic_type == CHIP_YELLOW_CARP) 44 + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC); 45 + else 46 + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 61 47 62 48 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 63 49 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; ··· 73 49 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) 74 50 { 75 51 if (enable) 76 - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 77 - BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 78 - BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 52 + if (adev->asic_type == CHIP_YELLOW_CARP) 53 + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 54 + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 55 + BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 56 + else 57 + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 58 + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 59 + BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 79 60 else 80 - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 61 + if (adev->asic_type == CHIP_YELLOW_CARP) 62 + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0); 63 + else 64 + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 81 65 } 82 66 83 67 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev) ··· 124 92 125 93 if (use_doorbell) { 126 94 doorbell_range = REG_SET_FIELD(doorbell_range, 127 - GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, 128 - doorbell_index); 95 + GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, 96 + doorbell_index); 129 97 doorbell_range = REG_SET_FIELD(doorbell_range, 130 - GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); 98 + GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); 131 99 } else { 132 100 doorbell_range = REG_SET_FIELD(doorbell_range, 133 - GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); 101 + GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); 134 102 } 135 103 136 104 WREG32_PCIE_PORT(reg, doorbell_range); ··· 155 123 156 124 if (enable) { 157 125 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 158 - DOORBELL_SELFRING_GPA_APER_EN, 1) | 159 - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 160 - DOORBELL_SELFRING_GPA_APER_MODE, 1) | 161 - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 162 - DOORBELL_SELFRING_GPA_APER_SIZE, 0); 126 + DOORBELL_SELFRING_GPA_APER_EN, 1) | 127 + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 128 + DOORBELL_SELFRING_GPA_APER_MODE, 1) | 129 + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 130 + DOORBELL_SELFRING_GPA_APER_SIZE, 0); 163 131 164 132 WREG32_SOC15(NBIO, 0, 165 - regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 166 - lower_32_bits(adev->doorbell.base)); 133 + regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 134 + lower_32_bits(adev->doorbell.base)); 167 135 WREG32_SOC15(NBIO, 0, 168 - regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 169 - upper_32_bits(adev->doorbell.base)); 136 + regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 137 + upper_32_bits(adev->doorbell.base)); 170 138 } 171 139 172 140 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 173 - tmp); 141 + tmp); 174 142 } 175 143 176 144 ··· 250 218 { 251 219 uint32_t def, data; 252 220 253 - def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 254 - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 255 - data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 256 - PCIE_CNTL2__MST_MEM_LS_EN_MASK | 257 - PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 258 - } else { 259 - data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 260 - PCIE_CNTL2__MST_MEM_LS_EN_MASK | 261 - PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 262 - } 221 + if (adev->asic_type == CHIP_YELLOW_CARP) { 222 + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 223 + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 224 + data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 225 + else 226 + data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 263 227 264 - if (def != data) 265 - WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 228 + if (def != data) 229 + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 230 + 231 + data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1)); 232 + def = data; 233 + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 234 + data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 235 + BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 236 + else 237 + data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 238 + BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 239 + 240 + if (def != data) 241 + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), 242 + data); 243 + } else { 244 + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 245 + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 246 + data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 247 + PCIE_CNTL2__MST_MEM_LS_EN_MASK | 248 + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 249 + else 250 + data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 251 + PCIE_CNTL2__MST_MEM_LS_EN_MASK | 252 + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 253 + 254 + if (def != data) 255 + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 256 + } 266 257 } 267 258 268 259 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, ··· 352 297 static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 353 298 { 354 299 uint32_t def, data; 300 + if (adev->asic_type == CHIP_YELLOW_CARP) { 301 + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3)); 302 + data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 303 + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 304 + data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 305 + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 355 306 356 - def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); 357 - data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 358 - data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 307 + if (def != data) 308 + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data); 309 + } else { 310 + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); 311 + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 312 + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 313 + data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 314 + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 359 315 360 - if (def != data) 361 - WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), 362 - data); 316 + if (def != data) 317 + WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data); 318 + } 363 319 } 364 320 365 321 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {