tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Staging: bcm: Macros: Fixed multiple coding style violations.

Fixed multiple indentation issues.

Signed-off-by: Benjamin James Wright <bwright.au@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

authored by

Ben Wright and committed by
Greg Kroah-Hartman 01188858 e5969d55

+156 -159
+156 -159
drivers/staging/bcm/Macros.h
··· 1 1 /************************************* 2 - * Macros.h 2 + * Macros.h 3 3 **************************************/ 4 - #ifndef __MACROS_H__ 4 + #ifndef __MACROS_H__ 5 5 #define __MACROS_H__ 6 6 7 - #define TX_TIMER_PERIOD 10 //10 msec 7 + #define TX_TIMER_PERIOD 10 /*10 msec*/ 8 8 #define MAX_CLASSIFIERS 100 9 - //#define MAX_CLASSIFIERS_PER_SF 20 9 + /* #define MAX_CLASSIFIERS_PER_SF 20 */ 10 10 #define MAX_TARGET_DSX_BUFFERS 24 11 11 12 - #define MAX_CNTRL_PKTS 100 13 - #define MAX_DATA_PKTS 200 14 - #define MAX_ETH_SIZE 1536 12 + #define MAX_CNTRL_PKTS 100 13 + #define MAX_DATA_PKTS 200 14 + #define MAX_ETH_SIZE 1536 15 15 #define MAX_CNTL_PKT_SIZE 2048 16 16 17 17 #define MTU_SIZE 1400 ··· 20 20 #define MAC_ADDR_REGISTER 0xbf60d000 21 21 22 22 23 - ///////////Quality of Service/////////////////////////// 24 - #define NO_OF_QUEUES 17 25 - #define HiPriority NO_OF_QUEUES-1 26 - #define LowPriority 0 27 - #define BE 2 28 - #define rtPS 4 29 - #define ERTPS 5 30 - #define UGS 6 23 + /* Quality of Service */ 24 + #define NO_OF_QUEUES 17 25 + #define HiPriority (NO_OF_QUEUES-1) 26 + #define LowPriority 0 27 + #define BE 2 28 + #define rtPS 4 29 + #define ERTPS 5 30 + #define UGS 6 31 31 32 - #define BE_BUCKET_SIZE 1024*1024*100 //32kb 33 - #define rtPS_BUCKET_SIZE 1024*1024*100 //8kb 34 - #define MAX_ALLOWED_RATE 1024*1024*100 35 - #define TX_PACKET_THRESHOLD 10 36 - #define XSECONDS 1*HZ 37 - #define DSC_ACTIVATE_REQUEST 248 38 - #define QUEUE_DEPTH_OFFSET 0x1fc01000 39 - #define MAX_DEVICE_DESC_SIZE 2040 40 - #define MAX_CTRL_QUEUE_LEN 100 41 - #define MAX_APP_QUEUE_LEN 200 42 - #define MAX_LATENCY_ALLOWED 0xFFFFFFFF 43 - #define DEFAULT_UG_INTERVAL 250 44 - #define DEFAULT_UGI_FACTOR 4 32 + #define BE_BUCKET_SIZE (1024*1024*100) /* 32kb */ 33 + #define rtPS_BUCKET_SIZE (1024*1024*100) /* 8kb */ 34 + #define MAX_ALLOWED_RATE (1024*1024*100) 35 + #define TX_PACKET_THRESHOLD 10 36 + #define XSECONDS (1*HZ) 37 + #define DSC_ACTIVATE_REQUEST 248 38 + #define QUEUE_DEPTH_OFFSET 0x1fc01000 39 + #define MAX_DEVICE_DESC_SIZE 2040 40 + #define MAX_CTRL_QUEUE_LEN 100 41 + #define MAX_APP_QUEUE_LEN 200 42 + #define MAX_LATENCY_ALLOWED 0xFFFFFFFF 43 + #define DEFAULT_UG_INTERVAL 250 44 + #define DEFAULT_UGI_FACTOR 4 45 45 46 - #define DEFAULT_PERSFCOUNT 60 47 - #define MAX_CONNECTIONS 10 48 - #define MAX_CLASS_NAME_LENGTH 32 46 + #define DEFAULT_PERSFCOUNT 60 47 + #define MAX_CONNECTIONS 10 48 + #define MAX_CLASS_NAME_LENGTH 32 49 49 50 - #define ETH_LENGTH_OF_ADDRESS 6 51 - #define MAX_MULTICAST_ADDRESSES 32 52 - #define IP_LENGTH_OF_ADDRESS 4 50 + #define ETH_LENGTH_OF_ADDRESS 6 51 + #define MAX_MULTICAST_ADDRESSES 32 52 + #define IP_LENGTH_OF_ADDRESS 4 53 53 54 - #define IP_PACKET_ONLY_MODE 0 55 - #define ETH_PACKET_TUNNELING_MODE 1 54 + #define IP_PACKET_ONLY_MODE 0 55 + #define ETH_PACKET_TUNNELING_MODE 1 56 56 57 - ////////////Link Request////////////// 58 - #define SET_MAC_ADDRESS_REQUEST 0 59 - #define SYNC_UP_REQUEST 1 60 - #define SYNCED_UP 2 61 - #define LINK_UP_REQUEST 3 62 - #define LINK_CONNECTED 4 63 - #define SYNC_UP_NOTIFICATION 2 64 - #define LINK_UP_NOTIFICATION 4 57 + /* Link Request */ 58 + #define SET_MAC_ADDRESS_REQUEST 0 59 + #define SYNC_UP_REQUEST 1 60 + #define SYNCED_UP 2 61 + #define LINK_UP_REQUEST 3 62 + #define LINK_CONNECTED 4 63 + #define SYNC_UP_NOTIFICATION 2 64 + #define LINK_UP_NOTIFICATION 4 65 65 66 66 67 67 #define LINK_NET_ENTRY 0x0002 68 - #define HMC_STATUS 0x0004 68 + #define HMC_STATUS 0x0004 69 69 #define LINK_UP_CONTROL_REQ 0x83 70 70 71 71 #define STATS_POINTER_REQ_STATUS 0x86 72 72 #define NETWORK_ENTRY_REQ_PAYLOAD 198 73 - #define LINK_DOWN_REQ_PAYLOAD 226 73 + #define LINK_DOWN_REQ_PAYLOAD 226 74 74 #define SYNC_UP_REQ_PAYLOAD 228 75 - #define STATISTICS_POINTER_REQ 237 75 + #define STATISTICS_POINTER_REQ 237 76 76 #define LINK_UP_REQ_PAYLOAD 245 77 77 #define LINK_UP_ACK 246 78 78 79 79 #define STATS_MSG_SIZE 4 80 80 #define INDEX_TO_DATA 4 81 81 82 - #define GO_TO_IDLE_MODE_PAYLOAD 210 83 - #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 84 - #define IDLE_MODE_SF_UPDATE_MSG 187 82 + #define GO_TO_IDLE_MODE_PAYLOAD 210 83 + #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 84 + #define IDLE_MODE_SF_UPDATE_MSG 187 85 85 86 - #define SKB_RESERVE_ETHERNET_HEADER 16 87 - #define SKB_RESERVE_PHS_BYTES 32 86 + #define SKB_RESERVE_ETHERNET_HEADER 16 87 + #define SKB_RESERVE_PHS_BYTES 32 88 88 89 - #define IP_PACKET_ONLY_MODE 0 90 - #define ETH_PACKET_TUNNELING_MODE 1 89 + #define IP_PACKET_ONLY_MODE 0 90 + #define ETH_PACKET_TUNNELING_MODE 1 91 91 92 - #define ETH_CS_802_3 1 93 - #define ETH_CS_802_1Q_VLAN 3 94 - #define IPV4_CS 1 95 - #define IPV6_CS 2 96 - #define ETH_CS_MASK 0x3f 92 + #define ETH_CS_802_3 1 93 + #define ETH_CS_802_1Q_VLAN 3 94 + #define IPV4_CS 1 95 + #define IPV6_CS 2 96 + #define ETH_CS_MASK 0x3f 97 97 98 98 /** \brief Validity bit maps for TLVs in packet classification rule */ 99 99 100 - #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 101 - #define PKT_CLASSIFICATION_VLANID_VALID 1 100 + #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 101 + #define PKT_CLASSIFICATION_VLANID_VALID 1 102 102 103 103 #ifndef MIN 104 - #define MIN(_a, _b) ((_a) < (_b)? (_a): (_b)) 104 + #define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b)) 105 105 #endif 106 106 107 107 108 108 /*Leader related terms */ 109 - #define LEADER_STATUS 0x00 110 - #define LEADER_STATUS_TCP_ACK 0x1 111 - #define LEADER_SIZE sizeof(LEADER) 112 - #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) 113 - #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) 114 - #define CM_REQUEST_SIZE LEADER_SIZE + sizeof(stLocalSFChangeRequest) 115 - #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) 109 + #define LEADER_STATUS 0x00 110 + #define LEADER_STATUS_TCP_ACK 0x1 111 + #define LEADER_SIZE sizeof(LEADER) 112 + #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) 113 + #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) 114 + #define CM_REQUEST_SIZE (LEADER_SIZE + sizeof(stLocalSFChangeRequest)) 115 + #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) 116 116 117 117 118 - #define MAX_TRANSFER_CTRL_BYTE_USB 2 * 1024 118 + #define MAX_TRANSFER_CTRL_BYTE_USB (2*1024) 119 119 120 120 #define GET_MAILBOX1_REG_REQUEST 0x87 121 121 #define GET_MAILBOX1_REG_RESPONSE 0x67 ··· 124 124 #define TRANSMIT_NETWORK_DATA 0x00 125 125 #define RECEIVED_NETWORK_DATA 0x20 126 126 127 - #define CM_RESPONSES 0xA0 128 - #define STATUS_RSP 0xA1 129 - #define LINK_CONTROL_RESP 0xA2 130 - #define IDLE_MODE_STATUS 0xA3 131 - #define STATS_POINTER_RESP 0xA6 132 - #define MGMT_MSG_INFO_SW_STATUS 0xA7 133 - #define AUTH_SS_HOST_MSG 0xA8 127 + #define CM_RESPONSES 0xA0 128 + #define STATUS_RSP 0xA1 129 + #define LINK_CONTROL_RESP 0xA2 130 + #define IDLE_MODE_STATUS 0xA3 131 + #define STATS_POINTER_RESP 0xA6 132 + #define MGMT_MSG_INFO_SW_STATUS 0xA7 133 + #define AUTH_SS_HOST_MSG 0xA8 134 134 135 - #define CM_DSA_ACK_PAYLOAD 247 136 - #define CM_DSC_ACK_PAYLOAD 248 137 - #define CM_DSD_ACK_PAYLOAD 249 138 - #define CM_DSDEACTVATE 250 139 - #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 135 + #define CM_DSA_ACK_PAYLOAD 247 136 + #define CM_DSC_ACK_PAYLOAD 248 137 + #define CM_DSD_ACK_PAYLOAD 249 138 + #define CM_DSDEACTVATE 250 139 + #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 140 140 141 - #define MAC_REQ 0 142 - #define LINK_RESP 1 143 - #define RSSI_INDICATION 2 141 + #define MAC_REQ 0 142 + #define LINK_RESP 1 143 + #define RSSI_INDICATION 2 144 144 145 - #define SS_INFO 4 146 - #define STATISTICS_INFO 5 147 - #define CM_INDICATION 6 148 - #define PARAM_RESP 7 149 - #define BUFFER_1K 1024 150 - #define BUFFER_2K BUFFER_1K*2 151 - #define BUFFER_4K BUFFER_2K*2 152 - #define BUFFER_8K BUFFER_4K*2 153 - #define BUFFER_16K BUFFER_8K*2 154 - #define DOWNLINK_DIR 0 155 - #define UPLINK_DIR 1 145 + #define SS_INFO 4 146 + #define STATISTICS_INFO 5 147 + #define CM_INDICATION 6 148 + #define PARAM_RESP 7 149 + #define BUFFER_1K 1024 150 + #define BUFFER_2K (BUFFER_1K*2) 151 + #define BUFFER_4K (BUFFER_2K*2) 152 + #define BUFFER_8K (BUFFER_4K*2) 153 + #define BUFFER_16K (BUFFER_8K*2) 154 + #define DOWNLINK_DIR 0 155 + #define UPLINK_DIR 1 156 156 157 - #define BCM_SIGNATURE "BECEEM" 157 + #define BCM_SIGNATURE "BECEEM" 158 158 159 159 160 - #define GPIO_OUTPUT_REGISTER 0x0F00003C 160 + #define GPIO_OUTPUT_REGISTER 0x0F00003C 161 161 #define BCM_GPIO_OUTPUT_SET_REG 0x0F000040 162 162 #define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044 163 163 #define GPIO_MODE_REGISTER 0x0F000034 ··· 165 165 166 166 167 167 typedef struct _LINK_STATE { 168 - UCHAR ucLinkStatus; 169 - UCHAR bIdleMode; 170 - UCHAR bShutdownMode; 171 - }LINK_STATE, *PLINK_STATE; 168 + UCHAR ucLinkStatus; 169 + UCHAR bIdleMode; 170 + UCHAR bShutdownMode; 171 + } LINK_STATE, *PLINK_STATE; 172 172 173 173 174 174 enum enLinkStatus { 175 - WAIT_FOR_SYNC = 1, 176 - PHY_SYNC_ACHIVED = 2, 177 - LINKUP_IN_PROGRESS = 3, 178 - LINKUP_DONE = 4, 179 - DREG_RECEIVED = 5, 180 - LINK_STATUS_RESET_RECEIVED = 6, 181 - PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, 182 - LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, 183 - COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW =9 175 + WAIT_FOR_SYNC = 1, 176 + PHY_SYNC_ACHIVED = 2, 177 + LINKUP_IN_PROGRESS = 3, 178 + LINKUP_DONE = 4, 179 + DREG_RECEIVED = 5, 180 + LINK_STATUS_RESET_RECEIVED = 6, 181 + PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, 182 + LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, 183 + COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW = 9 184 184 }; 185 185 186 - typedef enum _E_PHS_DSC_ACTION 187 - { 188 - eAddPHSRule=0, 186 + typedef enum _E_PHS_DSC_ACTION { 187 + eAddPHSRule = 0, 189 188 eSetPHSRule, 190 189 eDeletePHSRule, 191 190 eDeleteAllPHSRules 192 - }E_PHS_DSC_ACTION; 191 + } E_PHS_DSC_ACTION; 193 192 194 193 195 - #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 // Host to Mac 196 - #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 // Mac to Host 197 - #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 //0b000010000 198 - #define MINIMUM_PENDING_DESCRIPTORS 5 194 + #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 /* Host to Mac */ 195 + #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 /* Mac to Host */ 196 + #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 /* 0b000010000 */ 197 + #define MINIMUM_PENDING_DESCRIPTORS 5 199 198 200 199 #define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC 201 200 #define SHUTDOWN_ACK_FROM_DRIVER 0x1 202 201 #define SHUTDOWN_NACK_FROM_DRIVER 0x2 203 202 204 - #define LINK_SYNC_UP_SUBTYPE 0x0001 205 - #define LINK_SYNC_DOWN_SUBTYPE 0x0001 203 + #define LINK_SYNC_UP_SUBTYPE 0x0001 204 + #define LINK_SYNC_DOWN_SUBTYPE 0x0001 206 205 207 206 208 207 ··· 225 226 226 227 #define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10) 227 228 228 - #define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN) 229 + #define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN) 229 230 #define AUTO_LINKUP_ENABLE 0x2 230 - #define AUTO_SYNC_DISABLE 0x1 231 + #define AUTO_SYNC_DISABLE 0x1 231 232 #define AUTO_FIRM_DOWNLOAD 0x1 232 233 #define SETTLE_DOWN_TIME 50 233 234 ··· 241 242 #define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3 242 243 #define IDLE_MODE_PAYLOAD_LENGTH 8 243 244 244 - #define IP_HEADER(Buffer) ((IPHeaderFormat*)(Buffer)) 245 - #define IPV4 4 246 - #define IP_VERSION(byte) (((byte&0xF0)>>4)) 245 + #define IP_HEADER(Buffer) ((IPHeaderFormat *)(Buffer)) 246 + #define IPV4 4 247 + #define IP_VERSION(byte) (((byte&0xF0)>>4)) 247 248 248 249 #define SET_MAC_ADDRESS 193 249 250 #define SET_MAC_ADDRESS_RESPONSE 236 ··· 262 263 263 264 #define INVALID_QUEUE_INDEX NO_OF_QUEUES 264 265 265 - #define INVALID_PID (pid_t)-1 266 - #define DDR_80_MHZ 0 267 - #define DDR_100_MHZ 1 268 - #define DDR_120_MHZ 2 // Additional Frequency for T3LP 269 - #define DDR_133_MHZ 3 270 - #define DDR_140_MHZ 4 // Not Used (Reserved for future) 271 - #define DDR_160_MHZ 5 // Additional Frequency for T3LP 272 - #define DDR_180_MHZ 6 // Not Used (Reserved for future) 273 - #define DDR_200_MHZ 7 // Not Used (Reserved for future) 266 + #define INVALID_PID ((pid_t)-1) 267 + #define DDR_80_MHZ 0 268 + #define DDR_100_MHZ 1 269 + #define DDR_120_MHZ 2 /* Additional Frequency for T3LP */ 270 + #define DDR_133_MHZ 3 271 + #define DDR_140_MHZ 4 /* Not Used (Reserved for future) */ 272 + #define DDR_160_MHZ 5 /* Additional Frequency for T3LP */ 273 + #define DDR_180_MHZ 6 /* Not Used (Reserved for future) */ 274 + #define DDR_200_MHZ 7 /* Not Used (Reserved for future) */ 274 275 275 276 #define MIPS_200_MHZ 0 276 277 #define MIPS_160_MHZ 1 ··· 290 291 #define EEPROM_REJECT_REG_3 0x0f003008 291 292 #define EEPROM_REJECT_REG_4 0x0f003020 292 293 #define EEPROM_REJECT_MASK 0x0fffffff 293 - #define VSG_MODE 0x3 294 + #define VSG_MODE 0x3 294 295 295 296 /* Idle Mode Related Registers */ 296 297 #define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C 297 - #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC 298 + #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC 298 299 299 - #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e 300 - #define DEVICE_INT_OUT_EP_REG0 0x0F011870 301 - #define DEVICE_INT_OUT_EP_REG1 0x0F011874 300 + #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e 301 + #define DEVICE_INT_OUT_EP_REG0 0x0F011870 302 + #define DEVICE_INT_OUT_EP_REG1 0x0F011874 302 303 303 304 #define BIN_FILE "/lib/firmware/macxvi200.bin" 304 305 #define CFG_FILE "/lib/firmware/macxvi.cfg" 305 306 #define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128 306 - #define MIN_VAL(x,y) ((x)<(y)?(x):(y)) 307 + #define MIN_VAL(x, y) ((x) < (y) ? (x) : (y)) 307 308 #define MAC_ADDRESS_SIZE 6 308 309 #define EEPROM_COMMAND_Q_REG 0x0F003018 309 310 #define EEPROM_READ_DATA_Q_REG 0x0F003020 310 - #define CHIP_ID_REG 0x0F000000 311 - #define GPIO_MODE_REG 0x0F000034 312 - #define GPIO_OUTPUT_REG 0x0F00003C 313 - #define WIMAX_MAX_ALLOWED_RATE 1024*1024*50 311 + #define CHIP_ID_REG 0x0F000000 312 + #define GPIO_MODE_REG 0x0F000034 313 + #define GPIO_OUTPUT_REG 0x0F00003C 314 + #define WIMAX_MAX_ALLOWED_RATE (1024*1024*50) 314 315 315 316 #define T3 0xbece0300 316 317 #define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400 ··· 318 319 #define RWM_READ 0 319 320 #define RWM_WRITE 1 320 321 321 - #define T3LPB 0xbece3300 322 - #define BCS220_2 0xbece3311 323 - #define BCS220_2BC 0xBECE3310 324 - #define BCS250_BC 0xbece3301 325 - #define BCS220_3 0xbece3321 322 + #define T3LPB 0xbece3300 323 + #define BCS220_2 0xbece3311 324 + #define BCS220_2BC 0xBECE3310 325 + #define BCS250_BC 0xbece3301 326 + #define BCS220_3 0xbece3321 326 327 327 328 328 - #define HPM_CONFIG_LDO145 0x0F000D54 329 - #define HPM_CONFIG_MSW 0x0F000D58 329 + #define HPM_CONFIG_LDO145 0x0F000D54 330 + #define HPM_CONFIG_MSW 0x0F000D58 330 331 331 332 #define T3B 0xbece0310 332 - typedef enum eNVM_TYPE 333 - { 333 + typedef enum eNVM_TYPE { 334 334 NVM_AUTODETECT = 0, 335 335 NVM_EEPROM, 336 336 NVM_FLASH, 337 337 NVM_UNKNOWN 338 - }NVM_TYPE; 338 + } NVM_TYPE; 339 339 340 - typedef enum ePMU_MODES 341 - { 340 + typedef enum ePMU_MODES { 342 341 HYBRID_MODE_7C = 0, 343 342 INTERNAL_MODE_6 = 1, 344 343 HYBRID_MODE_6 = 2 345 - }PMU_MODE; 344 + } PMU_MODE; 346 345 347 346 #define MAX_RDM_WRM_RETIRES 1 348 347 ··· 357 360 #define SKB_CB_LATENCY_OFFSET 1 358 361 #define SKB_CB_TCPACK_OFFSET 2 359 362 360 - #endif //__MACROS_H__ 363 + #endif /* __MACROS_H__ */