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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
irqchip/aspeed-intc: Add AST27XX INTC support
Support Aspeed Interrupt Controller on Aspeed Silicon SoCs.
ASPEED interrupt controller(INTC) maps the internal interrupt
sources to a parent interrupt controller, which can be GIC or INTC.
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20241016022410.1154574-3-kevin_chen@aspeedtech.com
authored by
Kevin Chen
and committed by
Thomas Gleixner
010863f4
37a99ff5
+140
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
···
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obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-intc.o
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obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
+139
drivers/irqchip/irq-aspeed-intc.c
+139
drivers/irqchip/irq-aspeed-intc.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Aspeed Interrupt Controller.
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*
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* Copyright (C) 2023 ASPEED Technology Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#define INTC_INT_ENABLE_REG 0x00
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#define INTC_INT_STATUS_REG 0x04
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#define INTC_IRQS_PER_WORD 32
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struct aspeed_intc_ic {
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void __iomem *base;
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raw_spinlock_t gic_lock;
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raw_spinlock_t intc_lock;
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struct irq_domain *irq_domain;
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};
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static void aspeed_intc_ic_irq_handler(struct irq_desc *desc)
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{
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struct aspeed_intc_ic *intc_ic = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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scoped_guard(raw_spinlock, &intc_ic->gic_lock) {
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unsigned long bit, status;
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status = readl(intc_ic->base + INTC_INT_STATUS_REG);
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for_each_set_bit(bit, &status, INTC_IRQS_PER_WORD) {
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generic_handle_domain_irq(intc_ic->irq_domain, bit);
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writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static void aspeed_intc_irq_mask(struct irq_data *data)
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{
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struct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);
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unsigned int mask = readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(data->hwirq);
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guard(raw_spinlock)(&intc_ic->intc_lock);
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writel(mask, intc_ic->base + INTC_INT_ENABLE_REG);
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}
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static void aspeed_intc_irq_unmask(struct irq_data *data)
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{
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struct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);
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unsigned int unmask = readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(data->hwirq);
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guard(raw_spinlock)(&intc_ic->intc_lock);
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writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG);
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}
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static struct irq_chip aspeed_intc_chip = {
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.name = "ASPEED INTC",
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.irq_mask = aspeed_intc_irq_mask,
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.irq_unmask = aspeed_intc_irq_unmask,
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};
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static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops = {
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.map = aspeed_intc_ic_map_irq_domain,
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};
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static int __init aspeed_intc_ic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct aspeed_intc_ic *intc_ic;
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int irq, i, ret = 0;
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intc_ic = kzalloc(sizeof(*intc_ic), GFP_KERNEL);
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if (!intc_ic)
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return -ENOMEM;
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intc_ic->base = of_iomap(node, 0);
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if (!intc_ic->base) {
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pr_err("Failed to iomap intc_ic base\n");
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ret = -ENOMEM;
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goto err_free_ic;
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}
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writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG);
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writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG);
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intc_ic->irq_domain = irq_domain_add_linear(node, INTC_IRQS_PER_WORD,
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&aspeed_intc_ic_irq_domain_ops, intc_ic);
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if (!intc_ic->irq_domain) {
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ret = -ENOMEM;
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goto err_iounmap;
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}
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raw_spin_lock_init(&intc_ic->gic_lock);
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raw_spin_lock_init(&intc_ic->intc_lock);
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/* Check all the irq numbers valid. If not, unmaps all the base and frees the data. */
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for (i = 0; i < of_irq_count(node); i++) {
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irq = irq_of_parse_and_map(node, i);
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if (!irq) {
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pr_err("Failed to get irq number\n");
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ret = -EINVAL;
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goto err_iounmap;
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}
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}
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for (i = 0; i < of_irq_count(node); i++) {
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irq = irq_of_parse_and_map(node, i);
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irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_ic);
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}
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return 0;
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err_iounmap:
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iounmap(intc_ic->base);
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err_free_ic:
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kfree(intc_ic);
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return ret;
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}
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IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_of_init);