tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parents

Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data instead of hardcoding a number that relies on an array
defined hundreds of lines above.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marijn Suijten and committed by
Stephen Boyd 00ff8188 6880fa6c

+40 -40
+40 -40
drivers/clk/qcom/gcc-sdm660.c
··· 284 284 .clkr.hw.init = &(struct clk_init_data){ 285 285 .name = "blsp1_qup1_i2c_apps_clk_src", 286 286 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 287 - .num_parents = 3, 287 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 288 288 .ops = &clk_rcg2_ops, 289 289 }, 290 290 }; ··· 309 309 .clkr.hw.init = &(struct clk_init_data){ 310 310 .name = "blsp1_qup1_spi_apps_clk_src", 311 311 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 312 - .num_parents = 3, 312 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 313 313 .ops = &clk_rcg2_ops, 314 314 }, 315 315 }; ··· 323 323 .clkr.hw.init = &(struct clk_init_data){ 324 324 .name = "blsp1_qup2_i2c_apps_clk_src", 325 325 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 326 - .num_parents = 3, 326 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 327 327 .ops = &clk_rcg2_ops, 328 328 }, 329 329 }; ··· 337 337 .clkr.hw.init = &(struct clk_init_data){ 338 338 .name = "blsp1_qup2_spi_apps_clk_src", 339 339 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 340 - .num_parents = 3, 340 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 341 341 .ops = &clk_rcg2_ops, 342 342 }, 343 343 }; ··· 351 351 .clkr.hw.init = &(struct clk_init_data){ 352 352 .name = "blsp1_qup3_i2c_apps_clk_src", 353 353 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 354 - .num_parents = 3, 354 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 355 355 .ops = &clk_rcg2_ops, 356 356 }, 357 357 }; ··· 365 365 .clkr.hw.init = &(struct clk_init_data){ 366 366 .name = "blsp1_qup3_spi_apps_clk_src", 367 367 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 368 - .num_parents = 3, 368 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 369 369 .ops = &clk_rcg2_ops, 370 370 }, 371 371 }; ··· 379 379 .clkr.hw.init = &(struct clk_init_data){ 380 380 .name = "blsp1_qup4_i2c_apps_clk_src", 381 381 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 382 - .num_parents = 3, 382 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 383 383 .ops = &clk_rcg2_ops, 384 384 }, 385 385 }; ··· 393 393 .clkr.hw.init = &(struct clk_init_data){ 394 394 .name = "blsp1_qup4_spi_apps_clk_src", 395 395 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 396 - .num_parents = 3, 396 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 397 397 .ops = &clk_rcg2_ops, 398 398 }, 399 399 }; ··· 426 426 .clkr.hw.init = &(struct clk_init_data){ 427 427 .name = "blsp1_uart1_apps_clk_src", 428 428 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 429 - .num_parents = 3, 429 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 430 430 .ops = &clk_rcg2_ops, 431 431 }, 432 432 }; ··· 440 440 .clkr.hw.init = &(struct clk_init_data){ 441 441 .name = "blsp1_uart2_apps_clk_src", 442 442 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 443 - .num_parents = 3, 443 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 444 444 .ops = &clk_rcg2_ops, 445 445 }, 446 446 }; ··· 454 454 .clkr.hw.init = &(struct clk_init_data){ 455 455 .name = "blsp2_qup1_i2c_apps_clk_src", 456 456 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 457 - .num_parents = 3, 457 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 458 458 .ops = &clk_rcg2_ops, 459 459 }, 460 460 }; ··· 468 468 .clkr.hw.init = &(struct clk_init_data){ 469 469 .name = "blsp2_qup1_spi_apps_clk_src", 470 470 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 471 - .num_parents = 3, 471 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 472 472 .ops = &clk_rcg2_ops, 473 473 }, 474 474 }; ··· 482 482 .clkr.hw.init = &(struct clk_init_data){ 483 483 .name = "blsp2_qup2_i2c_apps_clk_src", 484 484 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 485 - .num_parents = 3, 485 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 486 486 .ops = &clk_rcg2_ops, 487 487 }, 488 488 }; ··· 496 496 .clkr.hw.init = &(struct clk_init_data){ 497 497 .name = "blsp2_qup2_spi_apps_clk_src", 498 498 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 499 - .num_parents = 3, 499 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 500 500 .ops = &clk_rcg2_ops, 501 501 }, 502 502 }; ··· 510 510 .clkr.hw.init = &(struct clk_init_data){ 511 511 .name = "blsp2_qup3_i2c_apps_clk_src", 512 512 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 513 - .num_parents = 3, 513 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 514 514 .ops = &clk_rcg2_ops, 515 515 }, 516 516 }; ··· 524 524 .clkr.hw.init = &(struct clk_init_data){ 525 525 .name = "blsp2_qup3_spi_apps_clk_src", 526 526 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 527 - .num_parents = 3, 527 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 528 528 .ops = &clk_rcg2_ops, 529 529 }, 530 530 }; ··· 538 538 .clkr.hw.init = &(struct clk_init_data){ 539 539 .name = "blsp2_qup4_i2c_apps_clk_src", 540 540 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 541 - .num_parents = 3, 541 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 542 542 .ops = &clk_rcg2_ops, 543 543 }, 544 544 }; ··· 552 552 .clkr.hw.init = &(struct clk_init_data){ 553 553 .name = "blsp2_qup4_spi_apps_clk_src", 554 554 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 555 - .num_parents = 3, 555 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 556 556 .ops = &clk_rcg2_ops, 557 557 }, 558 558 }; ··· 566 566 .clkr.hw.init = &(struct clk_init_data){ 567 567 .name = "blsp2_uart1_apps_clk_src", 568 568 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 569 - .num_parents = 3, 569 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 570 570 .ops = &clk_rcg2_ops, 571 571 }, 572 572 }; ··· 580 580 .clkr.hw.init = &(struct clk_init_data){ 581 581 .name = "blsp2_uart2_apps_clk_src", 582 582 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 583 - .num_parents = 3, 583 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 584 584 .ops = &clk_rcg2_ops, 585 585 }, 586 586 }; ··· 601 601 .clkr.hw.init = &(struct clk_init_data){ 602 602 .name = "gp1_clk_src", 603 603 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 604 - .num_parents = 4, 604 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 605 605 .ops = &clk_rcg2_ops, 606 606 }, 607 607 }; ··· 615 615 .clkr.hw.init = &(struct clk_init_data){ 616 616 .name = "gp2_clk_src", 617 617 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 618 - .num_parents = 4, 618 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 619 619 .ops = &clk_rcg2_ops, 620 620 }, 621 621 }; ··· 629 629 .clkr.hw.init = &(struct clk_init_data){ 630 630 .name = "gp3_clk_src", 631 631 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 632 - .num_parents = 4, 632 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 633 633 .ops = &clk_rcg2_ops, 634 634 }, 635 635 }; ··· 649 649 .clkr.hw.init = &(struct clk_init_data){ 650 650 .name = "hmss_gpll0_clk_src", 651 651 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 652 - .num_parents = 3, 652 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 653 653 .ops = &clk_rcg2_ops, 654 654 }, 655 655 }; ··· 670 670 .clkr.hw.init = &(struct clk_init_data){ 671 671 .name = "hmss_gpll4_clk_src", 672 672 .parent_data = gcc_parent_data_xo_gpll4, 673 - .num_parents = 2, 673 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4), 674 674 .ops = &clk_rcg2_ops, 675 675 }, 676 676 }; ··· 689 689 .clkr.hw.init = &(struct clk_init_data){ 690 690 .name = "hmss_rbcpr_clk_src", 691 691 .parent_data = gcc_parent_data_xo_gpll0, 692 - .num_parents = 2, 692 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0), 693 693 .ops = &clk_rcg2_ops, 694 694 }, 695 695 }; ··· 708 708 .clkr.hw.init = &(struct clk_init_data){ 709 709 .name = "pdm2_clk_src", 710 710 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 711 - .num_parents = 3, 711 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 712 712 .ops = &clk_rcg2_ops, 713 713 }, 714 714 }; ··· 730 730 .clkr.hw.init = &(struct clk_init_data){ 731 731 .name = "qspi_ser_clk_src", 732 732 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, 733 - .num_parents = 6, 733 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div), 734 734 .ops = &clk_rcg2_ops, 735 735 }, 736 736 }; ··· 756 756 .clkr.hw.init = &(struct clk_init_data){ 757 757 .name = "sdcc1_apps_clk_src", 758 758 .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, 759 - .num_parents = 4, 759 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), 760 760 .ops = &clk_rcg2_ops, 761 761 }, 762 762 }; ··· 778 778 .clkr.hw.init = &(struct clk_init_data){ 779 779 .name = "sdcc1_ice_core_clk_src", 780 780 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 781 - .num_parents = 3, 781 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 782 782 .ops = &clk_rcg2_ops, 783 783 }, 784 784 }; ··· 804 804 .clkr.hw.init = &(struct clk_init_data){ 805 805 .name = "sdcc2_apps_clk_src", 806 806 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, 807 - .num_parents = 4, 807 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4), 808 808 .ops = &clk_rcg2_floor_ops, 809 809 }, 810 810 }; ··· 827 827 .clkr.hw.init = &(struct clk_init_data){ 828 828 .name = "ufs_axi_clk_src", 829 829 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 830 - .num_parents = 3, 830 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 831 831 .ops = &clk_rcg2_ops, 832 832 }, 833 833 }; ··· 848 848 .clkr.hw.init = &(struct clk_init_data){ 849 849 .name = "ufs_ice_core_clk_src", 850 850 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 851 - .num_parents = 3, 851 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 852 852 .ops = &clk_rcg2_ops, 853 853 }, 854 854 }; ··· 862 862 .clkr.hw.init = &(struct clk_init_data){ 863 863 .name = "ufs_phy_aux_clk_src", 864 864 .parent_data = gcc_parent_data_xo_sleep_clk, 865 - .num_parents = 2, 865 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), 866 866 .ops = &clk_rcg2_ops, 867 867 }, 868 868 }; ··· 883 883 .clkr.hw.init = &(struct clk_init_data){ 884 884 .name = "ufs_unipro_core_clk_src", 885 885 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 886 - .num_parents = 3, 886 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 887 887 .ops = &clk_rcg2_ops, 888 888 }, 889 889 }; ··· 904 904 .clkr.hw.init = &(struct clk_init_data){ 905 905 .name = "usb20_master_clk_src", 906 906 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 907 - .num_parents = 3, 907 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 908 908 .ops = &clk_rcg2_ops, 909 909 }, 910 910 }; ··· 924 924 .clkr.hw.init = &(struct clk_init_data){ 925 925 .name = "usb20_mock_utmi_clk_src", 926 926 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 927 - .num_parents = 3, 927 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 928 928 .ops = &clk_rcg2_ops, 929 929 }, 930 930 }; ··· 949 949 .clkr.hw.init = &(struct clk_init_data){ 950 950 .name = "usb30_master_clk_src", 951 951 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 952 - .num_parents = 3, 952 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 953 953 .ops = &clk_rcg2_ops, 954 954 }, 955 955 }; ··· 970 970 .clkr.hw.init = &(struct clk_init_data){ 971 971 .name = "usb30_mock_utmi_clk_src", 972 972 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 973 - .num_parents = 3, 973 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 974 974 .ops = &clk_rcg2_ops, 975 975 }, 976 976 }; ··· 990 990 .clkr.hw.init = &(struct clk_init_data){ 991 991 .name = "usb3_phy_aux_clk_src", 992 992 .parent_data = gcc_parent_data_xo_sleep_clk, 993 - .num_parents = 2, 993 + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), 994 994 .ops = &clk_rcg2_ops, 995 995 }, 996 996 };