tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: zynq: Add support for SOC_BUS
Provide information through SOC_BUS to user space.
Silicon revision is provided through devcfg device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+96
-1
+5
arch/arm/boot/dts/zynq-7000.dtsi
+5
arch/arm/boot/dts/zynq-7000.dtsi
+1
arch/arm/mach-zynq/Kconfig
+1
arch/arm/mach-zynq/Kconfig
+70
-1
arch/arm/mach-zynq/common.c
+70
-1
arch/arm/mach-zynq/common.c
···
29
29
#include <linux/memblock.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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+
#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
···
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/smp_scu.h>
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+
#include <asm/system_info.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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+
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#define ZYNQ_DEVCFG_MCTRL 0x80
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#define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28
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#define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
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void __iomem *zynq_scu_base;
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···
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};
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/**
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* zynq_get_revision - Get Zynq silicon revision
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*
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* Return: Silicon version or -1 otherwise
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*/
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static int __init zynq_get_revision(void)
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{
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struct device_node *np;
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void __iomem *zynq_devcfg_base;
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u32 revision;
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+
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np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
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if (!np) {
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pr_err("%s: no devcfg node found\n", __func__);
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return -1;
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}
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zynq_devcfg_base = of_iomap(np, 0);
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if (!zynq_devcfg_base) {
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pr_err("%s: Unable to map I/O memory\n", __func__);
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return -1;
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}
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revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
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revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
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revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
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iounmap(zynq_devcfg_base);
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return revision;
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}
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/**
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* zynq_init_machine - System specific initialization, intended to be
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* called from board specific initialization.
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*/
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static void __init zynq_init_machine(void)
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{
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struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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struct device *parent = NULL;
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/*
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* 64KB way size, 8-way associativity, parity disabled
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*/
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l2x0_of_init(0x02060000, 0xF0F0FFFF);
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-
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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goto out;
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system_rev = zynq_get_revision();
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soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
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soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
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zynq_slcr_get_device_id());
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->family);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr->soc_id);
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kfree(soc_dev_attr);
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goto out;
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}
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parent = soc_device_to_device(soc_dev);
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out:
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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platform_device_register(&zynq_cpuidle_device);
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platform_device_register_full(&devinfo);
+1
arch/arm/mach-zynq/common.h
+1
arch/arm/mach-zynq/common.h
+19
arch/arm/mach-zynq/slcr.c
+19
arch/arm/mach-zynq/slcr.c
···
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
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#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
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#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
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static void __iomem *zynq_slcr_base;
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static struct regmap *zynq_slcr_regmap;
···
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zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
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return 0;
83
+
}
84
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/**
86
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* zynq_slcr_get_device_id - Read device code id
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*
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* Return: Device code id
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*/
90
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u32 zynq_slcr_get_device_id(void)
91
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{
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u32 val;
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zynq_slcr_read(&val, SLCR_PSS_IDCODE);
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val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
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val &= SLCR_PSS_IDCODE_DEVICE_MASK;
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return val;
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}
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/**