Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/i915/vga: Extract intel_vga_regs.h

Extract the VGACNTR register definitions into their own
header file, to declutter i915_reg.h a bit.

v2: Group the register offst definitions together (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

+39 -30
+1
drivers/gpu/drm/i915/display/intel_vga.c
··· 16 16 #include "i915_reg.h" 17 17 #include "intel_de.h" 18 18 #include "intel_vga.h" 19 + #include "intel_vga_regs.h" 19 20 20 21 static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) 21 22 {
+36
drivers/gpu/drm/i915/display/intel_vga_regs.h
··· 1 + /* SPDX-License-Identifier: MIT */ 2 + /* 3 + * Copyright © 2025 Intel Corporation 4 + */ 5 + 6 + #ifndef __INTEL_VGA_REGS_H__ 7 + #define __INTEL_VGA_REGS_H__ 8 + 9 + #include "intel_display_reg_defs.h" 10 + 11 + #define VGACNTRL _MMIO(0x71400) 12 + #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 13 + #define CPU_VGACNTRL _MMIO(0x41000) 14 + #define VGA_DISP_DISABLE REG_BIT(31) 15 + #define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ 16 + #define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ 17 + #define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) 18 + #define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ 19 + #define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) 20 + #define VGA_BORDER_ENABLE REG_BIT(26) 21 + #define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 22 + #define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ 23 + #define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ 24 + #define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ 25 + #define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ 26 + #define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) 27 + #define VGA_PALETTE_BYPASS REG_BIT(19) 28 + #define VGA_NINE_DOT_DISABLE REG_BIT(18) 29 + #define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ 30 + #define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ 31 + #define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ 32 + #define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ 33 + #define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) 34 + #define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) 35 + 36 + #endif /* __INTEL_VGA_REGS_H__ */
+1
drivers/gpu/drm/i915/gvt/handlers.c
··· 56 56 #include "display/intel_pps_regs.h" 57 57 #include "display/intel_psr_regs.h" 58 58 #include "display/intel_sprite_regs.h" 59 + #include "display/intel_vga_regs.h" 59 60 #include "display/skl_universal_plane_regs.h" 60 61 #include "display/skl_watermark_regs.h" 61 62 #include "display/vlv_dsi_pll_regs.h"
-30
drivers/gpu/drm/i915/i915_reg.h
··· 1775 1775 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 1776 1776 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 1777 1777 1778 - /* VBIOS regs */ 1779 - #define VGACNTRL _MMIO(0x71400) 1780 - #define VGA_DISP_DISABLE REG_BIT(31) 1781 - #define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ 1782 - #define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ 1783 - #define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) 1784 - #define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ 1785 - #define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) 1786 - #define VGA_BORDER_ENABLE REG_BIT(26) 1787 - #define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 1788 - #define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ 1789 - #define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ 1790 - #define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ 1791 - #define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ 1792 - #define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) 1793 - #define VGA_PALETTE_BYPASS REG_BIT(19) 1794 - #define VGA_NINE_DOT_DISABLE REG_BIT(18) 1795 - #define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ 1796 - #define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ 1797 - #define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ 1798 - #define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ 1799 - #define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) 1800 - #define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) 1801 - 1802 - #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 1803 - 1804 - /* Ironlake */ 1805 - 1806 - #define CPU_VGACNTRL _MMIO(0x41000) 1807 - 1808 1778 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 1809 1779 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 1810 1780 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
+1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
··· 21 21 #include "display/intel_pfit_regs.h" 22 22 #include "display/intel_psr_regs.h" 23 23 #include "display/intel_sprite_regs.h" 24 + #include "display/intel_vga_regs.h" 24 25 #include "display/skl_universal_plane_regs.h" 25 26 #include "display/skl_watermark_regs.h" 26 27 #include "display/vlv_dsi_pll_regs.h"