Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
8250 Serial Driver: revert extra IRQ flag definition patch
Blackfin arch: update anomaly headers from toolchain trunk
Blackfin arch: Remove bad and usless code
Blackfin arch: Fix bug - set corret SSEL and IRQ to enable AD7877 on BF527
Blackfin arch: Fix typo. it should be _outsw_8
Blackfin arch: Cleanup no functional changes

arch/blackfin/kernel/gptimers.c

···
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/blackfin.h>
 #include <asm/gptimers.h>
 

arch/blackfin/lib/outs.S

···
 		R0 = R0 + R1;
 .Lword8_loop_e: W[P0] = R0;
 	RTS;
-ENDPROC(_outsw)
+ENDPROC(_outsw_8)

arch/blackfin/mach-bf527/boards/ezkit.c

···
 	{
 		.modalias		= "ad7877",
 		.platform_data		= &bfin_ad7877_ts_info,
-		.irq			= IRQ_PF6,
+		.irq			= IRQ_PF8,
 		.max_speed_hz	= 12500000,     /* max spi clock (SCK) speed in HZ */
 		.bus_num	= 0,
-		.chip_select  = 1,
+		.chip_select  = 2,
 		.controller_data = &spi_ad7877_chip_info,
 	},
 #endif

arch/blackfin/mach-bf537/boards/Makefile

···
 #
 
 obj-$(CONFIG_GENERIC_BF537_BOARD)      += generic_board.o
-obj-$(CONFIG_BFIN537_STAMP)            += stamp.o led.o
+obj-$(CONFIG_BFIN537_STAMP)            += stamp.o
 obj-$(CONFIG_BFIN537_BLUETECHNIX_CM)   += cm_bf537.o
 obj-$(CONFIG_PNAV10)                   += pnav10.o
 obj-$(CONFIG_CAMSIG_MINOTAUR)          += minotaur.o

arch/blackfin/mach-bf537/boards/led.S

···
-/****************************************************
- * LED1 ---- PF6        LED2 ---- PF7               *
- * LED3 ---- PF8        LED4 ---- PF9               *
- * LED5 ---- PF10       LED6 ---- PF11              *
- ****************************************************/
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-/* All functions in this file save the registers they uses.
-   So there is no need to save any registers before calling them.  */
-
-	.text;
-
-/* Initialize LEDs.  */
-
-ENTRY(_led_init)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R0;
-	[--SP] = R1;
-	[--SP] = R2;
-	R1 = PF6|PF7|PF8|PF9|PF10|PF11 (Z);
-	R2 = ~R1;
-
-	P0.H = hi(PORTF_FER);
-	P0.L = lo(PORTF_FER);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 & R2;
-	W[P0] = R0.L;
-	SSYNC;
-
-	P0.H = hi(PORTFIO_DIR);
-	P0.L = lo(PORTFIO_DIR);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 | R1;
-	W[P0] = R0.L;
-	SSYNC;
-
-	P0.H = hi(PORTFIO_INEN);
-	P0.L = lo(PORTFIO_INEN);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 & R2;
-	W[P0] = R0.L;
-	SSYNC;
-
-	R2 = [SP++];
-	R1 = [SP++];
-	R0 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_init, .-_led_init
-
-/* Set one LED on. Leave other LEDs unchanged.
-   It expects the LED number passed through R0.  */
-
-ENTRY(_led_on)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	P0.H = hi(PORTFIO);
-	P0.L = lo(PORTFIO);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 | R1;
-	W[P0] = R0.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_on, .-_led_on
-
-/* Set one LED off. Leave other LEDs unchanged.  */
-
-ENTRY(_led_off)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	R1 = ~R1;
-	P0.H = hi(PORTFIO);
-	P0.L = lo(PORTFIO);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 & R1;
-	W[P0] = R0.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_off, .-_led_off
-
-/* Toggle one LED. Leave other LEDs unchanged.  */
-
-ENTRY(_led_toggle)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	P0.H = hi(PORTFIO);
-	P0.L = lo(PORTFIO);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 ^ R1;
-	W[P0] = R0.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_toggle, .-_led_toggle
-
-/* Display the number using LEDs in binary format.  */
-
-ENTRY(_led_disp_num)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R1;
-	[--SP] = R2;
-	CALL _led_init;
-	R1 = 0x3f(X);
-	R0 = R0 & R1;
-	R2 = 6(X);
-	R0 <<= R2;
-	R1 <<= R2;
-	P0.H = hi(PORTFIO);
-	P0.L = lo(PORTFIO);
-	R2 = W[P0](Z);
-	SSYNC;
-	R1 = ~R1;
-	R2 = R2 & R1;
-	R2 = R2 | R0;
-	W[P0] = R2.L;
-	SSYNC;
-	R2 = [SP++];
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_disp_num, .-_led_disp_num
-
-/* Toggle the number using LEDs in binary format.  */
-
-ENTRY(_led_toggle_num)
-	LINK 12;
-	[--SP] = P0;
-	[--SP] = R1;
-	[--SP] = R2;
-	CALL _led_init;
-	R1 = 0x3f(X);
-	R0 = R0 & R1;
-	R1 = 6(X);
-	R0 <<= R1;
-	P0.H = hi(PORTFIO);
-	P0.L = lo(PORTFIO);
-	R1 = W[P0](Z);
-	SSYNC;
-	R1 = R1 ^ R0;
-	W[P0] = R1.L;
-	SSYNC;
-	R2 = [SP++];
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_toggle_num, .-_led_toggle_num
-

arch/blackfin/mach-bf548/boards/Makefile

···
 # arch/blackfin/mach-bf548/boards/Makefile
 #
 
-obj-$(CONFIG_BFIN548_EZKIT)            += ezkit.o led.o
+obj-$(CONFIG_BFIN548_EZKIT)            += ezkit.o
 obj-$(CONFIG_BFIN548_BLUETECHNIX_CM)   += cm_bf548.o

arch/blackfin/mach-bf548/boards/cm_bf548.c

···
 
 static int __init cm_bf548_init(void)
 {
-	printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
+	printk(KERN_INFO "%s(): registering device resources\n", __func__);
 	platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
 
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)

arch/blackfin/mach-bf548/boards/led.S

···
-/****************************************************
- * LED1 ---- PG6        LED2 ---- PG7               *
- * LED3 ---- PG8        LED4 ---- PG9               *
- * LED5 ---- PG10       LED6 ---- PG11              *
- ****************************************************/
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-/* All functions in this file save the registers they uses.
-   So there is no need to save any registers before calling them.  */
-
-	.text;
-
-/* Initialize LEDs.  */
-
-ENTRY(_led_init)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R0;
-	[--SP] = R1;
-	[--SP] = R2;
-	R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
-	R2 = ~R1;
-
-	P0.H = hi(PORTG_FER);
-	P0.L = lo(PORTG_FER);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 & R2;
-	W[P0] = R0.L;
-	SSYNC;
-
-	P0.H = hi(PORTG_DIR_SET);
-	P0.L = lo(PORTG_DIR_SET);
-	W[P0] = R1.L;
-	SSYNC;
-
-	P0.H = hi(PORTG_INEN);
-	P0.L = lo(PORTG_INEN);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 & R2;
-	W[P0] = R0.L;
-	SSYNC;
-
-	R2 = [SP++];
-	R1 = [SP++];
-	R0 = [SP++];
-	P0 = [SP++];
-	RTS;
-	.size	_led_init, .-_led_init
-
-/* Set one LED on. Leave other LEDs unchanged.
-   It expects the LED number passed through R0.  */
-
-ENTRY(_led_on)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	P0.H = hi(PORTG_SET);
-	P0.L = lo(PORTG_SET);
-	W[P0] = R1.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_on, .-_led_on
-
-/* Set one LED off. Leave other LEDs unchanged.  */
-
-ENTRY(_led_off)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	P0.H = hi(PORTG_CLEAR);
-	P0.L = lo(PORTG_CLEAR);
-	W[P0] = R1.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_off, .-_led_off
-
-/* Toggle one LED. Leave other LEDs unchanged.  */
-
-ENTRY(_led_toggle)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R1;
-	CALL _led_init;
-	R1 = 1;
-	R0 += 5;
-	R1 <<= R0;
-	P0.H = hi(PORTG);
-	P0.L = lo(PORTG);
-	R0 = W[P0](Z);
-	SSYNC;
-	R0 = R0 ^ R1;
-	W[P0] = R0.L;
-	SSYNC;
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_toggle, .-_led_toggle
-
-/* Display the number using LEDs in binary format.  */
-
-ENTRY(_led_disp_num)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R1;
-	[--SP] = R2;
-	CALL _led_init;
-	R1 = 0x3f(X);
-	R0 = R0 & R1;
-	R2 = 6(X);
-	R0 <<= R2;
-	R1 <<= R2;
-	P0.H = hi(PORTG);
-	P0.L = lo(PORTG);
-	R2 = W[P0](Z);
-	SSYNC;
-	R1 = ~R1;
-	R2 = R2 & R1;
-	R2 = R2 | R0;
-	W[P0] = R2.L;
-	SSYNC;
-	R2 = [SP++];
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_disp_num, .-_led_disp_num
-
-/* Toggle the number using LEDs in binary format.  */
-
-ENTRY(_led_toggle_num)
-	LINK 0;
-	[--SP] = P0;
-	[--SP] = R1;
-	[--SP] = R2;
-	CALL _led_init;
-	R1 = 0x3f(X);
-	R0 = R0 & R1;
-	R1 = 6(X);
-	R0 <<= R1;
-	P0.H = hi(PORTG);
-	P0.L = lo(PORTG);
-	R1 = W[P0](Z);
-	SSYNC;
-	R1 = R1 ^ R0;
-	W[P0] = R1.L;
-	SSYNC;
-	R2 = [SP++];
-	R1 = [SP++];
-	P0 = [SP++];
-	UNLINK;
-	RTS;
-	.size	_led_toggle_num, .-_led_toggle_num
-

drivers/serial/8250.c

···
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/serial.h>
 
 #include "8250.h"
 
···
  */
 #define CONFIG_HUB6 1
 
+#include <asm/serial.h>
 /*
  * SERIAL_PORT_DFNS tells us about built-in ports that have no
  * standard enumeration mechanism.   Platforms that can find all
···
 		INIT_LIST_HEAD(&up->list);
 		i->head = &up->list;
 		spin_unlock_irq(&i->lock);
-
-		irq_flags |= SERIAL_EXTRA_IRQ_FLAGS;
 
 		ret = request_irq(up->port.irq, serial8250_interrupt,
 				  irq_flags, "serial", i);

drivers/serial/8250.h

···
 #else
 #define ALPHA_KLUDGE_MCR 0
 #endif
-
-#ifndef SERIAL_EXTRA_IRQ_FLAGS
-#define SERIAL_EXTRA_IRQ_FLAGS 0
-#endif
-

include/asm-blackfin/bfin-global.h

···
 extern void *sram_alloc_with_lsl(size_t, unsigned long);
 extern int sram_free_with_lsl(const void*);
 
-extern void led_on(int);
-extern void led_off(int);
-extern void led_toggle(int);
-extern void led_disp_num(int);
-extern void led_toggle_num(int);
-extern void init_leds(void);
-
 extern const char bfin_board_name[];
 extern unsigned long wall_jiffies;
 

include/asm-blackfin/mach-bf527/anomaly.h

···
 
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (1)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
···
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000363 (0)
 

include/asm-blackfin/mach-bf533/anomaly.h

···
  * File: include/asm-blackfin/mach-bf533/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
···
 #define ANOMALY_05000315 (1)
 /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
 #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* PPI Does Not Start Properly In Specific Mode */
+#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+
 
 /* These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
···
 #define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
 /* Internal Voltage Regulator may not start up */
 #define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000266 (0)

include/asm-blackfin/mach-bf537/anomaly.h

···
  * File: include/asm-blackfin/mach-bf537/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
···
 #define ANOMALY_05000322 (1)
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
 #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
-#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
+/* New Feature: UART Remains Enabled after UART Boot */
+#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 #define ANOMALY_05000355 (1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
···
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
-
-
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)

include/asm-blackfin/mach-bf548/anomaly.h

···
 #define ANOMALY_05000365 (1)
 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
 #define ANOMALY_05000369 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
 /* Mobile DDR Operation Not Functional */
 #define ANOMALY_05000377 (1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */

include/asm-blackfin/mach-bf561/anomaly.h

···
  * File: include/asm-blackfin/mach-bf561/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */