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kernel
os
linux
Blackfin: unify DMA masks
Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+50
-301
+49
-20
arch/blackfin/include/asm/dma.h
+49
-20
arch/blackfin/include/asm/dma.h
···
16
16
17
17
#define MAX_DMA_ADDRESS PAGE_OFFSET
18
18
19
-
/*****************************************************************************
20
-
* Generic DMA Declarations
21
-
*
22
-
****************************************************************************/
19
+
/* DMA_CONFIG Masks */
20
+
#define DMAEN 0x0001 /* DMA Channel Enable */
21
+
#define WNR 0x0002 /* Channel Direction (W/R*) */
22
+
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
23
+
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
24
+
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
25
+
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
26
+
#define RESTART 0x0020 /* DMA Buffer Clear */
27
+
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
28
+
#define DI_EN 0x0080 /* Data Interrupt Enable */
29
+
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
30
+
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
31
+
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
32
+
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
33
+
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
34
+
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
35
+
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
36
+
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
37
+
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
38
+
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
39
+
#define NDSIZE 0x0f00 /* Next Descriptor Size */
40
+
#define DMAFLOW 0x7000 /* Flow Control */
41
+
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
42
+
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
43
+
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
44
+
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
45
+
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
46
+
47
+
/* DMA_IRQ_STATUS Masks */
48
+
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
49
+
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
50
+
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
51
+
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
23
52
24
53
/*-------------------------
25
54
* config reg bits value
26
55
*-------------------------*/
27
-
#define DATA_SIZE_8 0
28
-
#define DATA_SIZE_16 1
29
-
#define DATA_SIZE_32 2
56
+
#define DATA_SIZE_8 0
57
+
#define DATA_SIZE_16 1
58
+
#define DATA_SIZE_32 2
30
59
31
-
#define DMA_FLOW_STOP 0
32
-
#define DMA_FLOW_AUTO 1
33
-
#define DMA_FLOW_ARRAY 4
34
-
#define DMA_FLOW_SMALL 6
35
-
#define DMA_FLOW_LARGE 7
60
+
#define DMA_FLOW_STOP 0
61
+
#define DMA_FLOW_AUTO 1
62
+
#define DMA_FLOW_ARRAY 4
63
+
#define DMA_FLOW_SMALL 6
64
+
#define DMA_FLOW_LARGE 7
36
65
37
-
#define DIMENSION_LINEAR 0
38
-
#define DIMENSION_2D 1
66
+
#define DIMENSION_LINEAR 0
67
+
#define DIMENSION_2D 1
39
68
40
-
#define DIR_READ 0
41
-
#define DIR_WRITE 1
69
+
#define DIR_READ 0
70
+
#define DIR_WRITE 1
42
71
43
-
#define INTR_DISABLE 0
44
-
#define INTR_ON_BUF 2
45
-
#define INTR_ON_ROW 3
72
+
#define INTR_DISABLE 0
73
+
#define INTR_ON_BUF 2
74
+
#define INTR_ON_ROW 3
46
75
47
76
#define DMA_NOSYNC_KEEP_DMA_BUF 0
48
-
#define DMA_SYNC_RESTART 1
77
+
#define DMA_SYNC_RESTART 1
49
78
50
79
struct dmasg {
51
80
void *next_desc_addr;
-34
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
-34
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
···
1260
1260
1261
1261
1262
1262
/* ************************** DMA CONTROLLER MASKS ********************************/
1263
-
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1264
-
#define DMAEN 0x0001 /* DMA Channel Enable */
1265
-
#define WNR 0x0002 /* Channel Direction (W/R*) */
1266
-
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1267
-
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1268
-
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1269
-
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1270
-
#define RESTART 0x0020 /* DMA Buffer Clear */
1271
-
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1272
-
#define DI_EN 0x0080 /* Data Interrupt Enable */
1273
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1274
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1275
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1276
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1277
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1278
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1279
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1280
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1281
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1282
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1283
-
#define NDSIZE 0x0900 /* Next Descriptor Size */
1284
-
#define DMAFLOW 0x7000 /* Flow Control */
1285
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1286
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1287
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1288
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1289
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1290
1263
1291
1264
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1292
1265
#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
···
1276
1303
#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1277
1304
#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1278
1305
#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1279
-
1280
-
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1281
-
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1282
-
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1283
-
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1284
-
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1285
-
1286
1306
1287
1307
/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1288
1308
/* PPI_CONTROL Masks */
-34
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
-34
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
···
1269
1269
1270
1270
1271
1271
/* ************************** DMA CONTROLLER MASKS ********************************/
1272
-
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1273
-
#define DMAEN 0x0001 /* DMA Channel Enable */
1274
-
#define WNR 0x0002 /* Channel Direction (W/R*) */
1275
-
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1276
-
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1277
-
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1278
-
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1279
-
#define RESTART 0x0020 /* DMA Buffer Clear */
1280
-
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1281
-
#define DI_EN 0x0080 /* Data Interrupt Enable */
1282
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1283
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1284
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1285
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1286
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1287
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1288
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1289
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1290
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1291
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1292
-
#define NDSIZE 0x0900 /* Next Descriptor Size */
1293
-
#define DMAFLOW 0x7000 /* Flow Control */
1294
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1295
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1296
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1297
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1298
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1299
1272
1300
1273
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1301
1274
#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
···
1285
1312
#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1286
1313
#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1287
1314
#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1288
-
1289
-
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1290
-
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1291
-
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1292
-
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1293
-
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1294
-
1295
1315
1296
1316
/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1297
1317
/* PPI_CONTROL Masks */
+1
-48
arch/blackfin/mach-bf533/include/mach/defBF532.h
+1
-48
arch/blackfin/mach-bf533/include/mach/defBF532.h
···
637
637
638
638
/* ********** DMA CONTROLLER MASKS *********************8 */
639
639
640
-
/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
641
-
#define DMAEN 0x00000001 /* Channel Enable */
642
-
#define WNR 0x00000002 /* Channel Direction (W/R*) */
643
-
#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
644
-
#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
645
-
#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
646
-
#define DMA2D 0x00000010 /* 2D/1D* Mode */
647
-
#define RESTART 0x00000020 /* Restart */
648
-
#define DI_SEL 0x00000040 /* Data Interrupt Select */
649
-
#define DI_EN 0x00000080 /* Data Interrupt Enable */
650
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
651
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
652
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
653
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
654
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
655
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
656
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
657
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
658
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
659
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
660
-
#define NDSIZE 0x00000900 /* Next Descriptor Size */
661
-
#define DMAFLOW 0x00007000 /* Flow Control */
662
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
663
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
664
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
665
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
666
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
667
-
668
-
#define DMAEN_P 0 /* Channel Enable */
669
-
#define WNR_P 1 /* Channel Direction (W/R*) */
670
-
#define DMA2D_P 4 /* 2D/1D* Mode */
671
-
#define RESTART_P 5 /* Restart */
672
-
#define DI_SEL_P 6 /* Data Interrupt Select */
673
-
#define DI_EN_P 7 /* Data Interrupt Enable */
674
-
675
-
/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
676
-
677
-
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
678
-
#define DMA_ERR 0x00000002 /* DMA Error Indicator */
679
-
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
680
-
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
681
-
682
-
#define DMA_DONE_P 0 /* DMA Done Indicator */
683
-
#define DMA_ERR_P 1 /* DMA Error Indicator */
684
-
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
685
-
#define DMA_RUN_P 3 /* DMA Running Indicator */
686
-
687
-
/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
640
+
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
688
641
689
642
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
690
643
#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-34
arch/blackfin/mach-bf537/include/mach/defBF534.h
-34
arch/blackfin/mach-bf537/include/mach/defBF534.h
···
1584
1584
#define BGSTAT 0x0020 /* Bus Grant Status */
1585
1585
1586
1586
/* ************************** DMA CONTROLLER MASKS ********************************/
1587
-
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1588
-
#define DMAEN 0x0001 /* DMA Channel Enable */
1589
-
#define WNR 0x0002 /* Channel Direction (W/R*) */
1590
-
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1591
-
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1592
-
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1593
-
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1594
-
#define RESTART 0x0020 /* DMA Buffer Clear */
1595
-
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1596
-
#define DI_EN 0x0080 /* Data Interrupt Enable */
1597
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1598
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1599
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1600
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1601
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1602
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1603
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1604
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1605
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1606
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1607
-
#define NDSIZE 0x0900 /* Next Descriptor Size */
1608
-
1609
-
#define DMAFLOW 0x7000 /* Flow Control */
1610
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1611
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1612
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1613
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1614
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1615
1587
1616
1588
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1617
1589
#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
···
1600
1628
#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1601
1629
#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1602
1630
#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1603
-
1604
-
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1605
-
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1606
-
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1607
-
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1608
-
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1609
1631
1610
1632
/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1611
1633
/* PPI_CONTROL Masks */
-46
arch/blackfin/mach-bf538/include/mach/defBF539.h
-46
arch/blackfin/mach-bf538/include/mach/defBF539.h
···
1757
1757
1758
1758
1759
1759
/* ********** DMA CONTROLLER MASKS ***********************/
1760
-
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1761
-
#define DMAEN 0x0001 /* Channel Enable */
1762
-
#define WNR 0x0002 /* Channel Direction (W/R*) */
1763
-
#define WDSIZE_8 0x0000 /* Word Size 8 bits */
1764
-
#define WDSIZE_16 0x0004 /* Word Size 16 bits */
1765
-
#define WDSIZE_32 0x0008 /* Word Size 32 bits */
1766
-
#define DMA2D 0x0010 /* 2D/1D* Mode */
1767
-
#define RESTART 0x0020 /* Restart */
1768
-
#define DI_SEL 0x0040 /* Data Interrupt Select */
1769
-
#define DI_EN 0x0080 /* Data Interrupt Enable */
1770
-
#define NDSIZE 0x0900 /* Next Descriptor Size */
1771
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1772
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1773
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1774
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1775
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1776
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1777
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1778
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1779
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1780
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1781
-
1782
-
#define DMAFLOW 0x7000 /* Flow Control */
1783
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1784
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1785
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1786
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1787
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1788
-
1789
-
#define DMAEN_P 0x0 /* Channel Enable */
1790
-
#define WNR_P 0x1 /* Channel Direction (W/R*) */
1791
-
#define DMA2D_P 0x4 /* 2D/1D* Mode */
1792
-
#define RESTART_P 0x5 /* Restart */
1793
-
#define DI_SEL_P 0x6 /* Data Interrupt Select */
1794
-
#define DI_EN_P 0x7 /* Data Interrupt Enable */
1795
-
1796
-
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1797
-
#define DMA_DONE 0x0001 /* DMA Done Indicator */
1798
-
#define DMA_ERR 0x0002 /* DMA Error Indicator */
1799
-
#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
1800
-
#define DMA_RUN 0x0008 /* DMA Running Indicator */
1801
-
1802
-
#define DMA_DONE_P 0x0 /* DMA Done Indicator */
1803
-
#define DMA_ERR_P 0x1 /* DMA Error Indicator */
1804
-
#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
1805
-
#define DMA_RUN_P 0x3 /* DMA Running Indicator */
1806
1760
1807
1761
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1808
1762
-38
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
-38
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
···
1609
1609
#define PINT2 0x40000000 /* Pin Interrupt 2 */
1610
1610
#define PINT3 0x80000000 /* Pin Interrupt 3 */
1611
1611
1612
-
/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1613
-
1614
-
#define DMAEN 0x1 /* DMA Channel Enable */
1615
-
#define WNR 0x2 /* DMA Direction */
1616
-
#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1617
-
#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1618
-
#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1619
-
#define DMA2D 0x10 /* DMA Mode */
1620
-
#define RESTART 0x20 /* Work Unit Transitions */
1621
-
#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1622
-
#define DI_EN 0x80 /* Data Interrupt Enable */
1623
-
1624
-
#define NDSIZE 0xf00 /* Flex Descriptor Size */
1625
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1626
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1627
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1628
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1629
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1630
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1631
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1632
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1633
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1634
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1635
-
1636
-
#define DMAFLOW 0xf000 /* Next Operation */
1637
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1638
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1639
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1640
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1641
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1642
-
1643
-
/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1644
-
1645
-
#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1646
-
#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1647
-
#define DFETCH 0x4 /* DMA Descriptor Fetch */
1648
-
#define DMA_RUN 0x8 /* DMA Channel Running */
1649
-
1650
1612
/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1651
1613
1652
1614
#define CTYPE 0x40 /* DMA Channel Type */
-47
arch/blackfin/mach-bf561/include/mach/defBF561.h
-47
arch/blackfin/mach-bf561/include/mach/defBF561.h
···
1096
1096
1097
1097
/* ********** DMA CONTROLLER MASKS *********************8 */
1098
1098
1099
-
/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
1100
-
#define DMAEN 0x00000001 /* Channel Enable */
1101
-
#define WNR 0x00000002 /* Channel Direction (W/R*) */
1102
-
#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
1103
-
#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
1104
-
#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
1105
-
#define DMA2D 0x00000010 /* 2D/1D* Mode */
1106
-
#define RESTART 0x00000020 /* Restart */
1107
-
#define DI_SEL 0x00000040 /* Data Interrupt Select */
1108
-
#define DI_EN 0x00000080 /* Data Interrupt Enable */
1109
-
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1110
-
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1111
-
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1112
-
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1113
-
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1114
-
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1115
-
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1116
-
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1117
-
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1118
-
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1119
-
#define NDSIZE 0x00000900 /* Next Descriptor Size */
1120
-
#define DMAFLOW 0x00007000 /* Flow Control */
1121
-
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1122
-
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1123
-
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1124
-
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1125
-
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1126
-
1127
-
#define DMAEN_P 0 /* Channel Enable */
1128
-
#define WNR_P 1 /* Channel Direction (W/R*) */
1129
-
#define DMA2D_P 4 /* 2D/1D* Mode */
1130
-
#define RESTART_P 5 /* Restart */
1131
-
#define DI_SEL_P 6 /* Data Interrupt Select */
1132
-
#define DI_EN_P 7 /* Data Interrupt Enable */
1133
-
1134
-
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
1135
-
1136
-
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
1137
-
#define DMA_ERR 0x00000002 /* DMA Error Indicator */
1138
-
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
1139
-
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
1140
-
1141
-
#define DMA_DONE_P 0 /* DMA Done Indicator */
1142
-
#define DMA_ERR_P 1 /* DMA Error Indicator */
1143
-
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
1144
-
#define DMA_RUN_P 3 /* DMA Running Indicator */
1145
-
1146
1099
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
1147
1100
1148
1101
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */