Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

video: fbdev: Fix multiple style issues in xilinxfb

All reported by from checkpatch
./scripts/checkpatch.pl --max-line-length 120 -strict -f
drivers/video/fbdev/xilinxfb.c

WARNING: Block comments should align the * on each line
WARNING: Block comments use a trailing */ on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: please, no space before tabs
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for single statement blocks
WARNING: Missing a blank line after declarations
WARNING: struct of_device_id should normally be const
CHECK: Please don't use multiple blank lines
CHECK: Blank lines aren't necessary after an open brace '{'
CHECK: Alignment should match open parenthesis
CHECK: 'Endianess' may be misspelled - perhaps 'Endianness'?
CHECK: spaces preferred around that '*' (ctx:VxV)
ERROR: that open brace { should be on the previous line

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

authored by

Hyun Kwon and committed by
Bartlomiej Zolnierkiewicz
00a0af9a 69de8496

+28 -28
+28 -28
drivers/video/fbdev/xilinxfb.c
··· 41 42 #define DRIVER_NAME "xilinxfb" 43 44 - 45 /* 46 * Xilinx calls it "TFT LCD Controller" though it can also be used for 47 * the VGA port on the Xilinx ML40x board. This is a hardware display ··· 91 u32 xvirt, yvirt; /* resolution of memory buffer */ 92 93 /* Physical address of framebuffer memory; If non-zero, driver 94 - * will use provided memory address instead of allocating one from 95 - * the consistent pool. */ 96 u32 fb_phys; 97 }; 98 ··· 128 .activate = FB_ACTIVATE_NOW 129 }; 130 131 - 132 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ 133 #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ 134 135 struct xilinxfb_drvdata { 136 - 137 struct fb_info info; /* FB driver info record */ 138 139 phys_addr_t regs_phys; /* phys. address of the control 140 - registers */ 141 void __iomem *regs; /* virt. address of the control 142 - registers */ 143 #ifdef CONFIG_PPC_DCR 144 dcr_host_t dcr_host; 145 unsigned int dcr_len; ··· 148 dma_addr_t fb_phys; /* phys. address of the frame buffer */ 149 int fb_alloced; /* Flag, was the fb memory alloced? */ 150 151 - u8 flags; /* features of the driver */ 152 153 u32 reg_ctrl_default; 154 ··· 165 * which bus its connected and call the appropriate write API. 166 */ 167 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, 168 - u32 val) 169 { 170 if (drvdata->flags & BUS_ACCESS_FLAG) { 171 if (drvdata->flags & LITTLE_ENDIAN_ACCESS) ··· 195 } 196 197 static int 198 - xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, 199 - unsigned transp, struct fb_info *fbi) 200 { 201 u32 *palette = fbi->pseudo_palette; 202 ··· 205 206 if (fbi->var.grayscale) { 207 /* Convert color to grayscale. 208 - * grayscale = 0.30*R + 0.59*G + 0.11*B */ 209 - red = green = blue = 210 - (red * 77 + green * 151 + blue * 28 + 127) >> 8; 211 } 212 213 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ ··· 243 xilinx_fb_out32(drvdata, REG_CTRL, 0); 244 default: 245 break; 246 - 247 } 248 return 0; /* success */ 249 } 250 251 - static struct fb_ops xilinxfb_ops = 252 - { 253 .owner = THIS_MODULE, 254 .fb_setcolreg = xilinx_fb_setcolreg, 255 .fb_blank = xilinx_fb_blank, ··· 286 } else { 287 drvdata->fb_alloced = 1; 288 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize), 289 - &drvdata->fb_phys, GFP_KERNEL); 290 } 291 292 if (!drvdata->fb_virt) { ··· 301 /* Tell the hardware where the frame buffer is */ 302 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); 303 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); 304 - /* Endianess detection */ 305 if (rc != drvdata->fb_phys) { 306 drvdata->flags |= LITTLE_ENDIAN_ACCESS; 307 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); ··· 311 drvdata->reg_ctrl_default = REG_CTRL_ENABLE; 312 if (pdata->rotate_screen) 313 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; 314 - xilinx_fb_out32(drvdata, REG_CTRL, 315 - drvdata->reg_ctrl_default); 316 317 /* Fill struct fb_info */ 318 drvdata->info.device = dev; ··· 364 err_cmap: 365 if (drvdata->fb_alloced) 366 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt, 367 - drvdata->fb_phys); 368 else 369 iounmap(drvdata->fb_virt); 370 ··· 435 * Fill the resource structure if its direct BUS interface 436 * otherwise fill the dcr_host structure. 437 */ 438 - if (tft_access) { 439 drvdata->flags |= BUS_ACCESS_FLAG; 440 - } 441 #ifdef CONFIG_PPC_DCR 442 else { 443 int start; 444 start = dcr_resource_start(pdev->dev.of_node, 0); 445 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); 446 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); ··· 452 #endif 453 454 prop = of_get_property(pdev->dev.of_node, "phys-size", &size); 455 - if ((prop) && (size >= sizeof(u32)*2)) { 456 pdata.screen_width_mm = prop[0]; 457 pdata.screen_height_mm = prop[1]; 458 } 459 460 prop = of_get_property(pdev->dev.of_node, "resolution", &size); 461 - if ((prop) && (size >= sizeof(u32)*2)) { 462 pdata.xres = prop[0]; 463 pdata.yres = prop[1]; 464 } 465 466 prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); 467 - if ((prop) && (size >= sizeof(u32)*2)) { 468 pdata.xvirt = prop[0]; 469 pdata.yvirt = prop[1]; 470 } ··· 482 } 483 484 /* Match table for of_platform binding */ 485 - static struct of_device_id xilinxfb_of_match[] = { 486 { .compatible = "xlnx,xps-tft-1.00.a", }, 487 { .compatible = "xlnx,xps-tft-2.00.a", }, 488 { .compatible = "xlnx,xps-tft-2.01.a", },
··· 41 42 #define DRIVER_NAME "xilinxfb" 43 44 /* 45 * Xilinx calls it "TFT LCD Controller" though it can also be used for 46 * the VGA port on the Xilinx ML40x board. This is a hardware display ··· 92 u32 xvirt, yvirt; /* resolution of memory buffer */ 93 94 /* Physical address of framebuffer memory; If non-zero, driver 95 + * will use provided memory address instead of allocating one from 96 + * the consistent pool. 97 + */ 98 u32 fb_phys; 99 }; 100 ··· 128 .activate = FB_ACTIVATE_NOW 129 }; 130 131 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ 132 #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ 133 134 struct xilinxfb_drvdata { 135 struct fb_info info; /* FB driver info record */ 136 137 phys_addr_t regs_phys; /* phys. address of the control 138 + * registers 139 + */ 140 void __iomem *regs; /* virt. address of the control 141 + * registers 142 + */ 143 #ifdef CONFIG_PPC_DCR 144 dcr_host_t dcr_host; 145 unsigned int dcr_len; ··· 148 dma_addr_t fb_phys; /* phys. address of the frame buffer */ 149 int fb_alloced; /* Flag, was the fb memory alloced? */ 150 151 + u8 flags; /* features of the driver */ 152 153 u32 reg_ctrl_default; 154 ··· 165 * which bus its connected and call the appropriate write API. 166 */ 167 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, 168 + u32 val) 169 { 170 if (drvdata->flags & BUS_ACCESS_FLAG) { 171 if (drvdata->flags & LITTLE_ENDIAN_ACCESS) ··· 195 } 196 197 static int 198 + xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, 199 + unsigned int blue, unsigned int transp, struct fb_info *fbi) 200 { 201 u32 *palette = fbi->pseudo_palette; 202 ··· 205 206 if (fbi->var.grayscale) { 207 /* Convert color to grayscale. 208 + * grayscale = 0.30*R + 0.59*G + 0.11*B 209 + */ 210 + blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8; 211 + green = blue; 212 + red = green; 213 } 214 215 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ ··· 241 xilinx_fb_out32(drvdata, REG_CTRL, 0); 242 default: 243 break; 244 } 245 return 0; /* success */ 246 } 247 248 + static struct fb_ops xilinxfb_ops = { 249 .owner = THIS_MODULE, 250 .fb_setcolreg = xilinx_fb_setcolreg, 251 .fb_blank = xilinx_fb_blank, ··· 286 } else { 287 drvdata->fb_alloced = 1; 288 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize), 289 + &drvdata->fb_phys, 290 + GFP_KERNEL); 291 } 292 293 if (!drvdata->fb_virt) { ··· 300 /* Tell the hardware where the frame buffer is */ 301 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); 302 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); 303 + /* Endianness detection */ 304 if (rc != drvdata->fb_phys) { 305 drvdata->flags |= LITTLE_ENDIAN_ACCESS; 306 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); ··· 310 drvdata->reg_ctrl_default = REG_CTRL_ENABLE; 311 if (pdata->rotate_screen) 312 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; 313 + xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); 314 315 /* Fill struct fb_info */ 316 drvdata->info.device = dev; ··· 364 err_cmap: 365 if (drvdata->fb_alloced) 366 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt, 367 + drvdata->fb_phys); 368 else 369 iounmap(drvdata->fb_virt); 370 ··· 435 * Fill the resource structure if its direct BUS interface 436 * otherwise fill the dcr_host structure. 437 */ 438 + if (tft_access) 439 drvdata->flags |= BUS_ACCESS_FLAG; 440 #ifdef CONFIG_PPC_DCR 441 else { 442 int start; 443 + 444 start = dcr_resource_start(pdev->dev.of_node, 0); 445 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); 446 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); ··· 452 #endif 453 454 prop = of_get_property(pdev->dev.of_node, "phys-size", &size); 455 + if ((prop) && (size >= sizeof(u32) * 2)) { 456 pdata.screen_width_mm = prop[0]; 457 pdata.screen_height_mm = prop[1]; 458 } 459 460 prop = of_get_property(pdev->dev.of_node, "resolution", &size); 461 + if ((prop) && (size >= sizeof(u32) * 2)) { 462 pdata.xres = prop[0]; 463 pdata.yres = prop[1]; 464 } 465 466 prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); 467 + if ((prop) && (size >= sizeof(u32) * 2)) { 468 pdata.xvirt = prop[0]; 469 pdata.yvirt = prop[1]; 470 } ··· 482 } 483 484 /* Match table for of_platform binding */ 485 + static const struct of_device_id xilinxfb_of_match[] = { 486 { .compatible = "xlnx,xps-tft-1.00.a", }, 487 { .compatible = "xlnx,xps-tft-2.00.a", }, 488 { .compatible = "xlnx,xps-tft-2.01.a", },