Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm: change drm set mode messages as DRM_DEBUG
drm: fix crtc no modes printf + typo
drm/radeon/kms: only evict to GTT if CP is ready
drm/radeon/kms: Fix crash getting TV info with no BIOS.
drm/radeon/kms/rv100: reject modes > 135 Mhz on DVI (v2)
drm/radeon/kms/r6xx+: make irq handler less verbose
drm/radeon/kms: fix up LVDS handling on macs (v2)

+42 -8
+3 -2
drivers/gpu/drm/drm_crtc_helper.c
··· 702 if (encoder->crtc != crtc) 703 continue; 704 705 - DRM_INFO("%s: set mode %s %x\n", drm_get_encoder_name(encoder), 706 mode->name, mode->base.id); 707 encoder_funcs = encoder->helper_private; 708 encoder_funcs->mode_set(encoder, mode, adjusted_mode); ··· 1032 /* 1033 * we shouldn't end up with no modes here. 1034 */ 1035 - printk(KERN_INFO "No connectors reported conncted with modes\n"); 1036 1037 drm_setup_crtcs(dev); 1038
··· 702 if (encoder->crtc != crtc) 703 continue; 704 705 + DRM_DEBUG("%s: set mode %s %x\n", drm_get_encoder_name(encoder), 706 mode->name, mode->base.id); 707 encoder_funcs = encoder->helper_private; 708 encoder_funcs->mode_set(encoder, mode, adjusted_mode); ··· 1032 /* 1033 * we shouldn't end up with no modes here. 1034 */ 1035 + if (count == 0) 1036 + printk(KERN_INFO "No connectors reported connected with modes\n"); 1037 1038 drm_setup_crtcs(dev); 1039
+4 -4
drivers/gpu/drm/radeon/r600.c
··· 2729 } 2730 break; 2731 default: 2732 - DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2733 break; 2734 } 2735 break; ··· 2749 } 2750 break; 2751 default: 2752 - DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2753 break; 2754 } 2755 break; ··· 2798 } 2799 break; 2800 default: 2801 - DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2802 break; 2803 } 2804 break; ··· 2812 DRM_DEBUG("IH: CP EOP\n"); 2813 break; 2814 default: 2815 - DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2816 break; 2817 } 2818
··· 2729 } 2730 break; 2731 default: 2732 + DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2733 break; 2734 } 2735 break; ··· 2749 } 2750 break; 2751 default: 2752 + DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2753 break; 2754 } 2755 break; ··· 2798 } 2799 break; 2800 default: 2801 + DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2802 break; 2803 } 2804 break; ··· 2812 DRM_DEBUG("IH: CP EOP\n"); 2813 break; 2814 default: 2815 + DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2816 break; 2817 } 2818
+3
drivers/gpu/drm/radeon/radeon_combios.c
··· 687 uint16_t tv_info; 688 enum radeon_tv_std tv_std = TV_STD_NTSC; 689 690 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 691 if (tv_info) { 692 if (RBIOS8(tv_info + 6) == 'T') {
··· 687 uint16_t tv_info; 688 enum radeon_tv_std tv_std = TV_STD_NTSC; 689 690 + if (rdev->bios == NULL) 691 + return tv_std; 692 + 693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 694 if (tv_info) { 695 if (RBIOS8(tv_info + 6) == 'T') {
+8
drivers/gpu/drm/radeon/radeon_connectors.c
··· 900 static int radeon_dvi_mode_valid(struct drm_connector *connector, 901 struct drm_display_mode *mode) 902 { 903 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 904 905 /* XXX check mode bandwidth */ 906 907 if (radeon_connector->use_digital && (mode->clock > 165000)) { 908 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
··· 900 static int radeon_dvi_mode_valid(struct drm_connector *connector, 901 struct drm_display_mode *mode) 902 { 903 + struct drm_device *dev = connector->dev; 904 + struct radeon_device *rdev = dev->dev_private; 905 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 906 907 /* XXX check mode bandwidth */ 908 + 909 + /* clocks over 135 MHz have heat issues with DVI on RV100 */ 910 + if (radeon_connector->use_digital && 911 + (rdev->family == CHIP_RV100) && 912 + (mode->clock > 135000)) 913 + return MODE_CLOCK_HIGH; 914 915 if (radeon_connector->use_digital && (mode->clock > 165000)) { 916 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
+20 -1
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
··· 46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 48 int panel_pwr_delay = 2000; 49 DRM_DEBUG("\n"); 50 51 if (radeon_encoder->enc_priv) { ··· 58 panel_pwr_delay = lvds->panel_pwr_delay; 59 } 60 } 61 62 switch (mode) { 63 case DRM_MODE_DPMS_ON: ··· 84 85 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 86 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); 87 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); 88 udelay(panel_pwr_delay * 1000); 89 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); ··· 97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 98 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 99 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 100 - lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 101 udelay(panel_pwr_delay * 1000); 102 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 103 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
··· 46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 48 int panel_pwr_delay = 2000; 49 + bool is_mac = false; 50 DRM_DEBUG("\n"); 51 52 if (radeon_encoder->enc_priv) { ··· 57 panel_pwr_delay = lvds->panel_pwr_delay; 58 } 59 } 60 + 61 + /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 62 + * Taken from radeonfb. 63 + */ 64 + if ((rdev->mode_info.connector_table == CT_IBOOK) || 65 + (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 66 + (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 67 + (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 68 + is_mac = true; 69 70 switch (mode) { 71 case DRM_MODE_DPMS_ON: ··· 74 75 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 76 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); 77 + if (is_mac) 78 + lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 79 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); 80 udelay(panel_pwr_delay * 1000); 81 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); ··· 85 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 86 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 87 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 88 + if (is_mac) { 89 + lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 90 + WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 91 + lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 92 + } else { 93 + WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 94 + lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 95 + } 96 udelay(panel_pwr_delay * 1000); 97 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 98 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+4 -1
drivers/gpu/drm/radeon/radeon_ttm.c
··· 215 rbo = container_of(bo, struct radeon_bo, tbo); 216 switch (bo->mem.mem_type) { 217 case TTM_PL_VRAM: 218 - radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 219 break; 220 case TTM_PL_TT: 221 default:
··· 215 rbo = container_of(bo, struct radeon_bo, tbo); 216 switch (bo->mem.mem_type) { 217 case TTM_PL_VRAM: 218 + if (rbo->rdev->cp.ready == false) 219 + radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 220 + else 221 + radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 222 break; 223 case TTM_PL_TT: 224 default: