Merge tag 'sound-fix-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

+13

Documentation/sound/alsa-configuration.rst

··· 133 133 enable card; 134 134 Default: enabled, for PCI and ISA PnP cards 135 135 136 + These options are used for either specifying the order of instances or 137 + controlling enabling and disabling of each one of the devices if there 138 + are multiple devices bound with the same driver. For example, there are 139 + many machines which have two HD-audio controllers (one for HDMI/DP 140 + audio and another for onboard analog). In most cases, the second one is 141 + in primary usage, and people would like to assign it as the first 142 + appearing card. They can do it by specifying "index=1,0" module 143 + parameter, which will swap the assignment slots. 144 + 145 + Today, with the sound backend like PulseAudio and PipeWire which 146 + supports dynamic configuration, it's of little use, but that was a 147 + help for static configuration in the past. 148 + 136 149 Module snd-adlib 137 150 ---------------- 138 151

+11 -11

Documentation/sound/kernel-api/writing-an-alsa-driver.rst

··· 3994 3994 3995 3995 Suppose you have a file xyz.c. Add the following two lines:: 3996 3996 3997 - snd-xyz-objs := xyz.o 3998 - obj-$(CONFIG_SND_XYZ) += snd-xyz.o 3997 + snd-xyz-objs := xyz.o 3998 + obj-$(CONFIG_SND_XYZ) += snd-xyz.o 3999 3999 4000 4000 2. Create the Kconfig entry 4001 4001 4002 4002 Add the new entry of Kconfig for your xyz driver:: 4003 4003 4004 - config SND_XYZ 4005 - tristate "Foobar XYZ" 4006 - depends on SND 4007 - select SND_PCM 4008 - help 4009 - Say Y here to include support for Foobar XYZ soundcard. 4010 - To compile this driver as a module, choose M here: 4011 - the module will be called snd-xyz. 4004 + config SND_XYZ 4005 + tristate "Foobar XYZ" 4006 + depends on SND 4007 + select SND_PCM 4008 + help 4009 + Say Y here to include support for Foobar XYZ soundcard. 4010 + To compile this driver as a module, choose M here: 4011 + the module will be called snd-xyz. 4012 4012 4013 4013 The line ``select SND_PCM`` specifies that the driver xyz supports PCM. 4014 4014 In addition to SND_PCM, the following components are supported for ··· 4032 4032 1. Add a new directory (``sound/pci/xyz``) in ``sound/pci/Makefile`` 4033 4033 as below:: 4034 4034 4035 - obj-$(CONFIG_SND) += sound/pci/xyz/ 4035 + obj-$(CONFIG_SND) += sound/pci/xyz/ 4036 4036 4037 4037 4038 4038 2. Under the directory ``sound/pci/xyz``, create a Makefile::

+72 -33

sound/core/pcm_lib.c

··· 33 33 static int fill_silence_frames(struct snd_pcm_substream *substream, 34 34 snd_pcm_uframes_t off, snd_pcm_uframes_t frames); 35 35 36 + 37 + static inline void update_silence_vars(struct snd_pcm_runtime *runtime, 38 + snd_pcm_uframes_t ptr, 39 + snd_pcm_uframes_t new_ptr) 40 + { 41 + snd_pcm_sframes_t delta; 42 + 43 + delta = new_ptr - ptr; 44 + if (delta == 0) 45 + return; 46 + if (delta < 0) 47 + delta += runtime->boundary; 48 + if ((snd_pcm_uframes_t)delta < runtime->silence_filled) 49 + runtime->silence_filled -= delta; 50 + else 51 + runtime->silence_filled = 0; 52 + runtime->silence_start = new_ptr; 53 + } 54 + 36 55 /* 37 56 * fill ring buffer with silence 38 57 * runtime->silence_start: starting pointer to silence area ··· 61 42 * 62 43 * when runtime->silence_size >= runtime->boundary - fill processed area with silence immediately 63 44 */ 64 - void snd_pcm_playback_silence(struct snd_pcm_substream *substream) 45 + void snd_pcm_playback_silence(struct snd_pcm_substream *substream, snd_pcm_uframes_t new_hw_ptr) 65 46 { 66 47 struct snd_pcm_runtime *runtime = substream->runtime; 67 - snd_pcm_uframes_t appl_ptr = READ_ONCE(runtime->control->appl_ptr); 68 - snd_pcm_sframes_t added, hw_avail, frames; 69 - snd_pcm_uframes_t noise_dist, ofs, transfer; 48 + snd_pcm_uframes_t frames, ofs, transfer; 70 49 int err; 71 50 72 - added = appl_ptr - runtime->silence_start; 73 - if (added) { 74 - if (added < 0) 75 - added += runtime->boundary; 76 - if (added < runtime->silence_filled) 77 - runtime->silence_filled -= added; 78 - else 79 - runtime->silence_filled = 0; 80 - runtime->silence_start = appl_ptr; 81 - } 82 - 83 - // This will "legitimately" turn negative on underrun, and will be mangled 84 - // into a huge number by the boundary crossing handling. The initial state 85 - // might also be not quite sane. The code below MUST account for these cases. 86 - hw_avail = appl_ptr - runtime->status->hw_ptr; 87 - if (hw_avail < 0) 88 - hw_avail += runtime->boundary; 89 - 90 - noise_dist = hw_avail + runtime->silence_filled; 91 51 if (runtime->silence_size < runtime->boundary) { 92 - frames = runtime->silence_threshold - noise_dist; 93 - if (frames <= 0) 52 + snd_pcm_sframes_t noise_dist; 53 + snd_pcm_uframes_t appl_ptr = READ_ONCE(runtime->control->appl_ptr); 54 + update_silence_vars(runtime, runtime->silence_start, appl_ptr); 55 + /* initialization outside pointer updates */ 56 + if (new_hw_ptr == ULONG_MAX) 57 + new_hw_ptr = runtime->status->hw_ptr; 58 + /* get hw_avail with the boundary crossing */ 59 + noise_dist = appl_ptr - new_hw_ptr; 60 + if (noise_dist < 0) 61 + noise_dist += runtime->boundary; 62 + /* total noise distance */ 63 + noise_dist += runtime->silence_filled; 64 + if (noise_dist >= (snd_pcm_sframes_t) runtime->silence_threshold) 94 65 return; 66 + frames = runtime->silence_threshold - noise_dist; 95 67 if (frames > runtime->silence_size) 96 68 frames = runtime->silence_size; 97 69 } else { 98 - frames = runtime->buffer_size - noise_dist; 99 - if (frames <= 0) 100 - return; 70 + /* 71 + * This filling mode aims at free-running mode (used for example by dmix), 72 + * which doesn't update the application pointer. 73 + */ 74 + snd_pcm_uframes_t hw_ptr = runtime->status->hw_ptr; 75 + if (new_hw_ptr == ULONG_MAX) { 76 + /* 77 + * Initialization, fill the whole unused buffer with silence. 78 + * 79 + * Usually, this is entered while stopped, before data is queued, 80 + * so both pointers are expected to be zero. 81 + */ 82 + snd_pcm_sframes_t avail = runtime->control->appl_ptr - hw_ptr; 83 + if (avail < 0) 84 + avail += runtime->boundary; 85 + /* 86 + * In free-running mode, appl_ptr will be zero even while running, 87 + * so we end up with a huge number. There is no useful way to 88 + * handle this, so we just clear the whole buffer. 89 + */ 90 + runtime->silence_filled = avail > runtime->buffer_size ? 0 : avail; 91 + runtime->silence_start = hw_ptr; 92 + } else { 93 + /* Silence the just played area immediately */ 94 + update_silence_vars(runtime, hw_ptr, new_hw_ptr); 95 + } 96 + /* 97 + * In this mode, silence_filled actually includes the valid 98 + * sample data from the user. 99 + */ 100 + frames = runtime->buffer_size - runtime->silence_filled; 101 101 } 102 - 103 102 if (snd_BUG_ON(frames > runtime->buffer_size)) 103 + return; 104 + if (frames == 0) 104 105 return; 105 106 ofs = (runtime->silence_start + runtime->silence_filled) % runtime->buffer_size; 106 107 do { ··· 464 425 return 0; 465 426 } 466 427 428 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 429 + runtime->silence_size > 0) 430 + snd_pcm_playback_silence(substream, new_hw_ptr); 431 + 467 432 if (in_interrupt) { 468 433 delta = new_hw_ptr - runtime->hw_ptr_interrupt; 469 434 if (delta < 0) ··· 484 441 snd_BUG_ON(crossed_boundary != 1); 485 442 runtime->hw_ptr_wrap += runtime->boundary; 486 443 } 487 - 488 - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 489 - runtime->silence_size > 0) 490 - snd_pcm_playback_silence(substream); 491 444 492 445 update_audio_tstamp(substream, &curr_tstamp, &audio_tstamp); 493 446

+2 -1

sound/core/pcm_local.h

··· 29 29 struct snd_pcm_runtime *runtime); 30 30 int snd_pcm_update_hw_ptr(struct snd_pcm_substream *substream); 31 31 32 - void snd_pcm_playback_silence(struct snd_pcm_substream *substream); 32 + void snd_pcm_playback_silence(struct snd_pcm_substream *substream, 33 + snd_pcm_uframes_t new_hw_ptr); 33 34 34 35 static inline snd_pcm_uframes_t 35 36 snd_pcm_avail(struct snd_pcm_substream *substream)

+3 -3

sound/core/pcm_native.c

··· 958 958 if (snd_pcm_running(substream)) { 959 959 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 960 960 runtime->silence_size > 0) 961 - snd_pcm_playback_silence(substream); 961 + snd_pcm_playback_silence(substream, ULONG_MAX); 962 962 err = snd_pcm_update_state(substream, runtime); 963 963 } 964 964 snd_pcm_stream_unlock_irq(substream); ··· 1455 1455 __snd_pcm_set_state(runtime, state); 1456 1456 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 1457 1457 runtime->silence_size > 0) 1458 - snd_pcm_playback_silence(substream); 1458 + snd_pcm_playback_silence(substream, ULONG_MAX); 1459 1459 snd_pcm_timer_notify(substream, SNDRV_TIMER_EVENT_MSTART); 1460 1460 } 1461 1461 ··· 1916 1916 runtime->control->appl_ptr = runtime->status->hw_ptr; 1917 1917 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 1918 1918 runtime->silence_size > 0) 1919 - snd_pcm_playback_silence(substream); 1919 + snd_pcm_playback_silence(substream, ULONG_MAX); 1920 1920 snd_pcm_stream_unlock_irq(substream); 1921 1921 } 1922 1922

+8 -7

sound/pci/emu10k1/emu10k1_callback.c

··· 120 120 struct snd_emu10k1 *hw; 121 121 122 122 hw = vp->hw; 123 - dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease; 123 + dcysusv = (unsigned char)vp->reg.parm.modrelease | DCYSUSM_PHASE1_MASK; 124 124 snd_emu10k1_ptr_write(hw, DCYSUSM, vp->ch, dcysusv); 125 - dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease | DCYSUSV_CHANNELENABLE_MASK; 125 + dcysusv = (unsigned char)vp->reg.parm.volrelease | DCYSUSV_PHASE1_MASK | DCYSUSV_CHANNELENABLE_MASK; 126 126 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, dcysusv); 127 127 } 128 128 ··· 138 138 if (snd_BUG_ON(!vp)) 139 139 return; 140 140 hw = vp->hw; 141 - snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK); 141 + snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 142 + DCYSUSV_PHASE1_MASK | DCYSUSV_DECAYTIME_MASK | DCYSUSV_CHANNELENABLE_MASK); 142 143 if (vp->block) { 143 144 struct snd_emu10k1_memblk *emem; 144 145 emem = (struct snd_emu10k1_memblk *)vp->block; ··· 348 347 } 349 348 350 349 /* channel to be silent and idle */ 351 - snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0x0000); 352 - snd_emu10k1_ptr_write(hw, VTFT, ch, 0x0000FFFF); 353 - snd_emu10k1_ptr_write(hw, CVCF, ch, 0x0000FFFF); 350 + snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0); 351 + snd_emu10k1_ptr_write(hw, VTFT, ch, VTFT_FILTERTARGET_MASK); 352 + snd_emu10k1_ptr_write(hw, CVCF, ch, CVCF_CURRENTFILTER_MASK); 354 353 snd_emu10k1_ptr_write(hw, PTRX, ch, 0); 355 354 snd_emu10k1_ptr_write(hw, CPF, ch, 0); 356 355 ··· 454 453 /* reset volume */ 455 454 temp = (unsigned int)vp->vtarget << 16; 456 455 snd_emu10k1_ptr_write(hw, VTFT, ch, temp | vp->ftarget); 457 - snd_emu10k1_ptr_write(hw, CVCF, ch, temp | 0xff00); 456 + snd_emu10k1_ptr_write(hw, CVCF, ch, temp | CVCF_CURRENTFILTER_MASK); 458 457 return 0; 459 458 } 460 459

+23 -23

sound/pci/emu10k1/emu10k1_main.c

··· 59 59 { 60 60 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0); 61 61 snd_emu10k1_ptr_write(emu, IP, ch, 0); 62 - snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff); 63 - snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff); 62 + snd_emu10k1_ptr_write(emu, VTFT, ch, VTFT_FILTERTARGET_MASK); 63 + snd_emu10k1_ptr_write(emu, CVCF, ch, CVCF_CURRENTFILTER_MASK); 64 64 snd_emu10k1_ptr_write(emu, PTRX, ch, 0); 65 65 snd_emu10k1_ptr_write(emu, CPF, ch, 0); 66 66 snd_emu10k1_ptr_write(emu, CCR, ch, 0); ··· 74 74 75 75 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0); 76 76 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0); 77 - snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff); 77 + snd_emu10k1_ptr_write(emu, IFATN, ch, IFATN_FILTERCUTOFF_MASK | IFATN_ATTENUATION_MASK); 78 78 snd_emu10k1_ptr_write(emu, PEFE, ch, 0); 79 79 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0); 80 80 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */ ··· 90 90 91 91 /* Audigy extra stuffs */ 92 92 if (emu->audigy) { 93 - snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */ 94 - snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */ 95 - snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */ 96 - snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */ 93 + snd_emu10k1_ptr_write(emu, A_CSBA, ch, 0); 94 + snd_emu10k1_ptr_write(emu, A_CSDC, ch, 0); 95 + snd_emu10k1_ptr_write(emu, A_CSFE, ch, 0); 96 + snd_emu10k1_ptr_write(emu, A_CSHG, ch, 0); 97 97 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100); 98 98 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f); 99 99 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0); ··· 259 259 260 260 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr); 261 261 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */ 262 - snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */ 262 + snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_256K); /* taken from original driver */ 263 263 264 264 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); 265 265 for (ch = 0; ch < NUM_G; ch++) { ··· 818 818 /* FPGA netlist already present so clear it */ 819 819 /* Return to programming mode */ 820 820 821 - snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02); 821 + snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA); 822 822 } 823 823 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg); 824 824 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); ··· 858 858 /* Optical -> ADAT I/O */ 859 859 emu->emu1010.optical_in = 1; /* IN_ADAT */ 860 860 emu->emu1010.optical_out = 1; /* OUT_ADAT */ 861 - tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) | 862 - (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0); 861 + tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 862 + (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 863 863 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 864 864 /* Set no attenuation on Audio Dock pads. */ 865 - snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00); 866 865 emu->emu1010.adc_pads = 0x00; 866 + snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, emu->emu1010.adc_pads); 867 867 /* Unmute Audio dock DACs, Headphone source DAC-4. */ 868 - snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30); 868 + snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, EMU_HANA_DOCK_PHONES_192_DAC4); 869 869 /* DAC PADs. */ 870 - snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f); 871 - emu->emu1010.dac_pads = 0x0f; 870 + emu->emu1010.dac_pads = EMU_HANA_DOCK_DAC_PAD1 | EMU_HANA_DOCK_DAC_PAD2 | 871 + EMU_HANA_DOCK_DAC_PAD3 | EMU_HANA_DOCK_DAC_PAD4; 872 + snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, emu->emu1010.dac_pads); 872 873 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */ 873 - snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); 874 + snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, EMU_HANA_SPDIF_MODE_RX_INVALID); 874 875 /* MIDI routing */ 875 - snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); 876 - /* Unknown. */ 877 - snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); 876 + snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, EMU_HANA_MIDI_INA_FROM_HAMOA | EMU_HANA_MIDI_INB_FROM_DOCK2); 877 + snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, EMU_HANA_MIDI_OUT_DOCK2 | EMU_HANA_MIDI_OUT_SYNC2); 878 878 /* IRQ Enable: All on */ 879 - /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */ 879 + /* snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x0f); */ 880 880 /* IRQ Enable: All off */ 881 881 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00); 882 882 883 883 emu->emu1010.internal_clock = 1; /* 48000 */ 884 884 /* Default WCLK set to 48kHz. */ 885 - snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00); 885 + snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K); 886 886 /* Word Clock source, Internal 48kHz x1 */ 887 887 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K); 888 888 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */ 889 889 /* Audio Dock LEDs. */ 890 - snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); 890 + snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_LOCK | EMU_HANA_DOCK_LEDS_2_48K); 891 891 892 892 #if 0 893 893 /* For 96kHz */ ··· 1014 1014 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1); 1015 1015 snd_emu1010_fpga_link_dst_src_write(emu, 1016 1016 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1); 1017 - snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */ 1017 + snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 1018 1018 1019 1019 #if 0 1020 1020 snd_emu1010_fpga_link_dst_src_write(emu,

+3 -3

sound/pci/emu10k1/emufx.c

··· 1355 1355 gpr += 2; 1356 1356 1357 1357 /* mic capture buffer */ 1358 - A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R)); 1358 + A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1359 1359 1360 1360 /* Audigy CD Playback Volume */ 1361 1361 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); ··· 1438 1438 1439 1439 /* Stereo Mix Center Playback */ 1440 1440 /* Center = sub = Left/2 + Right/2 */ 1441 - A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1)); 1441 + A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1442 1442 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1443 1443 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1444 1444 gpr++; ··· 2478 2478 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2479 2479 spin_unlock_irq(&emu->emu_lock); 2480 2480 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2481 - snd_emu10k1_ptr_write(emu, TCBS, 0, 0); 2481 + snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2482 2482 if (emu->fx8010.etram_pages.area != NULL) { 2483 2483 snd_dma_free_pages(&emu->fx8010.etram_pages); 2484 2484 emu->fx8010.etram_pages.area = NULL;

+4 -4

sound/pci/emu10k1/emumixer.c

··· 827 827 change = (emu->emu1010.optical_out != val); 828 828 if (change) { 829 829 emu->emu1010.optical_out = val; 830 - tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) | 831 - (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0); 830 + tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 831 + (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 832 832 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 833 833 } 834 834 return change; ··· 878 878 change = (emu->emu1010.optical_in != val); 879 879 if (change) { 880 880 emu->emu1010.optical_in = val; 881 - tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) | 882 - (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0); 881 + tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 882 + (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 883 883 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 884 884 } 885 885 return change;

+6 -6

sound/pci/emu10k1/emupcm.c

··· 352 352 snd_emu10k1_ptr_write(emu, MAPA, voice, silent_page); 353 353 snd_emu10k1_ptr_write(emu, MAPB, voice, silent_page); 354 354 /* modulation envelope */ 355 - snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff); 356 - snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff); 355 + snd_emu10k1_ptr_write(emu, VTFT, voice, VTFT_FILTERTARGET_MASK); 356 + snd_emu10k1_ptr_write(emu, CVCF, voice, CVCF_CURRENTFILTER_MASK); 357 357 snd_emu10k1_ptr_write(emu, ATKHLDM, voice, 0); 358 358 snd_emu10k1_ptr_write(emu, DCYSUSM, voice, 0x007f); 359 359 snd_emu10k1_ptr_write(emu, LFOVAL1, voice, 0x8000); ··· 621 621 tmp = runtime->channels == 2 ? (master ? 1 : 2) : 0; 622 622 vattn = mix != NULL ? (mix->attn[tmp] << 16) : 0; 623 623 snd_emu10k1_ptr_write(emu, IFATN, voice, attn); 624 - snd_emu10k1_ptr_write(emu, VTFT, voice, vattn | 0xffff); 625 - snd_emu10k1_ptr_write(emu, CVCF, voice, vattn | 0xffff); 624 + snd_emu10k1_ptr_write(emu, VTFT, voice, vattn | VTFT_FILTERTARGET_MASK); 625 + snd_emu10k1_ptr_write(emu, CVCF, voice, vattn | CVCF_CURRENTFILTER_MASK); 626 626 snd_emu10k1_ptr_write(emu, DCYSUSV, voice, 0x7f7f); 627 627 snd_emu10k1_voice_clear_loop_stop(emu, voice); 628 628 } ··· 663 663 snd_emu10k1_ptr_write(emu, PTRX_PITCHTARGET, voice, 0); 664 664 snd_emu10k1_ptr_write(emu, CPF_CURRENTPITCH, voice, 0); 665 665 snd_emu10k1_ptr_write(emu, IFATN, voice, 0xffff); 666 - snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff); 667 - snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff); 666 + snd_emu10k1_ptr_write(emu, VTFT, voice, VTFT_FILTERTARGET_MASK); 667 + snd_emu10k1_ptr_write(emu, CVCF, voice, CVCF_CURRENTFILTER_MASK); 668 668 snd_emu10k1_ptr_write(emu, IP, voice, 0); 669 669 } 670 670

+9 -9

sound/pci/emu10k1/io.c

··· 95 95 regptr = (reg << 16) | chn; 96 96 97 97 spin_lock_irqsave(&emu->emu_lock, flags); 98 - outl(regptr, emu->port + 0x20 + PTR); 99 - val = inl(emu->port + 0x20 + DATA); 98 + outl(regptr, emu->port + PTR2); 99 + val = inl(emu->port + DATA2); 100 100 spin_unlock_irqrestore(&emu->emu_lock, flags); 101 101 return val; 102 102 } ··· 112 112 regptr = (reg << 16) | chn; 113 113 114 114 spin_lock_irqsave(&emu->emu_lock, flags); 115 - outl(regptr, emu->port + 0x20 + PTR); 116 - outl(data, emu->port + 0x20 + DATA); 115 + outl(regptr, emu->port + PTR2); 116 + outl(data, emu->port + DATA2); 117 117 spin_unlock_irqrestore(&emu->emu_lock, flags); 118 118 } 119 119 ··· 128 128 /* This function is not re-entrant, so protect against it. */ 129 129 spin_lock(&emu->spi_lock); 130 130 if (emu->card_capabilities->ca0108_chip) 131 - reg = 0x3c; /* PTR20, reg 0x3c */ 131 + reg = P17V_SPI; 132 132 else { 133 133 /* For other chip types the SPI register 134 134 * is currently unknown. */ ··· 280 280 return; 281 281 if (snd_BUG_ON(src & ~0x71f)) 282 282 return; 283 - snd_emu1010_fpga_write(emu, 0x00, dst >> 8); 284 - snd_emu1010_fpga_write(emu, 0x01, dst & 0x1f); 285 - snd_emu1010_fpga_write(emu, 0x02, src >> 8); 286 - snd_emu1010_fpga_write(emu, 0x03, src & 0x1f); 283 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8); 284 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f); 285 + snd_emu1010_fpga_write(emu, EMU_HANA_SRCHI, src >> 8); 286 + snd_emu1010_fpga_write(emu, EMU_HANA_SRCLO, src & 0x1f); 287 287 } 288 288 289 289 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)

+16 -13

sound/pci/emu10k1/p16v.c

··· 254 254 emu->p16v_buffer->bytes); 255 255 #endif /* debug */ 256 256 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel); 257 + tmp &= ~(A_SPDIF_RATE_MASK | A_EHC_SRC48_MASK); 257 258 switch (runtime->rate) { 258 259 case 44100: 259 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x8080); 260 + snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 261 + tmp | A_SPDIF_44100 | A_EHC_SRC48_44); 260 262 break; 261 263 case 96000: 262 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x4040); 264 + snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 265 + tmp | A_SPDIF_96000 | A_EHC_SRC48_96); 263 266 break; 264 267 case 192000: 265 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x2020); 268 + snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 269 + tmp | A_SPDIF_192000 | A_EHC_SRC48_192); 266 270 break; 267 271 case 48000: 268 272 default: 269 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x0000); 273 + snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, 274 + tmp | A_SPDIF_48000 | A_EHC_SRC48_BYPASS); 270 275 break; 271 276 } 272 277 /* FIXME: Check emu->buffer.size before actually writing to it. */ ··· 287 282 //snd_emu10k1_ptr20_write(emu, PLAYBACK_PERIOD_SIZE, channel, frames_to_bytes(runtime, runtime->period_size)<<16); // buffer size in bytes 288 283 snd_emu10k1_ptr20_write(emu, PLAYBACK_PERIOD_SIZE, channel, 0); // buffer size in bytes 289 284 snd_emu10k1_ptr20_write(emu, PLAYBACK_POINTER, channel, 0); 290 - snd_emu10k1_ptr20_write(emu, 0x07, channel, 0x0); 291 - snd_emu10k1_ptr20_write(emu, 0x08, channel, 0); 285 + snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_END_ADDRESS, channel, 0); 286 + snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_POINTER, channel, 0); 292 287 293 288 return 0; 294 289 } ··· 299 294 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); 300 295 struct snd_pcm_runtime *runtime = substream->runtime; 301 296 int channel = substream->pcm->device - emu->p16v_device_offset; 302 - u32 tmp; 303 297 304 298 /* 305 299 dev_dbg(emu->card->dev, "prepare capture:channel_number=%d, rate=%d, " ··· 308 304 runtime->buffer_size, runtime->period_size, 309 305 frames_to_bytes(runtime, 1)); 310 306 */ 311 - tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel); 312 307 switch (runtime->rate) { 313 308 case 44100: 314 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0800); 309 + snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_44100); 315 310 break; 316 311 case 96000: 317 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0400); 312 + snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_96000); 318 313 break; 319 314 case 192000: 320 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0200); 315 + snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_192000); 321 316 break; 322 317 case 48000: 323 318 default: 324 - snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0000); 319 + snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_48000); 325 320 break; 326 321 } 327 322 /* FIXME: Check emu->buffer.size before actually writing to it. */ 328 - snd_emu10k1_ptr20_write(emu, 0x13, channel, 0); 323 + snd_emu10k1_ptr20_write(emu, CAPTURE_FIFO_POINTER, channel, 0); 329 324 snd_emu10k1_ptr20_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr); 330 325 snd_emu10k1_ptr20_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size) << 16); // buffer size in bytes 331 326 snd_emu10k1_ptr20_write(emu, CAPTURE_POINTER, channel, 0);

+21

sound/pci/hda/hda_intel.c

··· 227 227 AZX_DRIVER_ATI, 228 228 AZX_DRIVER_ATIHDMI, 229 229 AZX_DRIVER_ATIHDMI_NS, 230 + AZX_DRIVER_GFHDMI, 230 231 AZX_DRIVER_VIA, 231 232 AZX_DRIVER_SIS, 232 233 AZX_DRIVER_ULI, ··· 350 349 [AZX_DRIVER_ATI] = "HDA ATI SB", 351 350 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 352 351 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 352 + [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 353 353 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 354 354 [AZX_DRIVER_SIS] = "HDA SIS966", 355 355 [AZX_DRIVER_ULI] = "HDA ULI M5461", ··· 1745 1743 } 1746 1744 1747 1745 switch (chip->driver_type) { 1746 + /* 1747 + * increase the bdl size for Glenfly Gpus for hardware 1748 + * limitation on hdac interrupt interval 1749 + */ 1750 + case AZX_DRIVER_GFHDMI: 1751 + return 128; 1748 1752 case AZX_DRIVER_ICH: 1749 1753 case AZX_DRIVER_PCH: 1750 1754 return 1; ··· 1866 1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1867 1859 } 1868 1860 #endif 1861 + /* 1862 + * Fix response write request not synced to memory when handle 1863 + * hdac interrupt on Glenfly Gpus 1864 + */ 1865 + if (chip->driver_type == AZX_DRIVER_GFHDMI) 1866 + bus->polling_mode = 1; 1869 1867 1870 1868 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1871 1869 if (err < 0) ··· 1973 1959 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1974 1960 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1975 1961 break; 1962 + case AZX_DRIVER_GFHDMI: 1976 1963 case AZX_DRIVER_GENERIC: 1977 1964 default: 1978 1965 chip->playback_streams = ICH6_NUM_PLAYBACK; ··· 2742 2727 { PCI_DEVICE(0x1002, 0xab38), 2743 2728 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2744 2729 AZX_DCAPS_PM_RUNTIME }, 2730 + /* GLENFLY */ 2731 + { PCI_DEVICE(0x6766, PCI_ANY_ID), 2732 + .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2733 + .class_mask = 0xffffff, 2734 + .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2735 + AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2745 2736 /* VIA VT8251/VT8237A */ 2746 2737 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2747 2738 /* VIA GFX VT7122/VX900 */

+22

sound/pci/hda/patch_hdmi.c

··· 4485 4485 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4486 4486 } 4487 4487 4488 + static int patch_gf_hdmi(struct hda_codec *codec) 4489 + { 4490 + int err; 4491 + 4492 + err = patch_generic_hdmi(codec); 4493 + if (err) 4494 + return err; 4495 + 4496 + /* 4497 + * Glenfly GPUs have two codecs, stream switches from one codec to 4498 + * another, need to do actual clean-ups in codec_cleanup_stream 4499 + */ 4500 + codec->no_sticky_stream = 1; 4501 + return 0; 4502 + } 4503 + 4488 4504 /* 4489 4505 * patch entries 4490 4506 */ ··· 4591 4575 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4592 4576 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4593 4577 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4578 + HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi), 4579 + HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi), 4580 + HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi), 4581 + HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi), 4582 + HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi), 4583 + HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi), 4594 4584 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4595 4585 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4596 4586 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),

+5

sound/pci/hda/patch_realtek.c

··· 9428 9428 SND_PCI_QUIRK(0x103c, 0x8898, "HP EliteBook 845 G8 Notebook PC", ALC285_FIXUP_HP_LIMIT_INT_MIC_BOOST), 9429 9429 SND_PCI_QUIRK(0x103c, 0x88d0, "HP Pavilion 15-eh1xxx (mainboard 88D0)", ALC287_FIXUP_HP_GPIO_LED), 9430 9430 SND_PCI_QUIRK(0x103c, 0x8902, "HP OMEN 16", ALC285_FIXUP_HP_MUTE_LED), 9431 + SND_PCI_QUIRK(0x103c, 0x8919, "HP Pavilion Aero Laptop 13-be0xxx", ALC287_FIXUP_HP_GPIO_LED), 9431 9432 SND_PCI_QUIRK(0x103c, 0x896d, "HP ZBook Firefly 16 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9432 9433 SND_PCI_QUIRK(0x103c, 0x896e, "HP EliteBook x360 830 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9433 9434 SND_PCI_QUIRK(0x103c, 0x8971, "HP EliteBook 830 G9", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), ··· 9479 9478 SND_PCI_QUIRK(0x103c, 0x8b8d, "HP", ALC236_FIXUP_HP_GPIO_LED), 9480 9479 SND_PCI_QUIRK(0x103c, 0x8b8f, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9481 9480 SND_PCI_QUIRK(0x103c, 0x8b92, "HP", ALC245_FIXUP_CS35L41_SPI_2_HP_GPIO_LED), 9481 + SND_PCI_QUIRK(0x103c, 0x8b96, "HP", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF), 9482 9482 SND_PCI_QUIRK(0x103c, 0x8bf0, "HP", ALC236_FIXUP_HP_GPIO_LED), 9483 9483 SND_PCI_QUIRK(0x1043, 0x103e, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), 9484 9484 SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), ··· 9502 9500 SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_ASUS_ZENBOOK), 9503 9501 SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A), 9504 9502 SND_PCI_QUIRK(0x1043, 0x1662, "ASUS GV301QH", ALC294_FIXUP_ASUS_DUAL_SPK), 9503 + SND_PCI_QUIRK(0x1043, 0x1683, "ASUS UM3402YAR", ALC287_FIXUP_CS35L41_I2C_2), 9505 9504 SND_PCI_QUIRK(0x1043, 0x16b2, "ASUS GU603", ALC289_FIXUP_ASUS_GA401), 9506 9505 SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC), 9507 9506 SND_PCI_QUIRK(0x1043, 0x1740, "ASUS UX430UA", ALC295_FIXUP_ASUS_DACS), ··· 9692 9689 SND_PCI_QUIRK(0x17aa, 0x22f1, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9693 9690 SND_PCI_QUIRK(0x17aa, 0x22f2, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9694 9691 SND_PCI_QUIRK(0x17aa, 0x22f3, "Thinkpad", ALC287_FIXUP_CS35L41_I2C_2), 9692 + SND_PCI_QUIRK(0x17aa, 0x2316, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), 9693 + SND_PCI_QUIRK(0x17aa, 0x2317, "Thinkpad P1 Gen 6", ALC287_FIXUP_CS35L41_I2C_2), 9695 9694 SND_PCI_QUIRK(0x17aa, 0x2318, "Thinkpad Z13 Gen2", ALC287_FIXUP_CS35L41_I2C_2), 9696 9695 SND_PCI_QUIRK(0x17aa, 0x2319, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2), 9697 9696 SND_PCI_QUIRK(0x17aa, 0x231a, "Thinkpad Z16 Gen2", ALC287_FIXUP_CS35L41_I2C_2),

+14

sound/soc/amd/yc/acp6x-mach.c

··· 230 230 { 231 231 .driver_data = &acp6x_card, 232 232 .matches = { 233 + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."), 234 + DMI_MATCH(DMI_PRODUCT_NAME, "M6400RC"), 235 + } 236 + }, 237 + { 238 + .driver_data = &acp6x_card, 239 + .matches = { 240 + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."), 241 + DMI_MATCH(DMI_PRODUCT_NAME, "M3402RA"), 242 + } 243 + }, 244 + { 245 + .driver_data = &acp6x_card, 246 + .matches = { 233 247 DMI_MATCH(DMI_BOARD_VENDOR, "Alienware"), 234 248 DMI_MATCH(DMI_PRODUCT_NAME, "Alienware m17 R5 AMD"), 235 249 }

+1 -1

sound/soc/codecs/Kconfig

··· 1090 1090 depends on I2C 1091 1091 1092 1092 config SND_SOC_MAX98090 1093 - tristate 1093 + tristate "Maxim MAX98090 CODEC" 1094 1094 depends on I2C 1095 1095 1096 1096 config SND_SOC_MAX98095

+1025 -12

sound/soc/codecs/wcd938x-sdw.c

··· 161 161 static int wcd9380_update_status(struct sdw_slave *slave, 162 162 enum sdw_slave_status status) 163 163 { 164 + struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev); 165 + 166 + if (wcd->regmap && (status == SDW_SLAVE_ATTACHED)) { 167 + /* Write out any cached changes that happened between probe and attach */ 168 + regcache_cache_only(wcd->regmap, false); 169 + return regcache_sync(wcd->regmap); 170 + } 171 + 164 172 return 0; 165 173 } 166 174 ··· 185 177 { 186 178 struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev); 187 179 struct irq_domain *slave_irq = wcd->slave_irq; 188 - struct regmap *regmap = dev_get_regmap(&slave->dev, NULL); 189 180 u32 sts1, sts2, sts3; 190 181 191 182 do { 192 183 handle_nested_irq(irq_find_mapping(slave_irq, 0)); 193 - regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1); 194 - regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2); 195 - regmap_read(regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3); 184 + regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1); 185 + regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2); 186 + regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3); 196 187 197 188 } while (sts1 || sts2 || sts3); 198 189 199 190 return IRQ_HANDLED; 200 191 } 192 + 193 + static const struct reg_default wcd938x_defaults[] = { 194 + {WCD938X_ANA_PAGE_REGISTER, 0x00}, 195 + {WCD938X_ANA_BIAS, 0x00}, 196 + {WCD938X_ANA_RX_SUPPLIES, 0x00}, 197 + {WCD938X_ANA_HPH, 0x0C}, 198 + {WCD938X_ANA_EAR, 0x00}, 199 + {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, 200 + {WCD938X_ANA_TX_CH1, 0x20}, 201 + {WCD938X_ANA_TX_CH2, 0x00}, 202 + {WCD938X_ANA_TX_CH3, 0x20}, 203 + {WCD938X_ANA_TX_CH4, 0x00}, 204 + {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, 205 + {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, 206 + {WCD938X_ANA_MBHC_MECH, 0x39}, 207 + {WCD938X_ANA_MBHC_ELECT, 0x08}, 208 + {WCD938X_ANA_MBHC_ZDET, 0x00}, 209 + {WCD938X_ANA_MBHC_RESULT_1, 0x00}, 210 + {WCD938X_ANA_MBHC_RESULT_2, 0x00}, 211 + {WCD938X_ANA_MBHC_RESULT_3, 0x00}, 212 + {WCD938X_ANA_MBHC_BTN0, 0x00}, 213 + {WCD938X_ANA_MBHC_BTN1, 0x10}, 214 + {WCD938X_ANA_MBHC_BTN2, 0x20}, 215 + {WCD938X_ANA_MBHC_BTN3, 0x30}, 216 + {WCD938X_ANA_MBHC_BTN4, 0x40}, 217 + {WCD938X_ANA_MBHC_BTN5, 0x50}, 218 + {WCD938X_ANA_MBHC_BTN6, 0x60}, 219 + {WCD938X_ANA_MBHC_BTN7, 0x70}, 220 + {WCD938X_ANA_MICB1, 0x10}, 221 + {WCD938X_ANA_MICB2, 0x10}, 222 + {WCD938X_ANA_MICB2_RAMP, 0x00}, 223 + {WCD938X_ANA_MICB3, 0x10}, 224 + {WCD938X_ANA_MICB4, 0x10}, 225 + {WCD938X_BIAS_CTL, 0x2A}, 226 + {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, 227 + {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, 228 + {WCD938X_LDOL_DISABLE_LDOL, 0x00}, 229 + {WCD938X_MBHC_CTL_CLK, 0x00}, 230 + {WCD938X_MBHC_CTL_ANA, 0x00}, 231 + {WCD938X_MBHC_CTL_SPARE_1, 0x00}, 232 + {WCD938X_MBHC_CTL_SPARE_2, 0x00}, 233 + {WCD938X_MBHC_CTL_BCS, 0x00}, 234 + {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, 235 + {WCD938X_MBHC_TEST_CTL, 0x00}, 236 + {WCD938X_LDOH_MODE, 0x2B}, 237 + {WCD938X_LDOH_BIAS, 0x68}, 238 + {WCD938X_LDOH_STB_LOADS, 0x00}, 239 + {WCD938X_LDOH_SLOWRAMP, 0x50}, 240 + {WCD938X_MICB1_TEST_CTL_1, 0x1A}, 241 + {WCD938X_MICB1_TEST_CTL_2, 0x00}, 242 + {WCD938X_MICB1_TEST_CTL_3, 0xA4}, 243 + {WCD938X_MICB2_TEST_CTL_1, 0x1A}, 244 + {WCD938X_MICB2_TEST_CTL_2, 0x00}, 245 + {WCD938X_MICB2_TEST_CTL_3, 0x24}, 246 + {WCD938X_MICB3_TEST_CTL_1, 0x1A}, 247 + {WCD938X_MICB3_TEST_CTL_2, 0x00}, 248 + {WCD938X_MICB3_TEST_CTL_3, 0xA4}, 249 + {WCD938X_MICB4_TEST_CTL_1, 0x1A}, 250 + {WCD938X_MICB4_TEST_CTL_2, 0x00}, 251 + {WCD938X_MICB4_TEST_CTL_3, 0xA4}, 252 + {WCD938X_TX_COM_ADC_VCM, 0x39}, 253 + {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, 254 + {WCD938X_TX_COM_SPARE1, 0x00}, 255 + {WCD938X_TX_COM_SPARE2, 0x00}, 256 + {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, 257 + {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, 258 + {WCD938X_TX_COM_SPARE3, 0x00}, 259 + {WCD938X_TX_COM_SPARE4, 0x00}, 260 + {WCD938X_TX_1_2_TEST_EN, 0xCC}, 261 + {WCD938X_TX_1_2_ADC_IB, 0xE9}, 262 + {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, 263 + {WCD938X_TX_1_2_TEST_CTL, 0x38}, 264 + {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, 265 + {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, 266 + {WCD938X_TX_1_2_SAR2_ERR, 0x00}, 267 + {WCD938X_TX_1_2_SAR1_ERR, 0x00}, 268 + {WCD938X_TX_3_4_TEST_EN, 0xCC}, 269 + {WCD938X_TX_3_4_ADC_IB, 0xE9}, 270 + {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, 271 + {WCD938X_TX_3_4_TEST_CTL, 0x38}, 272 + {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, 273 + {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, 274 + {WCD938X_TX_3_4_SAR4_ERR, 0x00}, 275 + {WCD938X_TX_3_4_SAR3_ERR, 0x00}, 276 + {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, 277 + {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, 278 + {WCD938X_TX_3_4_SPARE1, 0x00}, 279 + {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, 280 + {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, 281 + {WCD938X_TX_3_4_SPARE2, 0x00}, 282 + {WCD938X_CLASSH_MODE_1, 0x40}, 283 + {WCD938X_CLASSH_MODE_2, 0x3A}, 284 + {WCD938X_CLASSH_MODE_3, 0x00}, 285 + {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, 286 + {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, 287 + {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, 288 + {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, 289 + {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, 290 + {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, 291 + {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, 292 + {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, 293 + {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, 294 + {WCD938X_CLASSH_SPARE, 0x00}, 295 + {WCD938X_FLYBACK_EN, 0x4E}, 296 + {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, 297 + {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, 298 + {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, 299 + {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, 300 + {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, 301 + {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, 302 + {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, 303 + {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, 304 + {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, 305 + {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, 306 + {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, 307 + {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, 308 + {WCD938X_FLYBACK_CTRL_1, 0x65}, 309 + {WCD938X_FLYBACK_TEST_CTL, 0x00}, 310 + {WCD938X_RX_AUX_SW_CTL, 0x00}, 311 + {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, 312 + {WCD938X_RX_TIMER_DIV, 0x32}, 313 + {WCD938X_RX_OCP_CTL, 0x1F}, 314 + {WCD938X_RX_OCP_COUNT, 0x77}, 315 + {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, 316 + {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, 317 + {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, 318 + {WCD938X_RX_BIAS_HPH_PA, 0xAA}, 319 + {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, 320 + {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, 321 + {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, 322 + {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, 323 + {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, 324 + {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, 325 + {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, 326 + {WCD938X_RX_BIAS_MISC, 0x00}, 327 + {WCD938X_RX_BIAS_BUCK_RST, 0x08}, 328 + {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, 329 + {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, 330 + {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, 331 + {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, 332 + {WCD938X_HPH_L_STATUS, 0x04}, 333 + {WCD938X_HPH_R_STATUS, 0x04}, 334 + {WCD938X_HPH_CNP_EN, 0x80}, 335 + {WCD938X_HPH_CNP_WG_CTL, 0x9A}, 336 + {WCD938X_HPH_CNP_WG_TIME, 0x14}, 337 + {WCD938X_HPH_OCP_CTL, 0x28}, 338 + {WCD938X_HPH_AUTO_CHOP, 0x16}, 339 + {WCD938X_HPH_CHOP_CTL, 0x83}, 340 + {WCD938X_HPH_PA_CTL1, 0x46}, 341 + {WCD938X_HPH_PA_CTL2, 0x50}, 342 + {WCD938X_HPH_L_EN, 0x80}, 343 + {WCD938X_HPH_L_TEST, 0xE0}, 344 + {WCD938X_HPH_L_ATEST, 0x50}, 345 + {WCD938X_HPH_R_EN, 0x80}, 346 + {WCD938X_HPH_R_TEST, 0xE0}, 347 + {WCD938X_HPH_R_ATEST, 0x54}, 348 + {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, 349 + {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, 350 + {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, 351 + {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, 352 + {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, 353 + {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, 354 + {WCD938X_HPH_L_DAC_CTL, 0x20}, 355 + {WCD938X_HPH_R_DAC_CTL, 0x20}, 356 + {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, 357 + {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, 358 + {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, 359 + {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, 360 + {WCD938X_EAR_EAR_EN_REG, 0x22}, 361 + {WCD938X_EAR_EAR_PA_CON, 0x44}, 362 + {WCD938X_EAR_EAR_SP_CON, 0xDB}, 363 + {WCD938X_EAR_EAR_DAC_CON, 0x80}, 364 + {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, 365 + {WCD938X_EAR_TEST_CTL, 0x00}, 366 + {WCD938X_EAR_STATUS_REG_1, 0x00}, 367 + {WCD938X_EAR_STATUS_REG_2, 0x08}, 368 + {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, 369 + {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, 370 + {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, 371 + {WCD938X_SLEEP_CTL, 0x16}, 372 + {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, 373 + {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, 374 + {WCD938X_MBHC_NEW_CTL_1, 0x02}, 375 + {WCD938X_MBHC_NEW_CTL_2, 0x05}, 376 + {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, 377 + {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, 378 + {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, 379 + {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, 380 + {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, 381 + {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, 382 + {WCD938X_AUX_AUXPA, 0x00}, 383 + {WCD938X_LDORXTX_MODE, 0x0C}, 384 + {WCD938X_LDORXTX_CONFIG, 0x10}, 385 + {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, 386 + {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, 387 + {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, 388 + {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, 389 + {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, 390 + {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, 391 + {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, 392 + {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, 393 + {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, 394 + {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, 395 + {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, 396 + {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, 397 + {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, 398 + {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, 399 + {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, 400 + {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, 401 + {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, 402 + {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, 403 + {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, 404 + {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, 405 + {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, 406 + {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, 407 + {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, 408 + {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, 409 + {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, 410 + {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, 411 + {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, 412 + {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, 413 + {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, 414 + {WCD938X_AUX_INT_EN_REG, 0x00}, 415 + {WCD938X_AUX_INT_PA_CTRL, 0x06}, 416 + {WCD938X_AUX_INT_SP_CTRL, 0xD2}, 417 + {WCD938X_AUX_INT_DAC_CTRL, 0x80}, 418 + {WCD938X_AUX_INT_CLK_CTRL, 0x50}, 419 + {WCD938X_AUX_INT_TEST_CTRL, 0x00}, 420 + {WCD938X_AUX_INT_STATUS_REG, 0x00}, 421 + {WCD938X_AUX_INT_MISC, 0x00}, 422 + {WCD938X_LDORXTX_INT_BIAS, 0x6E}, 423 + {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, 424 + {WCD938X_LDORXTX_INT_TEST0, 0x1C}, 425 + {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, 426 + {WCD938X_LDORXTX_INT_TEST1, 0x1F}, 427 + {WCD938X_LDORXTX_INT_STATUS, 0x00}, 428 + {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, 429 + {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, 430 + {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, 431 + {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, 432 + {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, 433 + {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, 434 + {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, 435 + {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, 436 + {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, 437 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, 438 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, 439 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, 440 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, 441 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, 442 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, 443 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, 444 + {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, 445 + {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, 446 + {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, 447 + {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, 448 + {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, 449 + {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, 450 + {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, 451 + {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, 452 + {WCD938X_DIGITAL_CHIP_ID0, 0x00}, 453 + {WCD938X_DIGITAL_CHIP_ID1, 0x00}, 454 + {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, 455 + {WCD938X_DIGITAL_CHIP_ID3, 0x01}, 456 + {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, 457 + {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, 458 + {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, 459 + {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, 460 + {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, 461 + {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, 462 + {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, 463 + {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, 464 + {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, 465 + {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, 466 + {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, 467 + {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, 468 + {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, 469 + {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, 470 + {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, 471 + {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, 472 + {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, 473 + {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, 474 + {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, 475 + {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, 476 + {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, 477 + {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, 478 + {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, 479 + {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, 480 + {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, 481 + {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, 482 + {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, 483 + {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, 484 + {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, 485 + {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, 486 + {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, 487 + {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, 488 + {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, 489 + {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, 490 + {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, 491 + {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, 492 + {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, 493 + {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, 494 + {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, 495 + {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, 496 + {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, 497 + {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, 498 + {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, 499 + {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, 500 + {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, 501 + {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, 502 + {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, 503 + {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, 504 + {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, 505 + {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, 506 + {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, 507 + {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, 508 + {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, 509 + {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, 510 + {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, 511 + {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, 512 + {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, 513 + {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, 514 + {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, 515 + {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, 516 + {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, 517 + {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, 518 + {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, 519 + {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, 520 + {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, 521 + {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, 522 + {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, 523 + {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, 524 + {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, 525 + {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, 526 + {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, 527 + {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, 528 + {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, 529 + {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, 530 + {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, 531 + {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, 532 + {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, 533 + {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, 534 + {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, 535 + {WCD938X_DIGITAL_CDC_RST, 0x00}, 536 + {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, 537 + {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, 538 + {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, 539 + {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, 540 + {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, 541 + {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, 542 + {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, 543 + {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, 544 + {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, 545 + {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, 546 + {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, 547 + {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, 548 + {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, 549 + {WCD938X_DIGITAL_INTR_MODE, 0x00}, 550 + {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, 551 + {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, 552 + {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, 553 + {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, 554 + {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, 555 + {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, 556 + {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, 557 + {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, 558 + {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, 559 + {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, 560 + {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, 561 + {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, 562 + {WCD938X_DIGITAL_INTR_SET_0, 0x00}, 563 + {WCD938X_DIGITAL_INTR_SET_1, 0x00}, 564 + {WCD938X_DIGITAL_INTR_SET_2, 0x00}, 565 + {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, 566 + {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, 567 + {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, 568 + {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, 569 + {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, 570 + {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, 571 + {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, 572 + {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, 573 + {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, 574 + {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, 575 + {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, 576 + {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, 577 + {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, 578 + {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, 579 + {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, 580 + {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, 581 + {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, 582 + {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, 583 + {WCD938X_DIGITAL_I2C_CTL, 0x00}, 584 + {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, 585 + {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, 586 + {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, 587 + {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, 588 + {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, 589 + {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, 590 + {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, 591 + {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, 592 + {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, 593 + {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, 594 + {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, 595 + {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, 596 + {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, 597 + {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, 598 + {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, 599 + {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, 600 + {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, 601 + {WCD938X_DIGITAL_GPIO_MODE, 0x00}, 602 + {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, 603 + {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, 604 + {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, 605 + {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, 606 + {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, 607 + {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, 608 + {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, 609 + {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, 610 + {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, 611 + {WCD938X_DIGITAL_SSP_DBG, 0x00}, 612 + {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, 613 + {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, 614 + {WCD938X_DIGITAL_SPARE_0, 0x00}, 615 + {WCD938X_DIGITAL_SPARE_1, 0x00}, 616 + {WCD938X_DIGITAL_SPARE_2, 0x00}, 617 + {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, 618 + {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, 619 + {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, 620 + {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, 621 + {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, 622 + {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, 623 + {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, 624 + {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, 625 + {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, 626 + {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, 627 + {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, 628 + {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, 629 + {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, 630 + {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, 631 + {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, 632 + {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, 633 + {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, 634 + {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, 635 + {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, 636 + {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, 637 + {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, 638 + {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, 639 + {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, 640 + {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, 641 + {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, 642 + {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, 643 + {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, 644 + {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, 645 + {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, 646 + {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, 647 + {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, 648 + {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, 649 + {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, 650 + {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, 651 + {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, 652 + {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, 653 + {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, 654 + {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, 655 + {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, 656 + {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, 657 + {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, 658 + }; 659 + 660 + static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) 661 + { 662 + switch (reg) { 663 + case WCD938X_ANA_PAGE_REGISTER: 664 + case WCD938X_ANA_BIAS: 665 + case WCD938X_ANA_RX_SUPPLIES: 666 + case WCD938X_ANA_HPH: 667 + case WCD938X_ANA_EAR: 668 + case WCD938X_ANA_EAR_COMPANDER_CTL: 669 + case WCD938X_ANA_TX_CH1: 670 + case WCD938X_ANA_TX_CH2: 671 + case WCD938X_ANA_TX_CH3: 672 + case WCD938X_ANA_TX_CH4: 673 + case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: 674 + case WCD938X_ANA_MICB3_DSP_EN_LOGIC: 675 + case WCD938X_ANA_MBHC_MECH: 676 + case WCD938X_ANA_MBHC_ELECT: 677 + case WCD938X_ANA_MBHC_ZDET: 678 + case WCD938X_ANA_MBHC_BTN0: 679 + case WCD938X_ANA_MBHC_BTN1: 680 + case WCD938X_ANA_MBHC_BTN2: 681 + case WCD938X_ANA_MBHC_BTN3: 682 + case WCD938X_ANA_MBHC_BTN4: 683 + case WCD938X_ANA_MBHC_BTN5: 684 + case WCD938X_ANA_MBHC_BTN6: 685 + case WCD938X_ANA_MBHC_BTN7: 686 + case WCD938X_ANA_MICB1: 687 + case WCD938X_ANA_MICB2: 688 + case WCD938X_ANA_MICB2_RAMP: 689 + case WCD938X_ANA_MICB3: 690 + case WCD938X_ANA_MICB4: 691 + case WCD938X_BIAS_CTL: 692 + case WCD938X_BIAS_VBG_FINE_ADJ: 693 + case WCD938X_LDOL_VDDCX_ADJUST: 694 + case WCD938X_LDOL_DISABLE_LDOL: 695 + case WCD938X_MBHC_CTL_CLK: 696 + case WCD938X_MBHC_CTL_ANA: 697 + case WCD938X_MBHC_CTL_SPARE_1: 698 + case WCD938X_MBHC_CTL_SPARE_2: 699 + case WCD938X_MBHC_CTL_BCS: 700 + case WCD938X_MBHC_TEST_CTL: 701 + case WCD938X_LDOH_MODE: 702 + case WCD938X_LDOH_BIAS: 703 + case WCD938X_LDOH_STB_LOADS: 704 + case WCD938X_LDOH_SLOWRAMP: 705 + case WCD938X_MICB1_TEST_CTL_1: 706 + case WCD938X_MICB1_TEST_CTL_2: 707 + case WCD938X_MICB1_TEST_CTL_3: 708 + case WCD938X_MICB2_TEST_CTL_1: 709 + case WCD938X_MICB2_TEST_CTL_2: 710 + case WCD938X_MICB2_TEST_CTL_3: 711 + case WCD938X_MICB3_TEST_CTL_1: 712 + case WCD938X_MICB3_TEST_CTL_2: 713 + case WCD938X_MICB3_TEST_CTL_3: 714 + case WCD938X_MICB4_TEST_CTL_1: 715 + case WCD938X_MICB4_TEST_CTL_2: 716 + case WCD938X_MICB4_TEST_CTL_3: 717 + case WCD938X_TX_COM_ADC_VCM: 718 + case WCD938X_TX_COM_BIAS_ATEST: 719 + case WCD938X_TX_COM_SPARE1: 720 + case WCD938X_TX_COM_SPARE2: 721 + case WCD938X_TX_COM_TXFE_DIV_CTL: 722 + case WCD938X_TX_COM_TXFE_DIV_START: 723 + case WCD938X_TX_COM_SPARE3: 724 + case WCD938X_TX_COM_SPARE4: 725 + case WCD938X_TX_1_2_TEST_EN: 726 + case WCD938X_TX_1_2_ADC_IB: 727 + case WCD938X_TX_1_2_ATEST_REFCTL: 728 + case WCD938X_TX_1_2_TEST_CTL: 729 + case WCD938X_TX_1_2_TEST_BLK_EN1: 730 + case WCD938X_TX_1_2_TXFE1_CLKDIV: 731 + case WCD938X_TX_3_4_TEST_EN: 732 + case WCD938X_TX_3_4_ADC_IB: 733 + case WCD938X_TX_3_4_ATEST_REFCTL: 734 + case WCD938X_TX_3_4_TEST_CTL: 735 + case WCD938X_TX_3_4_TEST_BLK_EN3: 736 + case WCD938X_TX_3_4_TXFE3_CLKDIV: 737 + case WCD938X_TX_3_4_TEST_BLK_EN2: 738 + case WCD938X_TX_3_4_TXFE2_CLKDIV: 739 + case WCD938X_TX_3_4_SPARE1: 740 + case WCD938X_TX_3_4_TEST_BLK_EN4: 741 + case WCD938X_TX_3_4_TXFE4_CLKDIV: 742 + case WCD938X_TX_3_4_SPARE2: 743 + case WCD938X_CLASSH_MODE_1: 744 + case WCD938X_CLASSH_MODE_2: 745 + case WCD938X_CLASSH_MODE_3: 746 + case WCD938X_CLASSH_CTRL_VCL_1: 747 + case WCD938X_CLASSH_CTRL_VCL_2: 748 + case WCD938X_CLASSH_CTRL_CCL_1: 749 + case WCD938X_CLASSH_CTRL_CCL_2: 750 + case WCD938X_CLASSH_CTRL_CCL_3: 751 + case WCD938X_CLASSH_CTRL_CCL_4: 752 + case WCD938X_CLASSH_CTRL_CCL_5: 753 + case WCD938X_CLASSH_BUCK_TMUX_A_D: 754 + case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: 755 + case WCD938X_CLASSH_SPARE: 756 + case WCD938X_FLYBACK_EN: 757 + case WCD938X_FLYBACK_VNEG_CTRL_1: 758 + case WCD938X_FLYBACK_VNEG_CTRL_2: 759 + case WCD938X_FLYBACK_VNEG_CTRL_3: 760 + case WCD938X_FLYBACK_VNEG_CTRL_4: 761 + case WCD938X_FLYBACK_VNEG_CTRL_5: 762 + case WCD938X_FLYBACK_VNEG_CTRL_6: 763 + case WCD938X_FLYBACK_VNEG_CTRL_7: 764 + case WCD938X_FLYBACK_VNEG_CTRL_8: 765 + case WCD938X_FLYBACK_VNEG_CTRL_9: 766 + case WCD938X_FLYBACK_VNEGDAC_CTRL_1: 767 + case WCD938X_FLYBACK_VNEGDAC_CTRL_2: 768 + case WCD938X_FLYBACK_VNEGDAC_CTRL_3: 769 + case WCD938X_FLYBACK_CTRL_1: 770 + case WCD938X_FLYBACK_TEST_CTL: 771 + case WCD938X_RX_AUX_SW_CTL: 772 + case WCD938X_RX_PA_AUX_IN_CONN: 773 + case WCD938X_RX_TIMER_DIV: 774 + case WCD938X_RX_OCP_CTL: 775 + case WCD938X_RX_OCP_COUNT: 776 + case WCD938X_RX_BIAS_EAR_DAC: 777 + case WCD938X_RX_BIAS_EAR_AMP: 778 + case WCD938X_RX_BIAS_HPH_LDO: 779 + case WCD938X_RX_BIAS_HPH_PA: 780 + case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: 781 + case WCD938X_RX_BIAS_HPH_RDAC_LDO: 782 + case WCD938X_RX_BIAS_HPH_CNP1: 783 + case WCD938X_RX_BIAS_HPH_LOWPOWER: 784 + case WCD938X_RX_BIAS_AUX_DAC: 785 + case WCD938X_RX_BIAS_AUX_AMP: 786 + case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: 787 + case WCD938X_RX_BIAS_MISC: 788 + case WCD938X_RX_BIAS_BUCK_RST: 789 + case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: 790 + case WCD938X_RX_BIAS_FLYB_ERRAMP: 791 + case WCD938X_RX_BIAS_FLYB_BUFF: 792 + case WCD938X_RX_BIAS_FLYB_MID_RST: 793 + case WCD938X_HPH_CNP_EN: 794 + case WCD938X_HPH_CNP_WG_CTL: 795 + case WCD938X_HPH_CNP_WG_TIME: 796 + case WCD938X_HPH_OCP_CTL: 797 + case WCD938X_HPH_AUTO_CHOP: 798 + case WCD938X_HPH_CHOP_CTL: 799 + case WCD938X_HPH_PA_CTL1: 800 + case WCD938X_HPH_PA_CTL2: 801 + case WCD938X_HPH_L_EN: 802 + case WCD938X_HPH_L_TEST: 803 + case WCD938X_HPH_L_ATEST: 804 + case WCD938X_HPH_R_EN: 805 + case WCD938X_HPH_R_TEST: 806 + case WCD938X_HPH_R_ATEST: 807 + case WCD938X_HPH_RDAC_CLK_CTL1: 808 + case WCD938X_HPH_RDAC_CLK_CTL2: 809 + case WCD938X_HPH_RDAC_LDO_CTL: 810 + case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: 811 + case WCD938X_HPH_REFBUFF_UHQA_CTL: 812 + case WCD938X_HPH_REFBUFF_LP_CTL: 813 + case WCD938X_HPH_L_DAC_CTL: 814 + case WCD938X_HPH_R_DAC_CTL: 815 + case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: 816 + case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: 817 + case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: 818 + case WCD938X_EAR_EAR_EN_REG: 819 + case WCD938X_EAR_EAR_PA_CON: 820 + case WCD938X_EAR_EAR_SP_CON: 821 + case WCD938X_EAR_EAR_DAC_CON: 822 + case WCD938X_EAR_EAR_CNP_FSM_CON: 823 + case WCD938X_EAR_TEST_CTL: 824 + case WCD938X_ANA_NEW_PAGE_REGISTER: 825 + case WCD938X_HPH_NEW_ANA_HPH2: 826 + case WCD938X_HPH_NEW_ANA_HPH3: 827 + case WCD938X_SLEEP_CTL: 828 + case WCD938X_SLEEP_WATCHDOG_CTL: 829 + case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: 830 + case WCD938X_MBHC_NEW_CTL_1: 831 + case WCD938X_MBHC_NEW_CTL_2: 832 + case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: 833 + case WCD938X_MBHC_NEW_ZDET_ANA_CTL: 834 + case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: 835 + case WCD938X_TX_NEW_AMIC_MUX_CFG: 836 + case WCD938X_AUX_AUXPA: 837 + case WCD938X_LDORXTX_MODE: 838 + case WCD938X_LDORXTX_CONFIG: 839 + case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: 840 + case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: 841 + case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: 842 + case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: 843 + case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: 844 + case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: 845 + case WCD938X_HPH_NEW_INT_PA_MISC1: 846 + case WCD938X_HPH_NEW_INT_PA_MISC2: 847 + case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: 848 + case WCD938X_HPH_NEW_INT_HPH_TIMER1: 849 + case WCD938X_HPH_NEW_INT_HPH_TIMER2: 850 + case WCD938X_HPH_NEW_INT_HPH_TIMER3: 851 + case WCD938X_HPH_NEW_INT_HPH_TIMER4: 852 + case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: 853 + case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: 854 + case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: 855 + case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: 856 + case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: 857 + case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: 858 + case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: 859 + case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: 860 + case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: 861 + case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: 862 + case WCD938X_MBHC_NEW_INT_SPARE_2: 863 + case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: 864 + case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: 865 + case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: 866 + case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: 867 + case WCD938X_AUX_INT_EN_REG: 868 + case WCD938X_AUX_INT_PA_CTRL: 869 + case WCD938X_AUX_INT_SP_CTRL: 870 + case WCD938X_AUX_INT_DAC_CTRL: 871 + case WCD938X_AUX_INT_CLK_CTRL: 872 + case WCD938X_AUX_INT_TEST_CTRL: 873 + case WCD938X_AUX_INT_MISC: 874 + case WCD938X_LDORXTX_INT_BIAS: 875 + case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: 876 + case WCD938X_LDORXTX_INT_TEST0: 877 + case WCD938X_LDORXTX_INT_STARTUP_TIMER: 878 + case WCD938X_LDORXTX_INT_TEST1: 879 + case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: 880 + case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: 881 + case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: 882 + case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: 883 + case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: 884 + case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: 885 + case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: 886 + case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: 887 + case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: 888 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: 889 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: 890 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: 891 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: 892 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: 893 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: 894 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: 895 + case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: 896 + case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: 897 + case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: 898 + case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: 899 + case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: 900 + case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: 901 + case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: 902 + case WCD938X_DIGITAL_PAGE_REGISTER: 903 + case WCD938X_DIGITAL_SWR_TX_CLK_RATE: 904 + case WCD938X_DIGITAL_CDC_RST_CTL: 905 + case WCD938X_DIGITAL_TOP_CLK_CFG: 906 + case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: 907 + case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: 908 + case WCD938X_DIGITAL_SWR_RST_EN: 909 + case WCD938X_DIGITAL_CDC_PATH_MODE: 910 + case WCD938X_DIGITAL_CDC_RX_RST: 911 + case WCD938X_DIGITAL_CDC_RX0_CTL: 912 + case WCD938X_DIGITAL_CDC_RX1_CTL: 913 + case WCD938X_DIGITAL_CDC_RX2_CTL: 914 + case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: 915 + case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: 916 + case WCD938X_DIGITAL_CDC_COMP_CTL_0: 917 + case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: 918 + case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: 919 + case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: 920 + case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: 921 + case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: 922 + case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: 923 + case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: 924 + case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: 925 + case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: 926 + case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: 927 + case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: 928 + case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: 929 + case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: 930 + case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: 931 + case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: 932 + case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: 933 + case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: 934 + case WCD938X_DIGITAL_CDC_HPH_DSM_R1: 935 + case WCD938X_DIGITAL_CDC_HPH_DSM_R2: 936 + case WCD938X_DIGITAL_CDC_HPH_DSM_R3: 937 + case WCD938X_DIGITAL_CDC_HPH_DSM_R4: 938 + case WCD938X_DIGITAL_CDC_HPH_DSM_R5: 939 + case WCD938X_DIGITAL_CDC_HPH_DSM_R6: 940 + case WCD938X_DIGITAL_CDC_HPH_DSM_R7: 941 + case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: 942 + case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: 943 + case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: 944 + case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: 945 + case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: 946 + case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: 947 + case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: 948 + case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: 949 + case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: 950 + case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: 951 + case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: 952 + case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: 953 + case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: 954 + case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: 955 + case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: 956 + case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: 957 + case WCD938X_DIGITAL_CDC_AUX_DSM_R1: 958 + case WCD938X_DIGITAL_CDC_AUX_DSM_R2: 959 + case WCD938X_DIGITAL_CDC_AUX_DSM_R3: 960 + case WCD938X_DIGITAL_CDC_AUX_DSM_R4: 961 + case WCD938X_DIGITAL_CDC_AUX_DSM_R5: 962 + case WCD938X_DIGITAL_CDC_AUX_DSM_R6: 963 + case WCD938X_DIGITAL_CDC_AUX_DSM_R7: 964 + case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: 965 + case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: 966 + case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: 967 + case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: 968 + case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: 969 + case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: 970 + case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: 971 + case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: 972 + case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: 973 + case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: 974 + case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: 975 + case WCD938X_DIGITAL_CDC_SWR_CLH: 976 + case WCD938X_DIGITAL_SWR_CLH_BYP: 977 + case WCD938X_DIGITAL_CDC_TX0_CTL: 978 + case WCD938X_DIGITAL_CDC_TX1_CTL: 979 + case WCD938X_DIGITAL_CDC_TX2_CTL: 980 + case WCD938X_DIGITAL_CDC_TX_RST: 981 + case WCD938X_DIGITAL_CDC_REQ_CTL: 982 + case WCD938X_DIGITAL_CDC_RST: 983 + case WCD938X_DIGITAL_CDC_AMIC_CTL: 984 + case WCD938X_DIGITAL_CDC_DMIC_CTL: 985 + case WCD938X_DIGITAL_CDC_DMIC1_CTL: 986 + case WCD938X_DIGITAL_CDC_DMIC2_CTL: 987 + case WCD938X_DIGITAL_CDC_DMIC3_CTL: 988 + case WCD938X_DIGITAL_CDC_DMIC4_CTL: 989 + case WCD938X_DIGITAL_EFUSE_PRG_CTL: 990 + case WCD938X_DIGITAL_EFUSE_CTL: 991 + case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: 992 + case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: 993 + case WCD938X_DIGITAL_PDM_WD_CTL0: 994 + case WCD938X_DIGITAL_PDM_WD_CTL1: 995 + case WCD938X_DIGITAL_PDM_WD_CTL2: 996 + case WCD938X_DIGITAL_INTR_MODE: 997 + case WCD938X_DIGITAL_INTR_MASK_0: 998 + case WCD938X_DIGITAL_INTR_MASK_1: 999 + case WCD938X_DIGITAL_INTR_MASK_2: 1000 + case WCD938X_DIGITAL_INTR_CLEAR_0: 1001 + case WCD938X_DIGITAL_INTR_CLEAR_1: 1002 + case WCD938X_DIGITAL_INTR_CLEAR_2: 1003 + case WCD938X_DIGITAL_INTR_LEVEL_0: 1004 + case WCD938X_DIGITAL_INTR_LEVEL_1: 1005 + case WCD938X_DIGITAL_INTR_LEVEL_2: 1006 + case WCD938X_DIGITAL_INTR_SET_0: 1007 + case WCD938X_DIGITAL_INTR_SET_1: 1008 + case WCD938X_DIGITAL_INTR_SET_2: 1009 + case WCD938X_DIGITAL_INTR_TEST_0: 1010 + case WCD938X_DIGITAL_INTR_TEST_1: 1011 + case WCD938X_DIGITAL_INTR_TEST_2: 1012 + case WCD938X_DIGITAL_TX_MODE_DBG_EN: 1013 + case WCD938X_DIGITAL_TX_MODE_DBG_0_1: 1014 + case WCD938X_DIGITAL_TX_MODE_DBG_2_3: 1015 + case WCD938X_DIGITAL_LB_IN_SEL_CTL: 1016 + case WCD938X_DIGITAL_LOOP_BACK_MODE: 1017 + case WCD938X_DIGITAL_SWR_DAC_TEST: 1018 + case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: 1019 + case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: 1020 + case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: 1021 + case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: 1022 + case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: 1023 + case WCD938X_DIGITAL_PAD_CTL_SWR_0: 1024 + case WCD938X_DIGITAL_PAD_CTL_SWR_1: 1025 + case WCD938X_DIGITAL_I2C_CTL: 1026 + case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: 1027 + case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: 1028 + case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: 1029 + case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: 1030 + case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: 1031 + case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: 1032 + case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: 1033 + case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: 1034 + case WCD938X_DIGITAL_PAD_INP_DIS_0: 1035 + case WCD938X_DIGITAL_PAD_INP_DIS_1: 1036 + case WCD938X_DIGITAL_DRIVE_STRENGTH_0: 1037 + case WCD938X_DIGITAL_DRIVE_STRENGTH_1: 1038 + case WCD938X_DIGITAL_DRIVE_STRENGTH_2: 1039 + case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: 1040 + case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: 1041 + case WCD938X_DIGITAL_GPIO_MODE: 1042 + case WCD938X_DIGITAL_PIN_CTL_OE: 1043 + case WCD938X_DIGITAL_PIN_CTL_DATA_0: 1044 + case WCD938X_DIGITAL_PIN_CTL_DATA_1: 1045 + case WCD938X_DIGITAL_DIG_DEBUG_CTL: 1046 + case WCD938X_DIGITAL_DIG_DEBUG_EN: 1047 + case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: 1048 + case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: 1049 + case WCD938X_DIGITAL_SSP_DBG: 1050 + case WCD938X_DIGITAL_SPARE_0: 1051 + case WCD938X_DIGITAL_SPARE_1: 1052 + case WCD938X_DIGITAL_SPARE_2: 1053 + case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: 1054 + case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: 1055 + case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: 1056 + case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: 1057 + case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: 1058 + case WCD938X_DIGITAL_DEM_BYPASS_DATA0: 1059 + case WCD938X_DIGITAL_DEM_BYPASS_DATA1: 1060 + case WCD938X_DIGITAL_DEM_BYPASS_DATA2: 1061 + case WCD938X_DIGITAL_DEM_BYPASS_DATA3: 1062 + return true; 1063 + } 1064 + 1065 + return false; 1066 + } 1067 + 1068 + static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) 1069 + { 1070 + switch (reg) { 1071 + case WCD938X_ANA_MBHC_RESULT_1: 1072 + case WCD938X_ANA_MBHC_RESULT_2: 1073 + case WCD938X_ANA_MBHC_RESULT_3: 1074 + case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: 1075 + case WCD938X_TX_1_2_SAR2_ERR: 1076 + case WCD938X_TX_1_2_SAR1_ERR: 1077 + case WCD938X_TX_3_4_SAR4_ERR: 1078 + case WCD938X_TX_3_4_SAR3_ERR: 1079 + case WCD938X_HPH_L_STATUS: 1080 + case WCD938X_HPH_R_STATUS: 1081 + case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: 1082 + case WCD938X_EAR_STATUS_REG_1: 1083 + case WCD938X_EAR_STATUS_REG_2: 1084 + case WCD938X_MBHC_NEW_FSM_STATUS: 1085 + case WCD938X_MBHC_NEW_ADC_RESULT: 1086 + case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: 1087 + case WCD938X_AUX_INT_STATUS_REG: 1088 + case WCD938X_LDORXTX_INT_STATUS: 1089 + case WCD938X_DIGITAL_CHIP_ID0: 1090 + case WCD938X_DIGITAL_CHIP_ID1: 1091 + case WCD938X_DIGITAL_CHIP_ID2: 1092 + case WCD938X_DIGITAL_CHIP_ID3: 1093 + case WCD938X_DIGITAL_INTR_STATUS_0: 1094 + case WCD938X_DIGITAL_INTR_STATUS_1: 1095 + case WCD938X_DIGITAL_INTR_STATUS_2: 1096 + case WCD938X_DIGITAL_INTR_CLEAR_0: 1097 + case WCD938X_DIGITAL_INTR_CLEAR_1: 1098 + case WCD938X_DIGITAL_INTR_CLEAR_2: 1099 + case WCD938X_DIGITAL_SWR_HM_TEST_0: 1100 + case WCD938X_DIGITAL_SWR_HM_TEST_1: 1101 + case WCD938X_DIGITAL_EFUSE_T_DATA_0: 1102 + case WCD938X_DIGITAL_EFUSE_T_DATA_1: 1103 + case WCD938X_DIGITAL_PIN_STATUS_0: 1104 + case WCD938X_DIGITAL_PIN_STATUS_1: 1105 + case WCD938X_DIGITAL_MODE_STATUS_0: 1106 + case WCD938X_DIGITAL_MODE_STATUS_1: 1107 + case WCD938X_DIGITAL_EFUSE_REG_0: 1108 + case WCD938X_DIGITAL_EFUSE_REG_1: 1109 + case WCD938X_DIGITAL_EFUSE_REG_2: 1110 + case WCD938X_DIGITAL_EFUSE_REG_3: 1111 + case WCD938X_DIGITAL_EFUSE_REG_4: 1112 + case WCD938X_DIGITAL_EFUSE_REG_5: 1113 + case WCD938X_DIGITAL_EFUSE_REG_6: 1114 + case WCD938X_DIGITAL_EFUSE_REG_7: 1115 + case WCD938X_DIGITAL_EFUSE_REG_8: 1116 + case WCD938X_DIGITAL_EFUSE_REG_9: 1117 + case WCD938X_DIGITAL_EFUSE_REG_10: 1118 + case WCD938X_DIGITAL_EFUSE_REG_11: 1119 + case WCD938X_DIGITAL_EFUSE_REG_12: 1120 + case WCD938X_DIGITAL_EFUSE_REG_13: 1121 + case WCD938X_DIGITAL_EFUSE_REG_14: 1122 + case WCD938X_DIGITAL_EFUSE_REG_15: 1123 + case WCD938X_DIGITAL_EFUSE_REG_16: 1124 + case WCD938X_DIGITAL_EFUSE_REG_17: 1125 + case WCD938X_DIGITAL_EFUSE_REG_18: 1126 + case WCD938X_DIGITAL_EFUSE_REG_19: 1127 + case WCD938X_DIGITAL_EFUSE_REG_20: 1128 + case WCD938X_DIGITAL_EFUSE_REG_21: 1129 + case WCD938X_DIGITAL_EFUSE_REG_22: 1130 + case WCD938X_DIGITAL_EFUSE_REG_23: 1131 + case WCD938X_DIGITAL_EFUSE_REG_24: 1132 + case WCD938X_DIGITAL_EFUSE_REG_25: 1133 + case WCD938X_DIGITAL_EFUSE_REG_26: 1134 + case WCD938X_DIGITAL_EFUSE_REG_27: 1135 + case WCD938X_DIGITAL_EFUSE_REG_28: 1136 + case WCD938X_DIGITAL_EFUSE_REG_29: 1137 + case WCD938X_DIGITAL_EFUSE_REG_30: 1138 + case WCD938X_DIGITAL_EFUSE_REG_31: 1139 + return true; 1140 + } 1141 + return false; 1142 + } 1143 + 1144 + static bool wcd938x_readable_register(struct device *dev, unsigned int reg) 1145 + { 1146 + bool ret; 1147 + 1148 + ret = wcd938x_readonly_register(dev, reg); 1149 + if (!ret) 1150 + return wcd938x_rdwr_register(dev, reg); 1151 + 1152 + return ret; 1153 + } 1154 + 1155 + static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) 1156 + { 1157 + return wcd938x_rdwr_register(dev, reg); 1158 + } 1159 + 1160 + static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) 1161 + { 1162 + if (reg <= WCD938X_BASE_ADDRESS) 1163 + return false; 1164 + 1165 + if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) 1166 + return true; 1167 + 1168 + if (wcd938x_readonly_register(dev, reg)) 1169 + return true; 1170 + 1171 + return false; 1172 + } 1173 + 1174 + static const struct regmap_config wcd938x_regmap_config = { 1175 + .name = "wcd938x_csr", 1176 + .reg_bits = 32, 1177 + .val_bits = 8, 1178 + .cache_type = REGCACHE_RBTREE, 1179 + .reg_defaults = wcd938x_defaults, 1180 + .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), 1181 + .max_register = WCD938X_MAX_REGISTER, 1182 + .readable_reg = wcd938x_readable_register, 1183 + .writeable_reg = wcd938x_writeable_register, 1184 + .volatile_reg = wcd938x_volatile_register, 1185 + .can_multi_write = true, 1186 + }; 201 1187 202 1188 static const struct sdw_slave_ops wcd9380_slave_ops = { 203 1189 .update_status = wcd9380_update_status, ··· 1263 261 wcd->ch_info = &wcd938x_sdw_rx_ch_info[0]; 1264 262 } 1265 263 264 + if (wcd->is_tx) { 265 + wcd->regmap = devm_regmap_init_sdw(pdev, &wcd938x_regmap_config); 266 + if (IS_ERR(wcd->regmap)) 267 + return dev_err_probe(dev, PTR_ERR(wcd->regmap), 268 + "Regmap init failed\n"); 269 + 270 + /* Start in cache-only until device is enumerated */ 271 + regcache_cache_only(wcd->regmap, true); 272 + }; 273 + 1266 274 pm_runtime_set_autosuspend_delay(dev, 3000); 1267 275 pm_runtime_use_autosuspend(dev); 1268 276 pm_runtime_mark_last_busy(dev); ··· 1290 278 1291 279 static int __maybe_unused wcd938x_sdw_runtime_suspend(struct device *dev) 1292 280 { 1293 - struct regmap *regmap = dev_get_regmap(dev, NULL); 281 + struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev); 1294 282 1295 - if (regmap) { 1296 - regcache_cache_only(regmap, true); 1297 - regcache_mark_dirty(regmap); 283 + if (wcd->regmap) { 284 + regcache_cache_only(wcd->regmap, true); 285 + regcache_mark_dirty(wcd->regmap); 1298 286 } 287 + 1299 288 return 0; 1300 289 } 1301 290 1302 291 static int __maybe_unused wcd938x_sdw_runtime_resume(struct device *dev) 1303 292 { 1304 - struct regmap *regmap = dev_get_regmap(dev, NULL); 293 + struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev); 1305 294 1306 - if (regmap) { 1307 - regcache_cache_only(regmap, false); 1308 - regcache_sync(regmap); 295 + if (wcd->regmap) { 296 + regcache_cache_only(wcd->regmap, false); 297 + regcache_sync(wcd->regmap); 1309 298 } 1310 299 1311 300 pm_runtime_mark_last_busy(dev);

+4 -999

sound/soc/codecs/wcd938x.c

··· 273 273 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 274 274 }; 275 275 276 - static const struct reg_default wcd938x_defaults[] = { 277 - {WCD938X_ANA_PAGE_REGISTER, 0x00}, 278 - {WCD938X_ANA_BIAS, 0x00}, 279 - {WCD938X_ANA_RX_SUPPLIES, 0x00}, 280 - {WCD938X_ANA_HPH, 0x0C}, 281 - {WCD938X_ANA_EAR, 0x00}, 282 - {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, 283 - {WCD938X_ANA_TX_CH1, 0x20}, 284 - {WCD938X_ANA_TX_CH2, 0x00}, 285 - {WCD938X_ANA_TX_CH3, 0x20}, 286 - {WCD938X_ANA_TX_CH4, 0x00}, 287 - {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, 288 - {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, 289 - {WCD938X_ANA_MBHC_MECH, 0x39}, 290 - {WCD938X_ANA_MBHC_ELECT, 0x08}, 291 - {WCD938X_ANA_MBHC_ZDET, 0x00}, 292 - {WCD938X_ANA_MBHC_RESULT_1, 0x00}, 293 - {WCD938X_ANA_MBHC_RESULT_2, 0x00}, 294 - {WCD938X_ANA_MBHC_RESULT_3, 0x00}, 295 - {WCD938X_ANA_MBHC_BTN0, 0x00}, 296 - {WCD938X_ANA_MBHC_BTN1, 0x10}, 297 - {WCD938X_ANA_MBHC_BTN2, 0x20}, 298 - {WCD938X_ANA_MBHC_BTN3, 0x30}, 299 - {WCD938X_ANA_MBHC_BTN4, 0x40}, 300 - {WCD938X_ANA_MBHC_BTN5, 0x50}, 301 - {WCD938X_ANA_MBHC_BTN6, 0x60}, 302 - {WCD938X_ANA_MBHC_BTN7, 0x70}, 303 - {WCD938X_ANA_MICB1, 0x10}, 304 - {WCD938X_ANA_MICB2, 0x10}, 305 - {WCD938X_ANA_MICB2_RAMP, 0x00}, 306 - {WCD938X_ANA_MICB3, 0x10}, 307 - {WCD938X_ANA_MICB4, 0x10}, 308 - {WCD938X_BIAS_CTL, 0x2A}, 309 - {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, 310 - {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, 311 - {WCD938X_LDOL_DISABLE_LDOL, 0x00}, 312 - {WCD938X_MBHC_CTL_CLK, 0x00}, 313 - {WCD938X_MBHC_CTL_ANA, 0x00}, 314 - {WCD938X_MBHC_CTL_SPARE_1, 0x00}, 315 - {WCD938X_MBHC_CTL_SPARE_2, 0x00}, 316 - {WCD938X_MBHC_CTL_BCS, 0x00}, 317 - {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, 318 - {WCD938X_MBHC_TEST_CTL, 0x00}, 319 - {WCD938X_LDOH_MODE, 0x2B}, 320 - {WCD938X_LDOH_BIAS, 0x68}, 321 - {WCD938X_LDOH_STB_LOADS, 0x00}, 322 - {WCD938X_LDOH_SLOWRAMP, 0x50}, 323 - {WCD938X_MICB1_TEST_CTL_1, 0x1A}, 324 - {WCD938X_MICB1_TEST_CTL_2, 0x00}, 325 - {WCD938X_MICB1_TEST_CTL_3, 0xA4}, 326 - {WCD938X_MICB2_TEST_CTL_1, 0x1A}, 327 - {WCD938X_MICB2_TEST_CTL_2, 0x00}, 328 - {WCD938X_MICB2_TEST_CTL_3, 0x24}, 329 - {WCD938X_MICB3_TEST_CTL_1, 0x1A}, 330 - {WCD938X_MICB3_TEST_CTL_2, 0x00}, 331 - {WCD938X_MICB3_TEST_CTL_3, 0xA4}, 332 - {WCD938X_MICB4_TEST_CTL_1, 0x1A}, 333 - {WCD938X_MICB4_TEST_CTL_2, 0x00}, 334 - {WCD938X_MICB4_TEST_CTL_3, 0xA4}, 335 - {WCD938X_TX_COM_ADC_VCM, 0x39}, 336 - {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, 337 - {WCD938X_TX_COM_SPARE1, 0x00}, 338 - {WCD938X_TX_COM_SPARE2, 0x00}, 339 - {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, 340 - {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, 341 - {WCD938X_TX_COM_SPARE3, 0x00}, 342 - {WCD938X_TX_COM_SPARE4, 0x00}, 343 - {WCD938X_TX_1_2_TEST_EN, 0xCC}, 344 - {WCD938X_TX_1_2_ADC_IB, 0xE9}, 345 - {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, 346 - {WCD938X_TX_1_2_TEST_CTL, 0x38}, 347 - {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, 348 - {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, 349 - {WCD938X_TX_1_2_SAR2_ERR, 0x00}, 350 - {WCD938X_TX_1_2_SAR1_ERR, 0x00}, 351 - {WCD938X_TX_3_4_TEST_EN, 0xCC}, 352 - {WCD938X_TX_3_4_ADC_IB, 0xE9}, 353 - {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, 354 - {WCD938X_TX_3_4_TEST_CTL, 0x38}, 355 - {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, 356 - {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, 357 - {WCD938X_TX_3_4_SAR4_ERR, 0x00}, 358 - {WCD938X_TX_3_4_SAR3_ERR, 0x00}, 359 - {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, 360 - {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, 361 - {WCD938X_TX_3_4_SPARE1, 0x00}, 362 - {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, 363 - {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, 364 - {WCD938X_TX_3_4_SPARE2, 0x00}, 365 - {WCD938X_CLASSH_MODE_1, 0x40}, 366 - {WCD938X_CLASSH_MODE_2, 0x3A}, 367 - {WCD938X_CLASSH_MODE_3, 0x00}, 368 - {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, 369 - {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, 370 - {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, 371 - {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, 372 - {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, 373 - {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, 374 - {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, 375 - {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, 376 - {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, 377 - {WCD938X_CLASSH_SPARE, 0x00}, 378 - {WCD938X_FLYBACK_EN, 0x4E}, 379 - {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, 380 - {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, 381 - {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, 382 - {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, 383 - {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, 384 - {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, 385 - {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, 386 - {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, 387 - {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, 388 - {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, 389 - {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, 390 - {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, 391 - {WCD938X_FLYBACK_CTRL_1, 0x65}, 392 - {WCD938X_FLYBACK_TEST_CTL, 0x00}, 393 - {WCD938X_RX_AUX_SW_CTL, 0x00}, 394 - {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, 395 - {WCD938X_RX_TIMER_DIV, 0x32}, 396 - {WCD938X_RX_OCP_CTL, 0x1F}, 397 - {WCD938X_RX_OCP_COUNT, 0x77}, 398 - {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, 399 - {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, 400 - {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, 401 - {WCD938X_RX_BIAS_HPH_PA, 0xAA}, 402 - {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, 403 - {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, 404 - {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, 405 - {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, 406 - {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, 407 - {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, 408 - {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, 409 - {WCD938X_RX_BIAS_MISC, 0x00}, 410 - {WCD938X_RX_BIAS_BUCK_RST, 0x08}, 411 - {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, 412 - {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, 413 - {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, 414 - {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, 415 - {WCD938X_HPH_L_STATUS, 0x04}, 416 - {WCD938X_HPH_R_STATUS, 0x04}, 417 - {WCD938X_HPH_CNP_EN, 0x80}, 418 - {WCD938X_HPH_CNP_WG_CTL, 0x9A}, 419 - {WCD938X_HPH_CNP_WG_TIME, 0x14}, 420 - {WCD938X_HPH_OCP_CTL, 0x28}, 421 - {WCD938X_HPH_AUTO_CHOP, 0x16}, 422 - {WCD938X_HPH_CHOP_CTL, 0x83}, 423 - {WCD938X_HPH_PA_CTL1, 0x46}, 424 - {WCD938X_HPH_PA_CTL2, 0x50}, 425 - {WCD938X_HPH_L_EN, 0x80}, 426 - {WCD938X_HPH_L_TEST, 0xE0}, 427 - {WCD938X_HPH_L_ATEST, 0x50}, 428 - {WCD938X_HPH_R_EN, 0x80}, 429 - {WCD938X_HPH_R_TEST, 0xE0}, 430 - {WCD938X_HPH_R_ATEST, 0x54}, 431 - {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, 432 - {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, 433 - {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, 434 - {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, 435 - {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, 436 - {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, 437 - {WCD938X_HPH_L_DAC_CTL, 0x20}, 438 - {WCD938X_HPH_R_DAC_CTL, 0x20}, 439 - {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, 440 - {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, 441 - {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, 442 - {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, 443 - {WCD938X_EAR_EAR_EN_REG, 0x22}, 444 - {WCD938X_EAR_EAR_PA_CON, 0x44}, 445 - {WCD938X_EAR_EAR_SP_CON, 0xDB}, 446 - {WCD938X_EAR_EAR_DAC_CON, 0x80}, 447 - {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, 448 - {WCD938X_EAR_TEST_CTL, 0x00}, 449 - {WCD938X_EAR_STATUS_REG_1, 0x00}, 450 - {WCD938X_EAR_STATUS_REG_2, 0x08}, 451 - {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, 452 - {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, 453 - {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, 454 - {WCD938X_SLEEP_CTL, 0x16}, 455 - {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, 456 - {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, 457 - {WCD938X_MBHC_NEW_CTL_1, 0x02}, 458 - {WCD938X_MBHC_NEW_CTL_2, 0x05}, 459 - {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, 460 - {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, 461 - {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, 462 - {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, 463 - {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, 464 - {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, 465 - {WCD938X_AUX_AUXPA, 0x00}, 466 - {WCD938X_LDORXTX_MODE, 0x0C}, 467 - {WCD938X_LDORXTX_CONFIG, 0x10}, 468 - {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, 469 - {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, 470 - {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, 471 - {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, 472 - {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, 473 - {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, 474 - {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, 475 - {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, 476 - {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, 477 - {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, 478 - {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, 479 - {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, 480 - {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, 481 - {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, 482 - {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, 483 - {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, 484 - {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, 485 - {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, 486 - {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, 487 - {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, 488 - {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, 489 - {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, 490 - {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, 491 - {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, 492 - {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, 493 - {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, 494 - {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, 495 - {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, 496 - {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, 497 - {WCD938X_AUX_INT_EN_REG, 0x00}, 498 - {WCD938X_AUX_INT_PA_CTRL, 0x06}, 499 - {WCD938X_AUX_INT_SP_CTRL, 0xD2}, 500 - {WCD938X_AUX_INT_DAC_CTRL, 0x80}, 501 - {WCD938X_AUX_INT_CLK_CTRL, 0x50}, 502 - {WCD938X_AUX_INT_TEST_CTRL, 0x00}, 503 - {WCD938X_AUX_INT_STATUS_REG, 0x00}, 504 - {WCD938X_AUX_INT_MISC, 0x00}, 505 - {WCD938X_LDORXTX_INT_BIAS, 0x6E}, 506 - {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, 507 - {WCD938X_LDORXTX_INT_TEST0, 0x1C}, 508 - {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, 509 - {WCD938X_LDORXTX_INT_TEST1, 0x1F}, 510 - {WCD938X_LDORXTX_INT_STATUS, 0x00}, 511 - {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, 512 - {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, 513 - {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, 514 - {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, 515 - {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, 516 - {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, 517 - {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, 518 - {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, 519 - {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, 520 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, 521 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, 522 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, 523 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, 524 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, 525 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, 526 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, 527 - {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, 528 - {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, 529 - {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, 530 - {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, 531 - {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, 532 - {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, 533 - {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, 534 - {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, 535 - {WCD938X_DIGITAL_CHIP_ID0, 0x00}, 536 - {WCD938X_DIGITAL_CHIP_ID1, 0x00}, 537 - {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, 538 - {WCD938X_DIGITAL_CHIP_ID3, 0x01}, 539 - {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, 540 - {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, 541 - {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, 542 - {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, 543 - {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, 544 - {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, 545 - {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, 546 - {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, 547 - {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, 548 - {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, 549 - {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, 550 - {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, 551 - {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, 552 - {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, 553 - {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, 554 - {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, 555 - {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, 556 - {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, 557 - {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, 558 - {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, 559 - {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, 560 - {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, 561 - {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, 562 - {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, 563 - {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, 564 - {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, 565 - {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, 566 - {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, 567 - {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, 568 - {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, 569 - {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, 570 - {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, 571 - {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, 572 - {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, 573 - {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, 574 - {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, 575 - {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, 576 - {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, 577 - {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, 578 - {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, 579 - {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, 580 - {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, 581 - {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, 582 - {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, 583 - {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, 584 - {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, 585 - {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, 586 - {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, 587 - {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, 588 - {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, 589 - {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, 590 - {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, 591 - {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, 592 - {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, 593 - {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, 594 - {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, 595 - {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, 596 - {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, 597 - {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, 598 - {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, 599 - {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, 600 - {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, 601 - {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, 602 - {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, 603 - {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, 604 - {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, 605 - {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, 606 - {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, 607 - {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, 608 - {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, 609 - {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, 610 - {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, 611 - {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, 612 - {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, 613 - {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, 614 - {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, 615 - {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, 616 - {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, 617 - {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, 618 - {WCD938X_DIGITAL_CDC_RST, 0x00}, 619 - {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, 620 - {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, 621 - {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, 622 - {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, 623 - {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, 624 - {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, 625 - {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, 626 - {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, 627 - {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, 628 - {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, 629 - {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, 630 - {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, 631 - {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, 632 - {WCD938X_DIGITAL_INTR_MODE, 0x00}, 633 - {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, 634 - {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, 635 - {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, 636 - {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, 637 - {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, 638 - {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, 639 - {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, 640 - {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, 641 - {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, 642 - {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, 643 - {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, 644 - {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, 645 - {WCD938X_DIGITAL_INTR_SET_0, 0x00}, 646 - {WCD938X_DIGITAL_INTR_SET_1, 0x00}, 647 - {WCD938X_DIGITAL_INTR_SET_2, 0x00}, 648 - {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, 649 - {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, 650 - {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, 651 - {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, 652 - {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, 653 - {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, 654 - {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, 655 - {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, 656 - {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, 657 - {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, 658 - {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, 659 - {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, 660 - {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, 661 - {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, 662 - {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, 663 - {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, 664 - {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, 665 - {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, 666 - {WCD938X_DIGITAL_I2C_CTL, 0x00}, 667 - {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, 668 - {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, 669 - {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, 670 - {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, 671 - {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, 672 - {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, 673 - {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, 674 - {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, 675 - {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, 676 - {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, 677 - {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, 678 - {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, 679 - {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, 680 - {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, 681 - {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, 682 - {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, 683 - {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, 684 - {WCD938X_DIGITAL_GPIO_MODE, 0x00}, 685 - {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, 686 - {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, 687 - {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, 688 - {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, 689 - {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, 690 - {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, 691 - {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, 692 - {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, 693 - {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, 694 - {WCD938X_DIGITAL_SSP_DBG, 0x00}, 695 - {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, 696 - {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, 697 - {WCD938X_DIGITAL_SPARE_0, 0x00}, 698 - {WCD938X_DIGITAL_SPARE_1, 0x00}, 699 - {WCD938X_DIGITAL_SPARE_2, 0x00}, 700 - {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, 701 - {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, 702 - {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, 703 - {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, 704 - {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, 705 - {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, 706 - {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, 707 - {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, 708 - {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, 709 - {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, 710 - {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, 711 - {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, 712 - {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, 713 - {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, 714 - {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, 715 - {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, 716 - {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, 717 - {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, 718 - {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, 719 - {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, 720 - {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, 721 - {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, 722 - {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, 723 - {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, 724 - {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, 725 - {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, 726 - {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, 727 - {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, 728 - {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, 729 - {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, 730 - {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, 731 - {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, 732 - {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, 733 - {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, 734 - {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, 735 - {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, 736 - {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, 737 - {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, 738 - {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, 739 - {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, 740 - {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, 741 - }; 742 - 743 - static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) 744 - { 745 - switch (reg) { 746 - case WCD938X_ANA_PAGE_REGISTER: 747 - case WCD938X_ANA_BIAS: 748 - case WCD938X_ANA_RX_SUPPLIES: 749 - case WCD938X_ANA_HPH: 750 - case WCD938X_ANA_EAR: 751 - case WCD938X_ANA_EAR_COMPANDER_CTL: 752 - case WCD938X_ANA_TX_CH1: 753 - case WCD938X_ANA_TX_CH2: 754 - case WCD938X_ANA_TX_CH3: 755 - case WCD938X_ANA_TX_CH4: 756 - case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: 757 - case WCD938X_ANA_MICB3_DSP_EN_LOGIC: 758 - case WCD938X_ANA_MBHC_MECH: 759 - case WCD938X_ANA_MBHC_ELECT: 760 - case WCD938X_ANA_MBHC_ZDET: 761 - case WCD938X_ANA_MBHC_BTN0: 762 - case WCD938X_ANA_MBHC_BTN1: 763 - case WCD938X_ANA_MBHC_BTN2: 764 - case WCD938X_ANA_MBHC_BTN3: 765 - case WCD938X_ANA_MBHC_BTN4: 766 - case WCD938X_ANA_MBHC_BTN5: 767 - case WCD938X_ANA_MBHC_BTN6: 768 - case WCD938X_ANA_MBHC_BTN7: 769 - case WCD938X_ANA_MICB1: 770 - case WCD938X_ANA_MICB2: 771 - case WCD938X_ANA_MICB2_RAMP: 772 - case WCD938X_ANA_MICB3: 773 - case WCD938X_ANA_MICB4: 774 - case WCD938X_BIAS_CTL: 775 - case WCD938X_BIAS_VBG_FINE_ADJ: 776 - case WCD938X_LDOL_VDDCX_ADJUST: 777 - case WCD938X_LDOL_DISABLE_LDOL: 778 - case WCD938X_MBHC_CTL_CLK: 779 - case WCD938X_MBHC_CTL_ANA: 780 - case WCD938X_MBHC_CTL_SPARE_1: 781 - case WCD938X_MBHC_CTL_SPARE_2: 782 - case WCD938X_MBHC_CTL_BCS: 783 - case WCD938X_MBHC_TEST_CTL: 784 - case WCD938X_LDOH_MODE: 785 - case WCD938X_LDOH_BIAS: 786 - case WCD938X_LDOH_STB_LOADS: 787 - case WCD938X_LDOH_SLOWRAMP: 788 - case WCD938X_MICB1_TEST_CTL_1: 789 - case WCD938X_MICB1_TEST_CTL_2: 790 - case WCD938X_MICB1_TEST_CTL_3: 791 - case WCD938X_MICB2_TEST_CTL_1: 792 - case WCD938X_MICB2_TEST_CTL_2: 793 - case WCD938X_MICB2_TEST_CTL_3: 794 - case WCD938X_MICB3_TEST_CTL_1: 795 - case WCD938X_MICB3_TEST_CTL_2: 796 - case WCD938X_MICB3_TEST_CTL_3: 797 - case WCD938X_MICB4_TEST_CTL_1: 798 - case WCD938X_MICB4_TEST_CTL_2: 799 - case WCD938X_MICB4_TEST_CTL_3: 800 - case WCD938X_TX_COM_ADC_VCM: 801 - case WCD938X_TX_COM_BIAS_ATEST: 802 - case WCD938X_TX_COM_SPARE1: 803 - case WCD938X_TX_COM_SPARE2: 804 - case WCD938X_TX_COM_TXFE_DIV_CTL: 805 - case WCD938X_TX_COM_TXFE_DIV_START: 806 - case WCD938X_TX_COM_SPARE3: 807 - case WCD938X_TX_COM_SPARE4: 808 - case WCD938X_TX_1_2_TEST_EN: 809 - case WCD938X_TX_1_2_ADC_IB: 810 - case WCD938X_TX_1_2_ATEST_REFCTL: 811 - case WCD938X_TX_1_2_TEST_CTL: 812 - case WCD938X_TX_1_2_TEST_BLK_EN1: 813 - case WCD938X_TX_1_2_TXFE1_CLKDIV: 814 - case WCD938X_TX_3_4_TEST_EN: 815 - case WCD938X_TX_3_4_ADC_IB: 816 - case WCD938X_TX_3_4_ATEST_REFCTL: 817 - case WCD938X_TX_3_4_TEST_CTL: 818 - case WCD938X_TX_3_4_TEST_BLK_EN3: 819 - case WCD938X_TX_3_4_TXFE3_CLKDIV: 820 - case WCD938X_TX_3_4_TEST_BLK_EN2: 821 - case WCD938X_TX_3_4_TXFE2_CLKDIV: 822 - case WCD938X_TX_3_4_SPARE1: 823 - case WCD938X_TX_3_4_TEST_BLK_EN4: 824 - case WCD938X_TX_3_4_TXFE4_CLKDIV: 825 - case WCD938X_TX_3_4_SPARE2: 826 - case WCD938X_CLASSH_MODE_1: 827 - case WCD938X_CLASSH_MODE_2: 828 - case WCD938X_CLASSH_MODE_3: 829 - case WCD938X_CLASSH_CTRL_VCL_1: 830 - case WCD938X_CLASSH_CTRL_VCL_2: 831 - case WCD938X_CLASSH_CTRL_CCL_1: 832 - case WCD938X_CLASSH_CTRL_CCL_2: 833 - case WCD938X_CLASSH_CTRL_CCL_3: 834 - case WCD938X_CLASSH_CTRL_CCL_4: 835 - case WCD938X_CLASSH_CTRL_CCL_5: 836 - case WCD938X_CLASSH_BUCK_TMUX_A_D: 837 - case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: 838 - case WCD938X_CLASSH_SPARE: 839 - case WCD938X_FLYBACK_EN: 840 - case WCD938X_FLYBACK_VNEG_CTRL_1: 841 - case WCD938X_FLYBACK_VNEG_CTRL_2: 842 - case WCD938X_FLYBACK_VNEG_CTRL_3: 843 - case WCD938X_FLYBACK_VNEG_CTRL_4: 844 - case WCD938X_FLYBACK_VNEG_CTRL_5: 845 - case WCD938X_FLYBACK_VNEG_CTRL_6: 846 - case WCD938X_FLYBACK_VNEG_CTRL_7: 847 - case WCD938X_FLYBACK_VNEG_CTRL_8: 848 - case WCD938X_FLYBACK_VNEG_CTRL_9: 849 - case WCD938X_FLYBACK_VNEGDAC_CTRL_1: 850 - case WCD938X_FLYBACK_VNEGDAC_CTRL_2: 851 - case WCD938X_FLYBACK_VNEGDAC_CTRL_3: 852 - case WCD938X_FLYBACK_CTRL_1: 853 - case WCD938X_FLYBACK_TEST_CTL: 854 - case WCD938X_RX_AUX_SW_CTL: 855 - case WCD938X_RX_PA_AUX_IN_CONN: 856 - case WCD938X_RX_TIMER_DIV: 857 - case WCD938X_RX_OCP_CTL: 858 - case WCD938X_RX_OCP_COUNT: 859 - case WCD938X_RX_BIAS_EAR_DAC: 860 - case WCD938X_RX_BIAS_EAR_AMP: 861 - case WCD938X_RX_BIAS_HPH_LDO: 862 - case WCD938X_RX_BIAS_HPH_PA: 863 - case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: 864 - case WCD938X_RX_BIAS_HPH_RDAC_LDO: 865 - case WCD938X_RX_BIAS_HPH_CNP1: 866 - case WCD938X_RX_BIAS_HPH_LOWPOWER: 867 - case WCD938X_RX_BIAS_AUX_DAC: 868 - case WCD938X_RX_BIAS_AUX_AMP: 869 - case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: 870 - case WCD938X_RX_BIAS_MISC: 871 - case WCD938X_RX_BIAS_BUCK_RST: 872 - case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: 873 - case WCD938X_RX_BIAS_FLYB_ERRAMP: 874 - case WCD938X_RX_BIAS_FLYB_BUFF: 875 - case WCD938X_RX_BIAS_FLYB_MID_RST: 876 - case WCD938X_HPH_CNP_EN: 877 - case WCD938X_HPH_CNP_WG_CTL: 878 - case WCD938X_HPH_CNP_WG_TIME: 879 - case WCD938X_HPH_OCP_CTL: 880 - case WCD938X_HPH_AUTO_CHOP: 881 - case WCD938X_HPH_CHOP_CTL: 882 - case WCD938X_HPH_PA_CTL1: 883 - case WCD938X_HPH_PA_CTL2: 884 - case WCD938X_HPH_L_EN: 885 - case WCD938X_HPH_L_TEST: 886 - case WCD938X_HPH_L_ATEST: 887 - case WCD938X_HPH_R_EN: 888 - case WCD938X_HPH_R_TEST: 889 - case WCD938X_HPH_R_ATEST: 890 - case WCD938X_HPH_RDAC_CLK_CTL1: 891 - case WCD938X_HPH_RDAC_CLK_CTL2: 892 - case WCD938X_HPH_RDAC_LDO_CTL: 893 - case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: 894 - case WCD938X_HPH_REFBUFF_UHQA_CTL: 895 - case WCD938X_HPH_REFBUFF_LP_CTL: 896 - case WCD938X_HPH_L_DAC_CTL: 897 - case WCD938X_HPH_R_DAC_CTL: 898 - case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: 899 - case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: 900 - case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: 901 - case WCD938X_EAR_EAR_EN_REG: 902 - case WCD938X_EAR_EAR_PA_CON: 903 - case WCD938X_EAR_EAR_SP_CON: 904 - case WCD938X_EAR_EAR_DAC_CON: 905 - case WCD938X_EAR_EAR_CNP_FSM_CON: 906 - case WCD938X_EAR_TEST_CTL: 907 - case WCD938X_ANA_NEW_PAGE_REGISTER: 908 - case WCD938X_HPH_NEW_ANA_HPH2: 909 - case WCD938X_HPH_NEW_ANA_HPH3: 910 - case WCD938X_SLEEP_CTL: 911 - case WCD938X_SLEEP_WATCHDOG_CTL: 912 - case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: 913 - case WCD938X_MBHC_NEW_CTL_1: 914 - case WCD938X_MBHC_NEW_CTL_2: 915 - case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: 916 - case WCD938X_MBHC_NEW_ZDET_ANA_CTL: 917 - case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: 918 - case WCD938X_TX_NEW_AMIC_MUX_CFG: 919 - case WCD938X_AUX_AUXPA: 920 - case WCD938X_LDORXTX_MODE: 921 - case WCD938X_LDORXTX_CONFIG: 922 - case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: 923 - case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: 924 - case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: 925 - case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: 926 - case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: 927 - case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: 928 - case WCD938X_HPH_NEW_INT_PA_MISC1: 929 - case WCD938X_HPH_NEW_INT_PA_MISC2: 930 - case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: 931 - case WCD938X_HPH_NEW_INT_HPH_TIMER1: 932 - case WCD938X_HPH_NEW_INT_HPH_TIMER2: 933 - case WCD938X_HPH_NEW_INT_HPH_TIMER3: 934 - case WCD938X_HPH_NEW_INT_HPH_TIMER4: 935 - case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: 936 - case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: 937 - case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: 938 - case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: 939 - case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: 940 - case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: 941 - case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: 942 - case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: 943 - case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: 944 - case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: 945 - case WCD938X_MBHC_NEW_INT_SPARE_2: 946 - case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: 947 - case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: 948 - case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: 949 - case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: 950 - case WCD938X_AUX_INT_EN_REG: 951 - case WCD938X_AUX_INT_PA_CTRL: 952 - case WCD938X_AUX_INT_SP_CTRL: 953 - case WCD938X_AUX_INT_DAC_CTRL: 954 - case WCD938X_AUX_INT_CLK_CTRL: 955 - case WCD938X_AUX_INT_TEST_CTRL: 956 - case WCD938X_AUX_INT_MISC: 957 - case WCD938X_LDORXTX_INT_BIAS: 958 - case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: 959 - case WCD938X_LDORXTX_INT_TEST0: 960 - case WCD938X_LDORXTX_INT_STARTUP_TIMER: 961 - case WCD938X_LDORXTX_INT_TEST1: 962 - case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: 963 - case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: 964 - case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: 965 - case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: 966 - case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: 967 - case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: 968 - case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: 969 - case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: 970 - case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: 971 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: 972 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: 973 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: 974 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: 975 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: 976 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: 977 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: 978 - case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: 979 - case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: 980 - case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: 981 - case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: 982 - case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: 983 - case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: 984 - case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: 985 - case WCD938X_DIGITAL_PAGE_REGISTER: 986 - case WCD938X_DIGITAL_SWR_TX_CLK_RATE: 987 - case WCD938X_DIGITAL_CDC_RST_CTL: 988 - case WCD938X_DIGITAL_TOP_CLK_CFG: 989 - case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: 990 - case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: 991 - case WCD938X_DIGITAL_SWR_RST_EN: 992 - case WCD938X_DIGITAL_CDC_PATH_MODE: 993 - case WCD938X_DIGITAL_CDC_RX_RST: 994 - case WCD938X_DIGITAL_CDC_RX0_CTL: 995 - case WCD938X_DIGITAL_CDC_RX1_CTL: 996 - case WCD938X_DIGITAL_CDC_RX2_CTL: 997 - case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: 998 - case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: 999 - case WCD938X_DIGITAL_CDC_COMP_CTL_0: 1000 - case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: 1001 - case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: 1002 - case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: 1003 - case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: 1004 - case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: 1005 - case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: 1006 - case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: 1007 - case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: 1008 - case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: 1009 - case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: 1010 - case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: 1011 - case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: 1012 - case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: 1013 - case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: 1014 - case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: 1015 - case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: 1016 - case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: 1017 - case WCD938X_DIGITAL_CDC_HPH_DSM_R1: 1018 - case WCD938X_DIGITAL_CDC_HPH_DSM_R2: 1019 - case WCD938X_DIGITAL_CDC_HPH_DSM_R3: 1020 - case WCD938X_DIGITAL_CDC_HPH_DSM_R4: 1021 - case WCD938X_DIGITAL_CDC_HPH_DSM_R5: 1022 - case WCD938X_DIGITAL_CDC_HPH_DSM_R6: 1023 - case WCD938X_DIGITAL_CDC_HPH_DSM_R7: 1024 - case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: 1025 - case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: 1026 - case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: 1027 - case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: 1028 - case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: 1029 - case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: 1030 - case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: 1031 - case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: 1032 - case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: 1033 - case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: 1034 - case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: 1035 - case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: 1036 - case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: 1037 - case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: 1038 - case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: 1039 - case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: 1040 - case WCD938X_DIGITAL_CDC_AUX_DSM_R1: 1041 - case WCD938X_DIGITAL_CDC_AUX_DSM_R2: 1042 - case WCD938X_DIGITAL_CDC_AUX_DSM_R3: 1043 - case WCD938X_DIGITAL_CDC_AUX_DSM_R4: 1044 - case WCD938X_DIGITAL_CDC_AUX_DSM_R5: 1045 - case WCD938X_DIGITAL_CDC_AUX_DSM_R6: 1046 - case WCD938X_DIGITAL_CDC_AUX_DSM_R7: 1047 - case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: 1048 - case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: 1049 - case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: 1050 - case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: 1051 - case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: 1052 - case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: 1053 - case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: 1054 - case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: 1055 - case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: 1056 - case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: 1057 - case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: 1058 - case WCD938X_DIGITAL_CDC_SWR_CLH: 1059 - case WCD938X_DIGITAL_SWR_CLH_BYP: 1060 - case WCD938X_DIGITAL_CDC_TX0_CTL: 1061 - case WCD938X_DIGITAL_CDC_TX1_CTL: 1062 - case WCD938X_DIGITAL_CDC_TX2_CTL: 1063 - case WCD938X_DIGITAL_CDC_TX_RST: 1064 - case WCD938X_DIGITAL_CDC_REQ_CTL: 1065 - case WCD938X_DIGITAL_CDC_RST: 1066 - case WCD938X_DIGITAL_CDC_AMIC_CTL: 1067 - case WCD938X_DIGITAL_CDC_DMIC_CTL: 1068 - case WCD938X_DIGITAL_CDC_DMIC1_CTL: 1069 - case WCD938X_DIGITAL_CDC_DMIC2_CTL: 1070 - case WCD938X_DIGITAL_CDC_DMIC3_CTL: 1071 - case WCD938X_DIGITAL_CDC_DMIC4_CTL: 1072 - case WCD938X_DIGITAL_EFUSE_PRG_CTL: 1073 - case WCD938X_DIGITAL_EFUSE_CTL: 1074 - case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: 1075 - case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: 1076 - case WCD938X_DIGITAL_PDM_WD_CTL0: 1077 - case WCD938X_DIGITAL_PDM_WD_CTL1: 1078 - case WCD938X_DIGITAL_PDM_WD_CTL2: 1079 - case WCD938X_DIGITAL_INTR_MODE: 1080 - case WCD938X_DIGITAL_INTR_MASK_0: 1081 - case WCD938X_DIGITAL_INTR_MASK_1: 1082 - case WCD938X_DIGITAL_INTR_MASK_2: 1083 - case WCD938X_DIGITAL_INTR_CLEAR_0: 1084 - case WCD938X_DIGITAL_INTR_CLEAR_1: 1085 - case WCD938X_DIGITAL_INTR_CLEAR_2: 1086 - case WCD938X_DIGITAL_INTR_LEVEL_0: 1087 - case WCD938X_DIGITAL_INTR_LEVEL_1: 1088 - case WCD938X_DIGITAL_INTR_LEVEL_2: 1089 - case WCD938X_DIGITAL_INTR_SET_0: 1090 - case WCD938X_DIGITAL_INTR_SET_1: 1091 - case WCD938X_DIGITAL_INTR_SET_2: 1092 - case WCD938X_DIGITAL_INTR_TEST_0: 1093 - case WCD938X_DIGITAL_INTR_TEST_1: 1094 - case WCD938X_DIGITAL_INTR_TEST_2: 1095 - case WCD938X_DIGITAL_TX_MODE_DBG_EN: 1096 - case WCD938X_DIGITAL_TX_MODE_DBG_0_1: 1097 - case WCD938X_DIGITAL_TX_MODE_DBG_2_3: 1098 - case WCD938X_DIGITAL_LB_IN_SEL_CTL: 1099 - case WCD938X_DIGITAL_LOOP_BACK_MODE: 1100 - case WCD938X_DIGITAL_SWR_DAC_TEST: 1101 - case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: 1102 - case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: 1103 - case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: 1104 - case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: 1105 - case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: 1106 - case WCD938X_DIGITAL_PAD_CTL_SWR_0: 1107 - case WCD938X_DIGITAL_PAD_CTL_SWR_1: 1108 - case WCD938X_DIGITAL_I2C_CTL: 1109 - case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: 1110 - case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: 1111 - case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: 1112 - case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: 1113 - case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: 1114 - case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: 1115 - case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: 1116 - case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: 1117 - case WCD938X_DIGITAL_PAD_INP_DIS_0: 1118 - case WCD938X_DIGITAL_PAD_INP_DIS_1: 1119 - case WCD938X_DIGITAL_DRIVE_STRENGTH_0: 1120 - case WCD938X_DIGITAL_DRIVE_STRENGTH_1: 1121 - case WCD938X_DIGITAL_DRIVE_STRENGTH_2: 1122 - case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: 1123 - case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: 1124 - case WCD938X_DIGITAL_GPIO_MODE: 1125 - case WCD938X_DIGITAL_PIN_CTL_OE: 1126 - case WCD938X_DIGITAL_PIN_CTL_DATA_0: 1127 - case WCD938X_DIGITAL_PIN_CTL_DATA_1: 1128 - case WCD938X_DIGITAL_DIG_DEBUG_CTL: 1129 - case WCD938X_DIGITAL_DIG_DEBUG_EN: 1130 - case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: 1131 - case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: 1132 - case WCD938X_DIGITAL_SSP_DBG: 1133 - case WCD938X_DIGITAL_SPARE_0: 1134 - case WCD938X_DIGITAL_SPARE_1: 1135 - case WCD938X_DIGITAL_SPARE_2: 1136 - case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: 1137 - case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: 1138 - case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: 1139 - case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: 1140 - case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: 1141 - case WCD938X_DIGITAL_DEM_BYPASS_DATA0: 1142 - case WCD938X_DIGITAL_DEM_BYPASS_DATA1: 1143 - case WCD938X_DIGITAL_DEM_BYPASS_DATA2: 1144 - case WCD938X_DIGITAL_DEM_BYPASS_DATA3: 1145 - return true; 1146 - } 1147 - 1148 - return false; 1149 - } 1150 - 1151 - static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) 1152 - { 1153 - switch (reg) { 1154 - case WCD938X_ANA_MBHC_RESULT_1: 1155 - case WCD938X_ANA_MBHC_RESULT_2: 1156 - case WCD938X_ANA_MBHC_RESULT_3: 1157 - case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: 1158 - case WCD938X_TX_1_2_SAR2_ERR: 1159 - case WCD938X_TX_1_2_SAR1_ERR: 1160 - case WCD938X_TX_3_4_SAR4_ERR: 1161 - case WCD938X_TX_3_4_SAR3_ERR: 1162 - case WCD938X_HPH_L_STATUS: 1163 - case WCD938X_HPH_R_STATUS: 1164 - case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: 1165 - case WCD938X_EAR_STATUS_REG_1: 1166 - case WCD938X_EAR_STATUS_REG_2: 1167 - case WCD938X_MBHC_NEW_FSM_STATUS: 1168 - case WCD938X_MBHC_NEW_ADC_RESULT: 1169 - case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: 1170 - case WCD938X_AUX_INT_STATUS_REG: 1171 - case WCD938X_LDORXTX_INT_STATUS: 1172 - case WCD938X_DIGITAL_CHIP_ID0: 1173 - case WCD938X_DIGITAL_CHIP_ID1: 1174 - case WCD938X_DIGITAL_CHIP_ID2: 1175 - case WCD938X_DIGITAL_CHIP_ID3: 1176 - case WCD938X_DIGITAL_INTR_STATUS_0: 1177 - case WCD938X_DIGITAL_INTR_STATUS_1: 1178 - case WCD938X_DIGITAL_INTR_STATUS_2: 1179 - case WCD938X_DIGITAL_INTR_CLEAR_0: 1180 - case WCD938X_DIGITAL_INTR_CLEAR_1: 1181 - case WCD938X_DIGITAL_INTR_CLEAR_2: 1182 - case WCD938X_DIGITAL_SWR_HM_TEST_0: 1183 - case WCD938X_DIGITAL_SWR_HM_TEST_1: 1184 - case WCD938X_DIGITAL_EFUSE_T_DATA_0: 1185 - case WCD938X_DIGITAL_EFUSE_T_DATA_1: 1186 - case WCD938X_DIGITAL_PIN_STATUS_0: 1187 - case WCD938X_DIGITAL_PIN_STATUS_1: 1188 - case WCD938X_DIGITAL_MODE_STATUS_0: 1189 - case WCD938X_DIGITAL_MODE_STATUS_1: 1190 - case WCD938X_DIGITAL_EFUSE_REG_0: 1191 - case WCD938X_DIGITAL_EFUSE_REG_1: 1192 - case WCD938X_DIGITAL_EFUSE_REG_2: 1193 - case WCD938X_DIGITAL_EFUSE_REG_3: 1194 - case WCD938X_DIGITAL_EFUSE_REG_4: 1195 - case WCD938X_DIGITAL_EFUSE_REG_5: 1196 - case WCD938X_DIGITAL_EFUSE_REG_6: 1197 - case WCD938X_DIGITAL_EFUSE_REG_7: 1198 - case WCD938X_DIGITAL_EFUSE_REG_8: 1199 - case WCD938X_DIGITAL_EFUSE_REG_9: 1200 - case WCD938X_DIGITAL_EFUSE_REG_10: 1201 - case WCD938X_DIGITAL_EFUSE_REG_11: 1202 - case WCD938X_DIGITAL_EFUSE_REG_12: 1203 - case WCD938X_DIGITAL_EFUSE_REG_13: 1204 - case WCD938X_DIGITAL_EFUSE_REG_14: 1205 - case WCD938X_DIGITAL_EFUSE_REG_15: 1206 - case WCD938X_DIGITAL_EFUSE_REG_16: 1207 - case WCD938X_DIGITAL_EFUSE_REG_17: 1208 - case WCD938X_DIGITAL_EFUSE_REG_18: 1209 - case WCD938X_DIGITAL_EFUSE_REG_19: 1210 - case WCD938X_DIGITAL_EFUSE_REG_20: 1211 - case WCD938X_DIGITAL_EFUSE_REG_21: 1212 - case WCD938X_DIGITAL_EFUSE_REG_22: 1213 - case WCD938X_DIGITAL_EFUSE_REG_23: 1214 - case WCD938X_DIGITAL_EFUSE_REG_24: 1215 - case WCD938X_DIGITAL_EFUSE_REG_25: 1216 - case WCD938X_DIGITAL_EFUSE_REG_26: 1217 - case WCD938X_DIGITAL_EFUSE_REG_27: 1218 - case WCD938X_DIGITAL_EFUSE_REG_28: 1219 - case WCD938X_DIGITAL_EFUSE_REG_29: 1220 - case WCD938X_DIGITAL_EFUSE_REG_30: 1221 - case WCD938X_DIGITAL_EFUSE_REG_31: 1222 - return true; 1223 - } 1224 - return false; 1225 - } 1226 - 1227 - static bool wcd938x_readable_register(struct device *dev, unsigned int reg) 1228 - { 1229 - bool ret; 1230 - 1231 - ret = wcd938x_readonly_register(dev, reg); 1232 - if (!ret) 1233 - return wcd938x_rdwr_register(dev, reg); 1234 - 1235 - return ret; 1236 - } 1237 - 1238 - static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) 1239 - { 1240 - return wcd938x_rdwr_register(dev, reg); 1241 - } 1242 - 1243 - static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) 1244 - { 1245 - if (reg <= WCD938X_BASE_ADDRESS) 1246 - return false; 1247 - 1248 - if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) 1249 - return true; 1250 - 1251 - if (wcd938x_readonly_register(dev, reg)) 1252 - return true; 1253 - 1254 - return false; 1255 - } 1256 - 1257 - static struct regmap_config wcd938x_regmap_config = { 1258 - .name = "wcd938x_csr", 1259 - .reg_bits = 32, 1260 - .val_bits = 8, 1261 - .cache_type = REGCACHE_RBTREE, 1262 - .reg_defaults = wcd938x_defaults, 1263 - .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), 1264 - .max_register = WCD938X_MAX_REGISTER, 1265 - .readable_reg = wcd938x_readable_register, 1266 - .writeable_reg = wcd938x_writeable_register, 1267 - .volatile_reg = wcd938x_volatile_register, 1268 - .can_multi_write = true, 1269 - }; 1270 - 1271 276 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 1272 277 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 1273 278 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), ··· 3410 4405 return -EINVAL; 3411 4406 } 3412 4407 3413 - wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config); 3414 - if (IS_ERR(wcd938x->regmap)) { 3415 - dev_err(dev, "%s: tx csr regmap not found\n", __func__); 3416 - return PTR_ERR(wcd938x->regmap); 4408 + wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL); 4409 + if (!wcd938x->regmap) { 4410 + dev_err(dev, "could not get TX device regmap\n"); 4411 + return -EINVAL; 3417 4412 } 3418 4413 3419 4414 ret = wcd938x_irq_init(wcd938x, dev);

+1

sound/soc/codecs/wcd938x.h

··· 663 663 bool is_tx; 664 664 struct wcd938x_priv *wcd938x; 665 665 struct irq_domain *slave_irq; 666 + struct regmap *regmap; 666 667 }; 667 668 668 669 #if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW)

+1 -1

sound/soc/intel/common/soc-acpi-intel-byt-match.c

··· 124 124 }; 125 125 126 126 static const struct snd_soc_acpi_codecs wm5102_comp_ids = { 127 - .num_codecs = 2, 127 + .num_codecs = 3, 128 128 .codecs = { "10WM5102", "WM510204", "WM510205"}, 129 129 }; 130 130

+26

sound/soc/intel/common/soc-acpi-intel-cht-match.c

··· 50 50 return mach; 51 51 } 52 52 53 + /* 54 + * Some tablets with Android factory OS have buggy DSDTs with an ESSX8316 device 55 + * in the ACPI tables. While they are not using an ESS8316 codec. These DSDTs 56 + * also have an ACPI device for the correct codec, ignore the ESSX8316. 57 + */ 58 + static const struct dmi_system_id cht_ess8316_not_present_table[] = { 59 + { 60 + /* Nextbook Ares 8A */ 61 + .matches = { 62 + DMI_MATCH(DMI_SYS_VENDOR, "Insyde"), 63 + DMI_MATCH(DMI_PRODUCT_NAME, "CherryTrail"), 64 + DMI_MATCH(DMI_BIOS_VERSION, "M882"), 65 + }, 66 + }, 67 + { } 68 + }; 69 + 70 + static struct snd_soc_acpi_mach *cht_ess8316_quirk(void *arg) 71 + { 72 + if (dmi_check_system(cht_ess8316_not_present_table)) 73 + return NULL; 74 + 75 + return arg; 76 + } 77 + 53 78 static const struct snd_soc_acpi_codecs rt5640_comp_ids = { 54 79 .num_codecs = 2, 55 80 .codecs = { "10EC5640", "10EC3276" }, ··· 138 113 .drv_name = "bytcht_es8316", 139 114 .fw_filename = "intel/fw_sst_22a8.bin", 140 115 .board = "bytcht_es8316", 116 + .machine_quirk = cht_ess8316_quirk, 141 117 .sof_tplg_filename = "sof-cht-es8316.tplg", 142 118 }, 143 119 /* some CHT-T platforms rely on RT5640, use Baytrail machine driver */

+1

sound/usb/caiaq/input.c

··· 804 804 805 805 default: 806 806 /* no input methods supported on this device */ 807 + ret = -EINVAL; 807 808 goto exit_free_idev; 808 809 } 809 810

+58

sound/usb/quirks-table.h

··· 3884 3884 } 3885 3885 }, 3886 3886 3887 + { 3888 + /* 3889 + * PIONEER DJ DDJ-800 3890 + * PCM is 6 channels out, 6 channels in @ 44.1 fixed 3891 + * The Feedback for the output is the input 3892 + */ 3893 + USB_DEVICE_VENDOR_SPEC(0x2b73, 0x0029), 3894 + .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { 3895 + .ifnum = QUIRK_ANY_INTERFACE, 3896 + .type = QUIRK_COMPOSITE, 3897 + .data = (const struct snd_usb_audio_quirk[]) { 3898 + { 3899 + .ifnum = 0, 3900 + .type = QUIRK_AUDIO_FIXED_ENDPOINT, 3901 + .data = &(const struct audioformat) { 3902 + .formats = SNDRV_PCM_FMTBIT_S24_3LE, 3903 + .channels = 6, 3904 + .iface = 0, 3905 + .altsetting = 1, 3906 + .altset_idx = 1, 3907 + .endpoint = 0x01, 3908 + .ep_attr = USB_ENDPOINT_XFER_ISOC| 3909 + USB_ENDPOINT_SYNC_ASYNC, 3910 + .rates = SNDRV_PCM_RATE_44100, 3911 + .rate_min = 44100, 3912 + .rate_max = 44100, 3913 + .nr_rates = 1, 3914 + .rate_table = (unsigned int[]) { 44100 } 3915 + } 3916 + }, 3917 + { 3918 + .ifnum = 0, 3919 + .type = QUIRK_AUDIO_FIXED_ENDPOINT, 3920 + .data = &(const struct audioformat) { 3921 + .formats = SNDRV_PCM_FMTBIT_S24_3LE, 3922 + .channels = 6, 3923 + .iface = 0, 3924 + .altsetting = 1, 3925 + .altset_idx = 1, 3926 + .endpoint = 0x82, 3927 + .ep_idx = 1, 3928 + .ep_attr = USB_ENDPOINT_XFER_ISOC| 3929 + USB_ENDPOINT_SYNC_ASYNC| 3930 + USB_ENDPOINT_USAGE_IMPLICIT_FB, 3931 + .rates = SNDRV_PCM_RATE_44100, 3932 + .rate_min = 44100, 3933 + .rate_max = 44100, 3934 + .nr_rates = 1, 3935 + .rate_table = (unsigned int[]) { 44100 } 3936 + } 3937 + }, 3938 + { 3939 + .ifnum = -1 3940 + } 3941 + } 3942 + } 3943 + }, 3944 + 3887 3945 /* 3888 3946 * MacroSilicon MS2100/MS2106 based AV capture cards 3889 3947 *