tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef __AMDGPU_MCA_H__
22#define __AMDGPU_MCA_H__
23
24#include "amdgpu_ras.h"
25
26#define MCA_MAX_REGS_COUNT (16)
27
28#define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
29#define MCA_REG__STATUS__VAL(x) MCA_REG_FIELD(x, 63, 63)
30#define MCA_REG__STATUS__OVERFLOW(x) MCA_REG_FIELD(x, 62, 62)
31#define MCA_REG__STATUS__UC(x) MCA_REG_FIELD(x, 61, 61)
32#define MCA_REG__STATUS__EN(x) MCA_REG_FIELD(x, 60, 60)
33#define MCA_REG__STATUS__MISCV(x) MCA_REG_FIELD(x, 59, 59)
34#define MCA_REG__STATUS__ADDRV(x) MCA_REG_FIELD(x, 58, 58)
35#define MCA_REG__STATUS__PCC(x) MCA_REG_FIELD(x, 57, 57)
36#define MCA_REG__STATUS__ERRCOREIDVAL(x) MCA_REG_FIELD(x, 56, 56)
37#define MCA_REG__STATUS__TCC(x) MCA_REG_FIELD(x, 55, 55)
38#define MCA_REG__STATUS__SYNDV(x) MCA_REG_FIELD(x, 53, 53)
39#define MCA_REG__STATUS__CECC(x) MCA_REG_FIELD(x, 46, 46)
40#define MCA_REG__STATUS__UECC(x) MCA_REG_FIELD(x, 45, 45)
41#define MCA_REG__STATUS__DEFERRED(x) MCA_REG_FIELD(x, 44, 44)
42#define MCA_REG__STATUS__POISON(x) MCA_REG_FIELD(x, 43, 43)
43#define MCA_REG__STATUS__SCRUB(x) MCA_REG_FIELD(x, 40, 40)
44#define MCA_REG__STATUS__ERRCOREID(x) MCA_REG_FIELD(x, 37, 32)
45#define MCA_REG__STATUS__ADDRLSB(x) MCA_REG_FIELD(x, 29, 24)
46#define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
47#define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
48
49#define MCA_REG__MISC0__ERRCNT(x) MCA_REG_FIELD(x, 43, 32)
50
51#define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0)
52
53enum amdgpu_mca_ip {
54 AMDGPU_MCA_IP_UNKNOW = -1,
55 AMDGPU_MCA_IP_PSP = 0,
56 AMDGPU_MCA_IP_SDMA,
57 AMDGPU_MCA_IP_GC,
58 AMDGPU_MCA_IP_SMU,
59 AMDGPU_MCA_IP_MP5,
60 AMDGPU_MCA_IP_UMC,
61 AMDGPU_MCA_IP_PCS_XGMI,
62 AMDGPU_MCA_IP_COUNT,
63};
64
65enum amdgpu_mca_error_type {
66 AMDGPU_MCA_ERROR_TYPE_UE = 0,
67 AMDGPU_MCA_ERROR_TYPE_CE,
68};
69
70struct amdgpu_mca_ras_block {
71 struct amdgpu_ras_block_object ras_block;
72};
73
74struct amdgpu_mca_ras {
75 struct ras_common_if *ras_if;
76 struct amdgpu_mca_ras_block *ras;
77};
78
79struct amdgpu_mca {
80 struct amdgpu_mca_ras mp0;
81 struct amdgpu_mca_ras mp1;
82 struct amdgpu_mca_ras mpio;
83 const struct amdgpu_mca_smu_funcs *mca_funcs;
84};
85
86enum mca_reg_idx {
87 MCA_REG_IDX_STATUS = 1,
88 MCA_REG_IDX_ADDR = 2,
89 MCA_REG_IDX_MISC0 = 3,
90 MCA_REG_IDX_IPID = 5,
91 MCA_REG_IDX_SYND = 6,
92 MCA_REG_IDX_COUNT = 16,
93};
94
95struct mca_bank_info {
96 int socket_id;
97 int aid;
98 int hwid;
99 int mcatype;
100};
101
102struct mca_bank_entry {
103 int idx;
104 enum amdgpu_mca_error_type type;
105 enum amdgpu_mca_ip ip;
106 struct mca_bank_info info;
107 uint64_t regs[MCA_MAX_REGS_COUNT];
108};
109
110struct mca_bank_node {
111 struct mca_bank_entry entry;
112 struct list_head node;
113};
114
115struct mca_bank_set {
116 int nr_entries;
117 struct list_head list;
118};
119
120struct amdgpu_mca_smu_funcs {
121 int max_ue_count;
122 int max_ce_count;
123 int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);
124 int (*mca_get_ras_mca_set)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
125 struct mca_bank_set *mca_set);
126 int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
127 struct mca_bank_entry *entry, uint32_t *count);
128 int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
129 uint32_t *count);
130 int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
131 int idx, struct mca_bank_entry *entry);
132};
133
134void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
135 uint64_t mc_status_addr,
136 unsigned long *error_count);
137
138void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
139 uint64_t mc_status_addr,
140 unsigned long *error_count);
141
142void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
143 uint64_t mc_status_addr);
144
145void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
146 uint64_t mc_status_addr,
147 void *ras_error_status);
148int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
149int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
150int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
151
152void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs);
153int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);
154int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count);
155int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
156 enum amdgpu_mca_error_type type, uint32_t *total);
157int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
158 enum amdgpu_mca_error_type type, uint32_t *count);
159int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
160 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
161int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
162 enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set);
163int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
164 int idx, struct mca_bank_entry *entry);
165
166void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);
167
168void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set);
169int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry);
170void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set);
171int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data);
172
173#endif