Linux kernel mirror (for testing)
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#include "amdgpu_res_cursor.h"
34
35#ifdef CONFIG_MMU_NOTIFIER
36#include <linux/mmu_notifier.h>
37#endif
38
39#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
40#define AMDGPU_BO_MAX_PLACEMENTS 3
41
42/* BO flag to indicate a KFD userptr BO */
43#define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63)
44
45#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
46#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
47
48struct amdgpu_bo_param {
49 unsigned long size;
50 int byte_align;
51 u32 bo_ptr_size;
52 u32 domain;
53 u32 preferred_domain;
54 u64 flags;
55 enum ttm_bo_type type;
56 bool no_wait_gpu;
57 struct dma_resv *resv;
58 void (*destroy)(struct ttm_buffer_object *bo);
59 /* xcp partition number plus 1, 0 means any partition */
60 int8_t xcp_id_plus1;
61};
62
63/* bo virtual addresses in a vm */
64struct amdgpu_bo_va_mapping {
65 struct amdgpu_bo_va *bo_va;
66 struct list_head list;
67 struct rb_node rb;
68 uint64_t start;
69 uint64_t last;
70 uint64_t __subtree_last;
71 uint64_t offset;
72 uint64_t flags;
73};
74
75/* User space allocated BO in a VM */
76struct amdgpu_bo_va {
77 struct amdgpu_vm_bo_base base;
78
79 /* protected by bo being reserved */
80 unsigned ref_count;
81
82 /* all other members protected by the VM PD being reserved */
83 struct dma_fence *last_pt_update;
84
85 /* mappings for this bo_va */
86 struct list_head invalids;
87 struct list_head valids;
88
89 /* If the mappings are cleared or filled */
90 bool cleared;
91
92 bool is_xgmi;
93};
94
95struct amdgpu_bo {
96 /* Protected by tbo.reserved */
97 u32 preferred_domains;
98 u32 allowed_domains;
99 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
100 struct ttm_placement placement;
101 struct ttm_buffer_object tbo;
102 struct ttm_bo_kmap_obj kmap;
103 u64 flags;
104 /* per VM structure for page tables and with virtual addresses */
105 struct amdgpu_vm_bo_base *vm_bo;
106 /* Constant after initialization */
107 struct amdgpu_bo *parent;
108
109#ifdef CONFIG_MMU_NOTIFIER
110 struct mmu_interval_notifier notifier;
111#endif
112 struct kgd_mem *kfd_bo;
113
114 /*
115 * For GPUs with spatial partitioning, xcp partition number, -1 means
116 * any partition. For other ASICs without spatial partition, always 0
117 * for memory accounting.
118 */
119 int8_t xcp_id;
120};
121
122struct amdgpu_bo_user {
123 struct amdgpu_bo bo;
124 u64 tiling_flags;
125 u64 metadata_flags;
126 void *metadata;
127 u32 metadata_size;
128
129};
130
131struct amdgpu_bo_vm {
132 struct amdgpu_bo bo;
133 struct amdgpu_bo *shadow;
134 struct list_head shadow_list;
135 struct amdgpu_vm_bo_base entries[];
136};
137
138struct amdgpu_mem_stats {
139 /* current VRAM usage, includes visible VRAM */
140 uint64_t vram;
141 /* current visible VRAM usage */
142 uint64_t visible_vram;
143 /* current GTT usage */
144 uint64_t gtt;
145 /* current system memory usage */
146 uint64_t cpu;
147 /* sum of evicted buffers, includes visible VRAM */
148 uint64_t evicted_vram;
149 /* sum of evicted buffers due to CPU access */
150 uint64_t evicted_visible_vram;
151 /* how much userspace asked for, includes vis.VRAM */
152 uint64_t requested_vram;
153 /* how much userspace asked for */
154 uint64_t requested_visible_vram;
155 /* how much userspace asked for */
156 uint64_t requested_gtt;
157};
158
159static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
160{
161 return container_of(tbo, struct amdgpu_bo, tbo);
162}
163
164/**
165 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
166 * @mem_type: ttm memory type
167 *
168 * Returns corresponding domain of the ttm mem_type
169 */
170static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
171{
172 switch (mem_type) {
173 case TTM_PL_VRAM:
174 return AMDGPU_GEM_DOMAIN_VRAM;
175 case TTM_PL_TT:
176 return AMDGPU_GEM_DOMAIN_GTT;
177 case TTM_PL_SYSTEM:
178 return AMDGPU_GEM_DOMAIN_CPU;
179 case AMDGPU_PL_GDS:
180 return AMDGPU_GEM_DOMAIN_GDS;
181 case AMDGPU_PL_GWS:
182 return AMDGPU_GEM_DOMAIN_GWS;
183 case AMDGPU_PL_OA:
184 return AMDGPU_GEM_DOMAIN_OA;
185 default:
186 break;
187 }
188 return 0;
189}
190
191/**
192 * amdgpu_bo_reserve - reserve bo
193 * @bo: bo structure
194 * @no_intr: don't return -ERESTARTSYS on pending signal
195 *
196 * Returns:
197 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
198 * a signal. Release all buffer reservations and return to user-space.
199 */
200static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
201{
202 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
203 int r;
204
205 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
206 if (unlikely(r != 0)) {
207 if (r != -ERESTARTSYS)
208 dev_err(adev->dev, "%p reserve failed\n", bo);
209 return r;
210 }
211 return 0;
212}
213
214static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
215{
216 ttm_bo_unreserve(&bo->tbo);
217}
218
219static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
220{
221 return bo->tbo.base.size;
222}
223
224static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
225{
226 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
227}
228
229static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
230{
231 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
232}
233
234/**
235 * amdgpu_bo_mmap_offset - return mmap offset of bo
236 * @bo: amdgpu object for which we query the offset
237 *
238 * Returns mmap offset of the object.
239 */
240static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
241{
242 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
243}
244
245/**
246 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
247 */
248static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
249{
250 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
251 struct amdgpu_res_cursor cursor;
252
253 if (bo->tbo.resource->mem_type != TTM_PL_VRAM)
254 return false;
255
256 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
257 while (cursor.remaining) {
258 if (cursor.start < adev->gmc.visible_vram_size)
259 return true;
260
261 amdgpu_res_next(&cursor, cursor.size);
262 }
263
264 return false;
265}
266
267/**
268 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
269 */
270static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
271{
272 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
273}
274
275/**
276 * amdgpu_bo_encrypted - test if the BO is encrypted
277 * @bo: pointer to a buffer object
278 *
279 * Return true if the buffer object is encrypted, false otherwise.
280 */
281static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
282{
283 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
284}
285
286/**
287 * amdgpu_bo_shadowed - check if the BO is shadowed
288 *
289 * @bo: BO to be tested.
290 *
291 * Returns:
292 * NULL if not shadowed or else return a BO pointer.
293 */
294static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)
295{
296 if (bo->tbo.type == ttm_bo_type_kernel)
297 return to_amdgpu_bo_vm(bo)->shadow;
298
299 return NULL;
300}
301
302bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
303void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
304
305int amdgpu_bo_create(struct amdgpu_device *adev,
306 struct amdgpu_bo_param *bp,
307 struct amdgpu_bo **bo_ptr);
308int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
309 unsigned long size, int align,
310 u32 domain, struct amdgpu_bo **bo_ptr,
311 u64 *gpu_addr, void **cpu_addr);
312int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
313 unsigned long size, int align,
314 u32 domain, struct amdgpu_bo **bo_ptr,
315 u64 *gpu_addr, void **cpu_addr);
316int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
317 uint64_t offset, uint64_t size,
318 struct amdgpu_bo **bo_ptr, void **cpu_addr);
319int amdgpu_bo_create_user(struct amdgpu_device *adev,
320 struct amdgpu_bo_param *bp,
321 struct amdgpu_bo_user **ubo_ptr);
322int amdgpu_bo_create_vm(struct amdgpu_device *adev,
323 struct amdgpu_bo_param *bp,
324 struct amdgpu_bo_vm **ubo_ptr);
325void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
326 void **cpu_addr);
327int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
328void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
329void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
330struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
331void amdgpu_bo_unref(struct amdgpu_bo **bo);
332int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
333int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
334 u64 min_offset, u64 max_offset);
335void amdgpu_bo_unpin(struct amdgpu_bo *bo);
336int amdgpu_bo_init(struct amdgpu_device *adev);
337void amdgpu_bo_fini(struct amdgpu_device *adev);
338int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
339void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
340int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
341 uint32_t metadata_size, uint64_t flags);
342int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
343 size_t buffer_size, uint32_t *metadata_size,
344 uint64_t *flags);
345void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
346 bool evict,
347 struct ttm_resource *new_mem);
348void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
349vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
350void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
351 bool shared);
352int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
353 enum amdgpu_sync_mode sync_mode, void *owner,
354 bool intr);
355int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
356u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
357u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
358void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
359 struct amdgpu_mem_stats *stats);
360void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
361int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
362 struct dma_fence **fence);
363uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
364 uint32_t domain);
365
366/*
367 * sub allocation
368 */
369static inline struct amdgpu_sa_manager *
370to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
371{
372 return container_of(manager, struct amdgpu_sa_manager, base);
373}
374
375static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
376{
377 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
378 drm_suballoc_soffset(sa_bo);
379}
380
381static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
382{
383 return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
384 drm_suballoc_soffset(sa_bo);
385}
386
387int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
388 struct amdgpu_sa_manager *sa_manager,
389 unsigned size, u32 align, u32 domain);
390void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
391 struct amdgpu_sa_manager *sa_manager);
392int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
393 struct amdgpu_sa_manager *sa_manager);
394int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
395 struct drm_suballoc **sa_bo,
396 unsigned int size);
397void amdgpu_sa_bo_free(struct amdgpu_device *adev,
398 struct drm_suballoc **sa_bo,
399 struct dma_fence *fence);
400#if defined(CONFIG_DEBUG_FS)
401void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
402 struct seq_file *m);
403u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
404#endif
405void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
406
407bool amdgpu_bo_support_uswc(u64 bo_flags);
408
409
410#endif