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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 */
5#ifndef __PINCTRL_MSM_H__
6#define __PINCTRL_MSM_H__
7
8#include <linux/pm.h>
9#include <linux/types.h>
10
11struct platform_device;
12
13struct pinctrl_pin_desc;
14
15/**
16 * struct msm_function - a pinmux function
17 * @name: Name of the pinmux function.
18 * @groups: List of pingroups for this function.
19 * @ngroups: Number of entries in @groups.
20 */
21struct msm_function {
22 const char *name;
23 const char * const *groups;
24 unsigned ngroups;
25};
26
27/**
28 * struct msm_pingroup - Qualcomm pingroup definition
29 * @name: Name of the pingroup.
30 * @pins: A list of pins assigned to this pingroup.
31 * @npins: Number of entries in @pins.
32 * @funcs: A list of pinmux functions that can be selected for
33 * this group. The index of the selected function is used
34 * for programming the function selector.
35 * Entries should be indices into the groups list of the
36 * struct msm_pinctrl_soc_data.
37 * @ctl_reg: Offset of the register holding control bits for this group.
38 * @io_reg: Offset of the register holding input/output bits for this group.
39 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
40 * @intr_status_reg: Offset of the register holding the status bits for this group.
41 * @intr_target_reg: Offset of the register specifying routing of the interrupts
42 * from this group.
43 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
44 * @pull_bit: Offset in @ctl_reg for the bias configuration.
45 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
46 * @od_bit: Offset in @ctl_reg for controlling open drain.
47 * @oe_bit: Offset in @ctl_reg for controlling output enable.
48 * @in_bit: Offset in @io_reg for the input bit value.
49 * @out_bit: Offset in @io_reg for the output bit value.
50 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
51 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
52 * status.
53 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
54 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
55 * this gpio should get routed to the KPSS processor.
56 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
57 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
58 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
59 * @intr_detection_width: Number of bits used for specifying interrupt type,
60 * Should be 2 for SoCs that can detect both edges in hardware,
61 * otherwise 1.
62 */
63struct msm_pingroup {
64 const char *name;
65 const unsigned *pins;
66 unsigned npins;
67
68 unsigned *funcs;
69 unsigned nfuncs;
70
71 u32 ctl_reg;
72 u32 io_reg;
73 u32 intr_cfg_reg;
74 u32 intr_status_reg;
75 u32 intr_target_reg;
76
77 unsigned int tile:2;
78
79 unsigned mux_bit:5;
80
81 unsigned pull_bit:5;
82 unsigned drv_bit:5;
83 unsigned i2c_pull_bit:5;
84
85 unsigned od_bit:5;
86 unsigned egpio_enable:5;
87 unsigned egpio_present:5;
88 unsigned oe_bit:5;
89 unsigned in_bit:5;
90 unsigned out_bit:5;
91
92 unsigned intr_enable_bit:5;
93 unsigned intr_status_bit:5;
94 unsigned intr_ack_high:1;
95
96 unsigned intr_target_bit:5;
97 unsigned intr_target_kpss_val:5;
98 unsigned intr_raw_status_bit:5;
99 unsigned intr_polarity_bit:5;
100 unsigned intr_detection_bit:5;
101 unsigned intr_detection_width:5;
102};
103
104/**
105 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
106 * @gpio: The GPIOs that are wakeup capable
107 * @wakeirq: The interrupt at the always-on interrupt controller
108 */
109struct msm_gpio_wakeirq_map {
110 unsigned int gpio;
111 unsigned int wakeirq;
112};
113
114/**
115 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
116 * @pins: An array describing all pins the pin controller affects.
117 * @npins: The number of entries in @pins.
118 * @functions: An array describing all mux functions the SoC supports.
119 * @nfunctions: The number of entries in @functions.
120 * @groups: An array describing all pin groups the pin SoC supports.
121 * @ngroups: The numbmer of entries in @groups.
122 * @ngpio: The number of pingroups the driver should expose as GPIOs.
123 * @pull_no_keeper: The SoC does not support keeper bias.
124 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
125 * @nwakeirq_map: The number of entries in @wakeirq_map
126 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
127 * to be aware that their parent can't handle dual
128 * edge interrupts.
129 * @gpio_func: Which function number is GPIO (usually 0).
130 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
131 * hardware this is a mux 1-level above the TLMM, we'll treat
132 * it as if this is just another mux state of the TLMM. Since
133 * it doesn't really map to hardware, we'll allocate a virtual
134 * function number for eGPIO and any time we see that function
135 * number used we'll treat it as a request to mux away from
136 * our TLMM towards another owner.
137 */
138struct msm_pinctrl_soc_data {
139 const struct pinctrl_pin_desc *pins;
140 unsigned npins;
141 const struct msm_function *functions;
142 unsigned nfunctions;
143 const struct msm_pingroup *groups;
144 unsigned ngroups;
145 unsigned ngpios;
146 bool pull_no_keeper;
147 const char *const *tiles;
148 unsigned int ntiles;
149 const int *reserved_gpios;
150 const struct msm_gpio_wakeirq_map *wakeirq_map;
151 unsigned int nwakeirq_map;
152 bool wakeirq_dual_edge_errata;
153 unsigned int gpio_func;
154 unsigned int egpio_func;
155};
156
157extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
158
159int msm_pinctrl_probe(struct platform_device *pdev,
160 const struct msm_pinctrl_soc_data *soc_data);
161int msm_pinctrl_remove(struct platform_device *pdev);
162
163#endif