tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver
4 *
5 * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
6 */
7
8#include <linux/clk.h>
9#include <linux/device.h>
10#include <linux/interconnect-provider.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of_platform.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17
18#include <dt-bindings/interconnect/qcom,msm8996.h>
19
20#include "icc-rpm.h"
21#include "smd-rpm.h"
22#include "msm8996.h"
23
24static const char * const bus_mm_clocks[] = {
25 "bus",
26 "bus_a",
27 "iface"
28};
29
30static const char * const bus_a0noc_clocks[] = {
31 "aggre0_snoc_axi",
32 "aggre0_cnoc_ahb",
33 "aggre0_noc_mpu_cfg"
34};
35
36static const char * const bus_a2noc_clocks[] = {
37 "bus",
38 "bus_a",
39 "aggre2_ufs_axi",
40 "ufs_axi"
41};
42
43static const u16 mas_a0noc_common_links[] = {
44 MSM8996_SLAVE_A0NOC_SNOC
45};
46
47static struct qcom_icc_node mas_pcie_0 = {
48 .name = "mas_pcie_0",
49 .id = MSM8996_MASTER_PCIE_0,
50 .buswidth = 8,
51 .mas_rpm_id = 65,
52 .slv_rpm_id = -1,
53 .qos.ap_owned = true,
54 .qos.qos_mode = NOC_QOS_MODE_FIXED,
55 .qos.areq_prio = 1,
56 .qos.prio_level = 1,
57 .qos.qos_port = 0,
58 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
59 .links = mas_a0noc_common_links
60};
61
62static struct qcom_icc_node mas_pcie_1 = {
63 .name = "mas_pcie_1",
64 .id = MSM8996_MASTER_PCIE_1,
65 .buswidth = 8,
66 .mas_rpm_id = 66,
67 .slv_rpm_id = -1,
68 .qos.ap_owned = true,
69 .qos.qos_mode = NOC_QOS_MODE_FIXED,
70 .qos.areq_prio = 1,
71 .qos.prio_level = 1,
72 .qos.qos_port = 1,
73 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
74 .links = mas_a0noc_common_links
75};
76
77static struct qcom_icc_node mas_pcie_2 = {
78 .name = "mas_pcie_2",
79 .id = MSM8996_MASTER_PCIE_2,
80 .buswidth = 8,
81 .mas_rpm_id = 119,
82 .slv_rpm_id = -1,
83 .qos.ap_owned = true,
84 .qos.qos_mode = NOC_QOS_MODE_FIXED,
85 .qos.areq_prio = 1,
86 .qos.prio_level = 1,
87 .qos.qos_port = 2,
88 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
89 .links = mas_a0noc_common_links
90};
91
92static const u16 mas_a1noc_common_links[] = {
93 MSM8996_SLAVE_A1NOC_SNOC
94};
95
96static struct qcom_icc_node mas_cnoc_a1noc = {
97 .name = "mas_cnoc_a1noc",
98 .id = MSM8996_MASTER_CNOC_A1NOC,
99 .buswidth = 8,
100 .mas_rpm_id = 116,
101 .slv_rpm_id = -1,
102 .qos.ap_owned = true,
103 .qos.qos_mode = NOC_QOS_MODE_INVALID,
104 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
105 .links = mas_a1noc_common_links
106};
107
108static struct qcom_icc_node mas_crypto_c0 = {
109 .name = "mas_crypto_c0",
110 .id = MSM8996_MASTER_CRYPTO_CORE0,
111 .buswidth = 8,
112 .mas_rpm_id = 23,
113 .slv_rpm_id = -1,
114 .qos.ap_owned = true,
115 .qos.qos_mode = NOC_QOS_MODE_FIXED,
116 .qos.areq_prio = 1,
117 .qos.prio_level = 1,
118 .qos.qos_port = 0,
119 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
120 .links = mas_a1noc_common_links
121};
122
123static struct qcom_icc_node mas_pnoc_a1noc = {
124 .name = "mas_pnoc_a1noc",
125 .id = MSM8996_MASTER_PNOC_A1NOC,
126 .buswidth = 8,
127 .mas_rpm_id = 117,
128 .slv_rpm_id = -1,
129 .qos.ap_owned = false,
130 .qos.qos_mode = NOC_QOS_MODE_FIXED,
131 .qos.areq_prio = 0,
132 .qos.prio_level = 0,
133 .qos.qos_port = 1,
134 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
135 .links = mas_a1noc_common_links
136};
137
138static const u16 mas_a2noc_common_links[] = {
139 MSM8996_SLAVE_A2NOC_SNOC
140};
141
142static struct qcom_icc_node mas_usb3 = {
143 .name = "mas_usb3",
144 .id = MSM8996_MASTER_USB3,
145 .buswidth = 8,
146 .mas_rpm_id = 32,
147 .slv_rpm_id = -1,
148 .qos.ap_owned = true,
149 .qos.qos_mode = NOC_QOS_MODE_FIXED,
150 .qos.areq_prio = 1,
151 .qos.prio_level = 1,
152 .qos.qos_port = 3,
153 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
154 .links = mas_a2noc_common_links
155};
156
157static struct qcom_icc_node mas_ipa = {
158 .name = "mas_ipa",
159 .id = MSM8996_MASTER_IPA,
160 .buswidth = 8,
161 .mas_rpm_id = 59,
162 .slv_rpm_id = -1,
163 .qos.ap_owned = true,
164 .qos.qos_mode = NOC_QOS_MODE_FIXED,
165 .qos.areq_prio = 0,
166 .qos.prio_level = 0,
167 .qos.qos_port = -1,
168 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
169 .links = mas_a2noc_common_links
170};
171
172static struct qcom_icc_node mas_ufs = {
173 .name = "mas_ufs",
174 .id = MSM8996_MASTER_UFS,
175 .buswidth = 8,
176 .mas_rpm_id = 68,
177 .slv_rpm_id = -1,
178 .qos.ap_owned = true,
179 .qos.qos_mode = NOC_QOS_MODE_FIXED,
180 .qos.areq_prio = 1,
181 .qos.prio_level = 1,
182 .qos.qos_port = 2,
183 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
184 .links = mas_a2noc_common_links
185};
186
187static const u16 mas_apps_proc_links[] = {
188 MSM8996_SLAVE_BIMC_SNOC_1,
189 MSM8996_SLAVE_EBI_CH0,
190 MSM8996_SLAVE_BIMC_SNOC_0
191};
192
193static struct qcom_icc_node mas_apps_proc = {
194 .name = "mas_apps_proc",
195 .id = MSM8996_MASTER_AMPSS_M0,
196 .buswidth = 8,
197 .mas_rpm_id = 0,
198 .slv_rpm_id = -1,
199 .qos.ap_owned = true,
200 .qos.qos_mode = NOC_QOS_MODE_FIXED,
201 .qos.areq_prio = 0,
202 .qos.prio_level = 0,
203 .qos.qos_port = 0,
204 .num_links = ARRAY_SIZE(mas_apps_proc_links),
205 .links = mas_apps_proc_links
206};
207
208static const u16 mas_oxili_common_links[] = {
209 MSM8996_SLAVE_BIMC_SNOC_1,
210 MSM8996_SLAVE_HMSS_L3,
211 MSM8996_SLAVE_EBI_CH0,
212 MSM8996_SLAVE_BIMC_SNOC_0
213};
214
215static struct qcom_icc_node mas_oxili = {
216 .name = "mas_oxili",
217 .id = MSM8996_MASTER_GRAPHICS_3D,
218 .buswidth = 8,
219 .mas_rpm_id = 6,
220 .slv_rpm_id = -1,
221 .qos.ap_owned = true,
222 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
223 .qos.areq_prio = 0,
224 .qos.prio_level = 0,
225 .qos.qos_port = 1,
226 .num_links = ARRAY_SIZE(mas_oxili_common_links),
227 .links = mas_oxili_common_links
228};
229
230static struct qcom_icc_node mas_mnoc_bimc = {
231 .name = "mas_mnoc_bimc",
232 .id = MSM8996_MASTER_MNOC_BIMC,
233 .buswidth = 8,
234 .mas_rpm_id = 2,
235 .slv_rpm_id = -1,
236 .qos.ap_owned = true,
237 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
238 .qos.areq_prio = 0,
239 .qos.prio_level = 0,
240 .qos.qos_port = 2,
241 .num_links = ARRAY_SIZE(mas_oxili_common_links),
242 .links = mas_oxili_common_links
243};
244
245static const u16 mas_snoc_bimc_links[] = {
246 MSM8996_SLAVE_HMSS_L3,
247 MSM8996_SLAVE_EBI_CH0
248};
249
250static struct qcom_icc_node mas_snoc_bimc = {
251 .name = "mas_snoc_bimc",
252 .id = MSM8996_MASTER_SNOC_BIMC,
253 .buswidth = 8,
254 .mas_rpm_id = 3,
255 .slv_rpm_id = -1,
256 .qos.ap_owned = false,
257 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
258 .qos.areq_prio = 0,
259 .qos.prio_level = 0,
260 .qos.qos_port = -1,
261 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
262 .links = mas_snoc_bimc_links
263};
264
265static const u16 mas_snoc_cnoc_links[] = {
266 MSM8996_SLAVE_CLK_CTL,
267 MSM8996_SLAVE_RBCPR_CX,
268 MSM8996_SLAVE_A2NOC_SMMU_CFG,
269 MSM8996_SLAVE_A0NOC_MPU_CFG,
270 MSM8996_SLAVE_MESSAGE_RAM,
271 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
272 MSM8996_SLAVE_PCIE_0_CFG,
273 MSM8996_SLAVE_TLMM,
274 MSM8996_SLAVE_MPM,
275 MSM8996_SLAVE_A0NOC_SMMU_CFG,
276 MSM8996_SLAVE_EBI1_PHY_CFG,
277 MSM8996_SLAVE_BIMC_CFG,
278 MSM8996_SLAVE_PIMEM_CFG,
279 MSM8996_SLAVE_RBCPR_MX,
280 MSM8996_SLAVE_PRNG,
281 MSM8996_SLAVE_PCIE20_AHB2PHY,
282 MSM8996_SLAVE_A2NOC_MPU_CFG,
283 MSM8996_SLAVE_QDSS_CFG,
284 MSM8996_SLAVE_A2NOC_CFG,
285 MSM8996_SLAVE_A0NOC_CFG,
286 MSM8996_SLAVE_UFS_CFG,
287 MSM8996_SLAVE_CRYPTO_0_CFG,
288 MSM8996_SLAVE_PCIE_1_CFG,
289 MSM8996_SLAVE_SNOC_CFG,
290 MSM8996_SLAVE_SNOC_MPU_CFG,
291 MSM8996_SLAVE_A1NOC_MPU_CFG,
292 MSM8996_SLAVE_A1NOC_SMMU_CFG,
293 MSM8996_SLAVE_PCIE_2_CFG,
294 MSM8996_SLAVE_CNOC_MNOC_CFG,
295 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
296 MSM8996_SLAVE_PMIC_ARB,
297 MSM8996_SLAVE_IMEM_CFG,
298 MSM8996_SLAVE_A1NOC_CFG,
299 MSM8996_SLAVE_SSC_CFG,
300 MSM8996_SLAVE_TCSR,
301 MSM8996_SLAVE_LPASS_SMMU_CFG,
302 MSM8996_SLAVE_DCC_CFG
303};
304
305static struct qcom_icc_node mas_snoc_cnoc = {
306 .name = "mas_snoc_cnoc",
307 .id = MSM8996_MASTER_SNOC_CNOC,
308 .buswidth = 8,
309 .mas_rpm_id = 52,
310 .slv_rpm_id = -1,
311 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
312 .links = mas_snoc_cnoc_links
313};
314
315static const u16 mas_qdss_dap_links[] = {
316 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
317 MSM8996_SLAVE_RBCPR_CX,
318 MSM8996_SLAVE_A2NOC_SMMU_CFG,
319 MSM8996_SLAVE_A0NOC_MPU_CFG,
320 MSM8996_SLAVE_MESSAGE_RAM,
321 MSM8996_SLAVE_PCIE_0_CFG,
322 MSM8996_SLAVE_TLMM,
323 MSM8996_SLAVE_MPM,
324 MSM8996_SLAVE_A0NOC_SMMU_CFG,
325 MSM8996_SLAVE_EBI1_PHY_CFG,
326 MSM8996_SLAVE_BIMC_CFG,
327 MSM8996_SLAVE_PIMEM_CFG,
328 MSM8996_SLAVE_RBCPR_MX,
329 MSM8996_SLAVE_CLK_CTL,
330 MSM8996_SLAVE_PRNG,
331 MSM8996_SLAVE_PCIE20_AHB2PHY,
332 MSM8996_SLAVE_A2NOC_MPU_CFG,
333 MSM8996_SLAVE_QDSS_CFG,
334 MSM8996_SLAVE_A2NOC_CFG,
335 MSM8996_SLAVE_A0NOC_CFG,
336 MSM8996_SLAVE_UFS_CFG,
337 MSM8996_SLAVE_CRYPTO_0_CFG,
338 MSM8996_SLAVE_CNOC_A1NOC,
339 MSM8996_SLAVE_PCIE_1_CFG,
340 MSM8996_SLAVE_SNOC_CFG,
341 MSM8996_SLAVE_SNOC_MPU_CFG,
342 MSM8996_SLAVE_A1NOC_MPU_CFG,
343 MSM8996_SLAVE_A1NOC_SMMU_CFG,
344 MSM8996_SLAVE_PCIE_2_CFG,
345 MSM8996_SLAVE_CNOC_MNOC_CFG,
346 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
347 MSM8996_SLAVE_PMIC_ARB,
348 MSM8996_SLAVE_IMEM_CFG,
349 MSM8996_SLAVE_A1NOC_CFG,
350 MSM8996_SLAVE_SSC_CFG,
351 MSM8996_SLAVE_TCSR,
352 MSM8996_SLAVE_LPASS_SMMU_CFG,
353 MSM8996_SLAVE_DCC_CFG
354};
355
356static struct qcom_icc_node mas_qdss_dap = {
357 .name = "mas_qdss_dap",
358 .id = MSM8996_MASTER_QDSS_DAP,
359 .buswidth = 8,
360 .mas_rpm_id = 49,
361 .slv_rpm_id = -1,
362 .qos.ap_owned = true,
363 .qos.qos_mode = NOC_QOS_MODE_INVALID,
364 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
365 .links = mas_qdss_dap_links
366};
367
368static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
369 MSM8996_SLAVE_MMAGIC_CFG,
370 MSM8996_SLAVE_DSA_MPU_CFG,
371 MSM8996_SLAVE_MMSS_CLK_CFG,
372 MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
373 MSM8996_SLAVE_VENUS_CFG,
374 MSM8996_SLAVE_SMMU_VFE_CFG,
375 MSM8996_SLAVE_MISC_CFG,
376 MSM8996_SLAVE_SMMU_CPP_CFG,
377 MSM8996_SLAVE_GRAPHICS_3D_CFG,
378 MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
379 MSM8996_SLAVE_VENUS_THROTTLE_CFG,
380 MSM8996_SLAVE_CAMERA_CFG,
381 MSM8996_SLAVE_DISPLAY_CFG,
382 MSM8996_SLAVE_CPR_CFG,
383 MSM8996_SLAVE_SMMU_ROTATOR_CFG,
384 MSM8996_SLAVE_DSA_CFG,
385 MSM8996_SLAVE_SMMU_VENUS_CFG,
386 MSM8996_SLAVE_VMEM_CFG,
387 MSM8996_SLAVE_SMMU_JPEG_CFG,
388 MSM8996_SLAVE_SMMU_MDP_CFG,
389 MSM8996_SLAVE_MNOC_MPU_CFG
390};
391
392static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
393 .name = "mas_cnoc_mnoc_mmss_cfg",
394 .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG,
395 .buswidth = 8,
396 .mas_rpm_id = 4,
397 .slv_rpm_id = -1,
398 .qos.ap_owned = true,
399 .qos.qos_mode = NOC_QOS_MODE_INVALID,
400 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
401 .links = mas_cnoc_mnoc_mmss_cfg_links
402};
403
404static const u16 mas_cnoc_mnoc_cfg_links[] = {
405 MSM8996_SLAVE_SERVICE_MNOC
406};
407
408static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
409 .name = "mas_cnoc_mnoc_cfg",
410 .id = MSM8996_MASTER_CNOC_MNOC_CFG,
411 .buswidth = 8,
412 .mas_rpm_id = 5,
413 .slv_rpm_id = -1,
414 .qos.ap_owned = true,
415 .qos.qos_mode = NOC_QOS_MODE_INVALID,
416 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
417 .links = mas_cnoc_mnoc_cfg_links
418};
419
420static const u16 mas_mnoc_bimc_common_links[] = {
421 MSM8996_SLAVE_MNOC_BIMC
422};
423
424static struct qcom_icc_node mas_cpp = {
425 .name = "mas_cpp",
426 .id = MSM8996_MASTER_CPP,
427 .buswidth = 32,
428 .mas_rpm_id = 115,
429 .slv_rpm_id = -1,
430 .qos.ap_owned = true,
431 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
432 .qos.areq_prio = 0,
433 .qos.prio_level = 0,
434 .qos.qos_port = 5,
435 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
436 .links = mas_mnoc_bimc_common_links
437};
438
439static struct qcom_icc_node mas_jpeg = {
440 .name = "mas_jpeg",
441 .id = MSM8996_MASTER_JPEG,
442 .buswidth = 32,
443 .mas_rpm_id = 7,
444 .slv_rpm_id = -1,
445 .qos.ap_owned = true,
446 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
447 .qos.areq_prio = 0,
448 .qos.prio_level = 0,
449 .qos.qos_port = 7,
450 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
451 .links = mas_mnoc_bimc_common_links
452};
453
454static struct qcom_icc_node mas_mdp_p0 = {
455 .name = "mas_mdp_p0",
456 .id = MSM8996_MASTER_MDP_PORT0,
457 .buswidth = 32,
458 .mas_rpm_id = 8,
459 .slv_rpm_id = -1,
460 .qos.ap_owned = true,
461 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
462 .qos.areq_prio = 0,
463 .qos.prio_level = 0,
464 .qos.qos_port = 1,
465 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
466 .links = mas_mnoc_bimc_common_links
467};
468
469static struct qcom_icc_node mas_mdp_p1 = {
470 .name = "mas_mdp_p1",
471 .id = MSM8996_MASTER_MDP_PORT1,
472 .buswidth = 32,
473 .mas_rpm_id = 61,
474 .slv_rpm_id = -1,
475 .qos.ap_owned = true,
476 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
477 .qos.areq_prio = 0,
478 .qos.prio_level = 0,
479 .qos.qos_port = 2,
480 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
481 .links = mas_mnoc_bimc_common_links
482};
483
484static struct qcom_icc_node mas_rotator = {
485 .name = "mas_rotator",
486 .id = MSM8996_MASTER_ROTATOR,
487 .buswidth = 32,
488 .mas_rpm_id = 120,
489 .slv_rpm_id = -1,
490 .qos.ap_owned = true,
491 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
492 .qos.areq_prio = 0,
493 .qos.prio_level = 0,
494 .qos.qos_port = 0,
495 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
496 .links = mas_mnoc_bimc_common_links
497};
498
499static struct qcom_icc_node mas_venus = {
500 .name = "mas_venus",
501 .id = MSM8996_MASTER_VIDEO_P0,
502 .buswidth = 32,
503 .mas_rpm_id = 9,
504 .slv_rpm_id = -1,
505 .qos.ap_owned = true,
506 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
507 .qos.areq_prio = 0,
508 .qos.prio_level = 0,
509 .qos.qos_port = 3,
510 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
511 .links = mas_mnoc_bimc_common_links
512};
513
514static struct qcom_icc_node mas_vfe = {
515 .name = "mas_vfe",
516 .id = MSM8996_MASTER_VFE,
517 .buswidth = 32,
518 .mas_rpm_id = 11,
519 .slv_rpm_id = -1,
520 .qos.ap_owned = true,
521 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
522 .qos.areq_prio = 0,
523 .qos.prio_level = 0,
524 .qos.qos_port = 6,
525 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
526 .links = mas_mnoc_bimc_common_links
527};
528
529static const u16 mas_vmem_common_links[] = {
530 MSM8996_SLAVE_VMEM
531};
532
533static struct qcom_icc_node mas_snoc_vmem = {
534 .name = "mas_snoc_vmem",
535 .id = MSM8996_MASTER_SNOC_VMEM,
536 .buswidth = 32,
537 .mas_rpm_id = 114,
538 .slv_rpm_id = -1,
539 .qos.ap_owned = true,
540 .qos.qos_mode = NOC_QOS_MODE_INVALID,
541 .num_links = ARRAY_SIZE(mas_vmem_common_links),
542 .links = mas_vmem_common_links
543};
544
545static struct qcom_icc_node mas_venus_vmem = {
546 .name = "mas_venus_vmem",
547 .id = MSM8996_MASTER_VIDEO_P0_OCMEM,
548 .buswidth = 32,
549 .mas_rpm_id = 121,
550 .slv_rpm_id = -1,
551 .qos.ap_owned = true,
552 .qos.qos_mode = NOC_QOS_MODE_INVALID,
553 .num_links = ARRAY_SIZE(mas_vmem_common_links),
554 .links = mas_vmem_common_links
555};
556
557static const u16 mas_snoc_pnoc_links[] = {
558 MSM8996_SLAVE_BLSP_1,
559 MSM8996_SLAVE_BLSP_2,
560 MSM8996_SLAVE_SDCC_1,
561 MSM8996_SLAVE_SDCC_2,
562 MSM8996_SLAVE_SDCC_4,
563 MSM8996_SLAVE_TSIF,
564 MSM8996_SLAVE_PDM,
565 MSM8996_SLAVE_AHB2PHY
566};
567
568static struct qcom_icc_node mas_snoc_pnoc = {
569 .name = "mas_snoc_pnoc",
570 .id = MSM8996_MASTER_SNOC_PNOC,
571 .buswidth = 8,
572 .mas_rpm_id = 44,
573 .slv_rpm_id = -1,
574 .num_links = ARRAY_SIZE(mas_snoc_pnoc_links),
575 .links = mas_snoc_pnoc_links
576};
577
578static const u16 mas_pnoc_a1noc_common_links[] = {
579 MSM8996_SLAVE_PNOC_A1NOC
580};
581
582static struct qcom_icc_node mas_sdcc_1 = {
583 .name = "mas_sdcc_1",
584 .id = MSM8996_MASTER_SDCC_1,
585 .buswidth = 8,
586 .mas_rpm_id = 33,
587 .slv_rpm_id = -1,
588 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
589 .links = mas_pnoc_a1noc_common_links
590};
591
592static struct qcom_icc_node mas_sdcc_2 = {
593 .name = "mas_sdcc_2",
594 .id = MSM8996_MASTER_SDCC_2,
595 .buswidth = 8,
596 .mas_rpm_id = 35,
597 .slv_rpm_id = -1,
598 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
599 .links = mas_pnoc_a1noc_common_links
600};
601
602static struct qcom_icc_node mas_sdcc_4 = {
603 .name = "mas_sdcc_4",
604 .id = MSM8996_MASTER_SDCC_4,
605 .buswidth = 8,
606 .mas_rpm_id = 36,
607 .slv_rpm_id = -1,
608 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
609 .links = mas_pnoc_a1noc_common_links
610};
611
612static struct qcom_icc_node mas_usb_hs = {
613 .name = "mas_usb_hs",
614 .id = MSM8996_MASTER_USB_HS,
615 .buswidth = 8,
616 .mas_rpm_id = 42,
617 .slv_rpm_id = -1,
618 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
619 .links = mas_pnoc_a1noc_common_links
620};
621
622static struct qcom_icc_node mas_blsp_1 = {
623 .name = "mas_blsp_1",
624 .id = MSM8996_MASTER_BLSP_1,
625 .buswidth = 4,
626 .mas_rpm_id = 41,
627 .slv_rpm_id = -1,
628 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
629 .links = mas_pnoc_a1noc_common_links
630};
631
632static struct qcom_icc_node mas_blsp_2 = {
633 .name = "mas_blsp_2",
634 .id = MSM8996_MASTER_BLSP_2,
635 .buswidth = 4,
636 .mas_rpm_id = 39,
637 .slv_rpm_id = -1,
638 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
639 .links = mas_pnoc_a1noc_common_links
640};
641
642static struct qcom_icc_node mas_tsif = {
643 .name = "mas_tsif",
644 .id = MSM8996_MASTER_TSIF,
645 .buswidth = 4,
646 .mas_rpm_id = 37,
647 .slv_rpm_id = -1,
648 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
649 .links = mas_pnoc_a1noc_common_links
650};
651
652static const u16 mas_hmss_links[] = {
653 MSM8996_SLAVE_PIMEM,
654 MSM8996_SLAVE_OCIMEM,
655 MSM8996_SLAVE_SNOC_BIMC
656};
657
658static struct qcom_icc_node mas_hmss = {
659 .name = "mas_hmss",
660 .id = MSM8996_MASTER_HMSS,
661 .buswidth = 8,
662 .mas_rpm_id = 118,
663 .slv_rpm_id = -1,
664 .qos.ap_owned = true,
665 .qos.qos_mode = NOC_QOS_MODE_FIXED,
666 .qos.areq_prio = 1,
667 .qos.prio_level = 1,
668 .qos.qos_port = 4,
669 .num_links = ARRAY_SIZE(mas_hmss_links),
670 .links = mas_hmss_links
671};
672
673static const u16 mas_qdss_common_links[] = {
674 MSM8996_SLAVE_PIMEM,
675 MSM8996_SLAVE_USB3,
676 MSM8996_SLAVE_OCIMEM,
677 MSM8996_SLAVE_SNOC_BIMC,
678 MSM8996_SLAVE_SNOC_PNOC
679};
680
681static struct qcom_icc_node mas_qdss_bam = {
682 .name = "mas_qdss_bam",
683 .id = MSM8996_MASTER_QDSS_BAM,
684 .buswidth = 16,
685 .mas_rpm_id = 19,
686 .slv_rpm_id = -1,
687 .qos.ap_owned = true,
688 .qos.qos_mode = NOC_QOS_MODE_FIXED,
689 .qos.areq_prio = 1,
690 .qos.prio_level = 1,
691 .qos.qos_port = 2,
692 .num_links = ARRAY_SIZE(mas_qdss_common_links),
693 .links = mas_qdss_common_links
694};
695
696static const u16 mas_snoc_cfg_links[] = {
697 MSM8996_SLAVE_SERVICE_SNOC
698};
699
700static struct qcom_icc_node mas_snoc_cfg = {
701 .name = "mas_snoc_cfg",
702 .id = MSM8996_MASTER_SNOC_CFG,
703 .buswidth = 16,
704 .mas_rpm_id = 20,
705 .slv_rpm_id = -1,
706 .qos.ap_owned = true,
707 .qos.qos_mode = NOC_QOS_MODE_INVALID,
708 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
709 .links = mas_snoc_cfg_links
710};
711
712static const u16 mas_bimc_snoc_0_links[] = {
713 MSM8996_SLAVE_SNOC_VMEM,
714 MSM8996_SLAVE_USB3,
715 MSM8996_SLAVE_PIMEM,
716 MSM8996_SLAVE_LPASS,
717 MSM8996_SLAVE_APPSS,
718 MSM8996_SLAVE_SNOC_CNOC,
719 MSM8996_SLAVE_SNOC_PNOC,
720 MSM8996_SLAVE_OCIMEM,
721 MSM8996_SLAVE_QDSS_STM
722};
723
724static struct qcom_icc_node mas_bimc_snoc_0 = {
725 .name = "mas_bimc_snoc_0",
726 .id = MSM8996_MASTER_BIMC_SNOC_0,
727 .buswidth = 16,
728 .mas_rpm_id = 21,
729 .slv_rpm_id = -1,
730 .qos.ap_owned = true,
731 .qos.qos_mode = NOC_QOS_MODE_INVALID,
732 .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links),
733 .links = mas_bimc_snoc_0_links
734};
735
736static const u16 mas_bimc_snoc_1_links[] = {
737 MSM8996_SLAVE_PCIE_2,
738 MSM8996_SLAVE_PCIE_1,
739 MSM8996_SLAVE_PCIE_0
740};
741
742static struct qcom_icc_node mas_bimc_snoc_1 = {
743 .name = "mas_bimc_snoc_1",
744 .id = MSM8996_MASTER_BIMC_SNOC_1,
745 .buswidth = 16,
746 .mas_rpm_id = 109,
747 .slv_rpm_id = -1,
748 .qos.ap_owned = true,
749 .qos.qos_mode = NOC_QOS_MODE_INVALID,
750 .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links),
751 .links = mas_bimc_snoc_1_links
752};
753
754static const u16 mas_a0noc_snoc_links[] = {
755 MSM8996_SLAVE_SNOC_PNOC,
756 MSM8996_SLAVE_OCIMEM,
757 MSM8996_SLAVE_APPSS,
758 MSM8996_SLAVE_SNOC_BIMC,
759 MSM8996_SLAVE_PIMEM
760};
761
762static struct qcom_icc_node mas_a0noc_snoc = {
763 .name = "mas_a0noc_snoc",
764 .id = MSM8996_MASTER_A0NOC_SNOC,
765 .buswidth = 16,
766 .mas_rpm_id = 110,
767 .slv_rpm_id = -1,
768 .qos.ap_owned = true,
769 .qos.qos_mode = NOC_QOS_MODE_INVALID,
770 .num_links = ARRAY_SIZE(mas_a0noc_snoc_links),
771 .links = mas_a0noc_snoc_links
772};
773
774static const u16 mas_a1noc_snoc_links[] = {
775 MSM8996_SLAVE_SNOC_VMEM,
776 MSM8996_SLAVE_USB3,
777 MSM8996_SLAVE_PCIE_0,
778 MSM8996_SLAVE_PIMEM,
779 MSM8996_SLAVE_PCIE_2,
780 MSM8996_SLAVE_LPASS,
781 MSM8996_SLAVE_PCIE_1,
782 MSM8996_SLAVE_APPSS,
783 MSM8996_SLAVE_SNOC_BIMC,
784 MSM8996_SLAVE_SNOC_CNOC,
785 MSM8996_SLAVE_SNOC_PNOC,
786 MSM8996_SLAVE_OCIMEM,
787 MSM8996_SLAVE_QDSS_STM
788};
789
790static struct qcom_icc_node mas_a1noc_snoc = {
791 .name = "mas_a1noc_snoc",
792 .id = MSM8996_MASTER_A1NOC_SNOC,
793 .buswidth = 16,
794 .mas_rpm_id = 111,
795 .slv_rpm_id = -1,
796 .num_links = ARRAY_SIZE(mas_a1noc_snoc_links),
797 .links = mas_a1noc_snoc_links
798};
799
800static const u16 mas_a2noc_snoc_links[] = {
801 MSM8996_SLAVE_SNOC_VMEM,
802 MSM8996_SLAVE_USB3,
803 MSM8996_SLAVE_PCIE_1,
804 MSM8996_SLAVE_PIMEM,
805 MSM8996_SLAVE_PCIE_2,
806 MSM8996_SLAVE_QDSS_STM,
807 MSM8996_SLAVE_LPASS,
808 MSM8996_SLAVE_SNOC_BIMC,
809 MSM8996_SLAVE_SNOC_CNOC,
810 MSM8996_SLAVE_SNOC_PNOC,
811 MSM8996_SLAVE_OCIMEM,
812 MSM8996_SLAVE_PCIE_0
813};
814
815static struct qcom_icc_node mas_a2noc_snoc = {
816 .name = "mas_a2noc_snoc",
817 .id = MSM8996_MASTER_A2NOC_SNOC,
818 .buswidth = 16,
819 .mas_rpm_id = 112,
820 .slv_rpm_id = -1,
821 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
822 .links = mas_a2noc_snoc_links
823};
824
825static struct qcom_icc_node mas_qdss_etr = {
826 .name = "mas_qdss_etr",
827 .id = MSM8996_MASTER_QDSS_ETR,
828 .buswidth = 16,
829 .mas_rpm_id = 31,
830 .slv_rpm_id = -1,
831 .qos.ap_owned = true,
832 .qos.qos_mode = NOC_QOS_MODE_FIXED,
833 .qos.areq_prio = 1,
834 .qos.prio_level = 1,
835 .qos.qos_port = 3,
836 .num_links = ARRAY_SIZE(mas_qdss_common_links),
837 .links = mas_qdss_common_links
838};
839
840static const u16 slv_a0noc_snoc_links[] = {
841 MSM8996_MASTER_A0NOC_SNOC
842};
843
844static struct qcom_icc_node slv_a0noc_snoc = {
845 .name = "slv_a0noc_snoc",
846 .id = MSM8996_SLAVE_A0NOC_SNOC,
847 .buswidth = 8,
848 .mas_rpm_id = -1,
849 .slv_rpm_id = 141,
850 .qos.ap_owned = true,
851 .qos.qos_mode = NOC_QOS_MODE_INVALID,
852 .num_links = ARRAY_SIZE(slv_a0noc_snoc_links),
853 .links = slv_a0noc_snoc_links
854};
855
856static const u16 slv_a1noc_snoc_links[] = {
857 MSM8996_MASTER_A1NOC_SNOC
858};
859
860static struct qcom_icc_node slv_a1noc_snoc = {
861 .name = "slv_a1noc_snoc",
862 .id = MSM8996_SLAVE_A1NOC_SNOC,
863 .buswidth = 8,
864 .mas_rpm_id = -1,
865 .slv_rpm_id = 142,
866 .num_links = ARRAY_SIZE(slv_a1noc_snoc_links),
867 .links = slv_a1noc_snoc_links
868};
869
870static const u16 slv_a2noc_snoc_links[] = {
871 MSM8996_MASTER_A2NOC_SNOC
872};
873
874static struct qcom_icc_node slv_a2noc_snoc = {
875 .name = "slv_a2noc_snoc",
876 .id = MSM8996_SLAVE_A2NOC_SNOC,
877 .buswidth = 8,
878 .mas_rpm_id = -1,
879 .slv_rpm_id = 143,
880 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
881 .links = slv_a2noc_snoc_links
882};
883
884static struct qcom_icc_node slv_ebi = {
885 .name = "slv_ebi",
886 .id = MSM8996_SLAVE_EBI_CH0,
887 .buswidth = 8,
888 .mas_rpm_id = -1,
889 .slv_rpm_id = 0
890};
891
892static struct qcom_icc_node slv_hmss_l3 = {
893 .name = "slv_hmss_l3",
894 .id = MSM8996_SLAVE_HMSS_L3,
895 .buswidth = 8,
896 .mas_rpm_id = -1,
897 .slv_rpm_id = 160
898};
899
900static const u16 slv_bimc_snoc_0_links[] = {
901 MSM8996_MASTER_BIMC_SNOC_0
902};
903
904static struct qcom_icc_node slv_bimc_snoc_0 = {
905 .name = "slv_bimc_snoc_0",
906 .id = MSM8996_SLAVE_BIMC_SNOC_0,
907 .buswidth = 8,
908 .mas_rpm_id = -1,
909 .slv_rpm_id = 2,
910 .qos.ap_owned = true,
911 .qos.qos_mode = NOC_QOS_MODE_INVALID,
912 .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links),
913 .links = slv_bimc_snoc_0_links
914};
915
916static const u16 slv_bimc_snoc_1_links[] = {
917 MSM8996_MASTER_BIMC_SNOC_1
918};
919
920static struct qcom_icc_node slv_bimc_snoc_1 = {
921 .name = "slv_bimc_snoc_1",
922 .id = MSM8996_SLAVE_BIMC_SNOC_1,
923 .buswidth = 8,
924 .mas_rpm_id = -1,
925 .slv_rpm_id = 138,
926 .qos.ap_owned = true,
927 .qos.qos_mode = NOC_QOS_MODE_INVALID,
928 .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links),
929 .links = slv_bimc_snoc_1_links
930};
931
932static const u16 slv_cnoc_a1noc_links[] = {
933 MSM8996_MASTER_CNOC_A1NOC
934};
935
936static struct qcom_icc_node slv_cnoc_a1noc = {
937 .name = "slv_cnoc_a1noc",
938 .id = MSM8996_SLAVE_CNOC_A1NOC,
939 .buswidth = 4,
940 .mas_rpm_id = -1,
941 .slv_rpm_id = 75,
942 .qos.ap_owned = true,
943 .qos.qos_mode = NOC_QOS_MODE_INVALID,
944 .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links),
945 .links = slv_cnoc_a1noc_links
946};
947
948static struct qcom_icc_node slv_clk_ctl = {
949 .name = "slv_clk_ctl",
950 .id = MSM8996_SLAVE_CLK_CTL,
951 .buswidth = 4,
952 .mas_rpm_id = -1,
953 .slv_rpm_id = 47
954};
955
956static struct qcom_icc_node slv_tcsr = {
957 .name = "slv_tcsr",
958 .id = MSM8996_SLAVE_TCSR,
959 .buswidth = 4,
960 .mas_rpm_id = -1,
961 .slv_rpm_id = 50
962};
963
964static struct qcom_icc_node slv_tlmm = {
965 .name = "slv_tlmm",
966 .id = MSM8996_SLAVE_TLMM,
967 .buswidth = 4,
968 .mas_rpm_id = -1,
969 .slv_rpm_id = 51
970};
971
972static struct qcom_icc_node slv_crypto0_cfg = {
973 .name = "slv_crypto0_cfg",
974 .id = MSM8996_SLAVE_CRYPTO_0_CFG,
975 .buswidth = 4,
976 .mas_rpm_id = -1,
977 .slv_rpm_id = 52,
978 .qos.ap_owned = true,
979 .qos.qos_mode = NOC_QOS_MODE_INVALID
980};
981
982static struct qcom_icc_node slv_mpm = {
983 .name = "slv_mpm",
984 .id = MSM8996_SLAVE_MPM,
985 .buswidth = 4,
986 .mas_rpm_id = -1,
987 .slv_rpm_id = 62,
988 .qos.ap_owned = true,
989 .qos.qos_mode = NOC_QOS_MODE_INVALID
990};
991
992static struct qcom_icc_node slv_pimem_cfg = {
993 .name = "slv_pimem_cfg",
994 .id = MSM8996_SLAVE_PIMEM_CFG,
995 .buswidth = 4,
996 .mas_rpm_id = -1,
997 .slv_rpm_id = 167,
998 .qos.ap_owned = true,
999 .qos.qos_mode = NOC_QOS_MODE_INVALID
1000};
1001
1002static struct qcom_icc_node slv_imem_cfg = {
1003 .name = "slv_imem_cfg",
1004 .id = MSM8996_SLAVE_IMEM_CFG,
1005 .buswidth = 4,
1006 .mas_rpm_id = -1,
1007 .slv_rpm_id = 54,
1008 .qos.ap_owned = true,
1009 .qos.qos_mode = NOC_QOS_MODE_INVALID
1010};
1011
1012static struct qcom_icc_node slv_message_ram = {
1013 .name = "slv_message_ram",
1014 .id = MSM8996_SLAVE_MESSAGE_RAM,
1015 .buswidth = 4,
1016 .mas_rpm_id = -1,
1017 .slv_rpm_id = 55
1018};
1019
1020static struct qcom_icc_node slv_bimc_cfg = {
1021 .name = "slv_bimc_cfg",
1022 .id = MSM8996_SLAVE_BIMC_CFG,
1023 .buswidth = 4,
1024 .mas_rpm_id = -1,
1025 .slv_rpm_id = 56,
1026 .qos.ap_owned = true,
1027 .qos.qos_mode = NOC_QOS_MODE_INVALID
1028};
1029
1030static struct qcom_icc_node slv_pmic_arb = {
1031 .name = "slv_pmic_arb",
1032 .id = MSM8996_SLAVE_PMIC_ARB,
1033 .buswidth = 4,
1034 .mas_rpm_id = -1,
1035 .slv_rpm_id = 59
1036};
1037
1038static struct qcom_icc_node slv_prng = {
1039 .name = "slv_prng",
1040 .id = MSM8996_SLAVE_PRNG,
1041 .buswidth = 4,
1042 .mas_rpm_id = -1,
1043 .slv_rpm_id = 127,
1044 .qos.ap_owned = true,
1045 .qos.qos_mode = NOC_QOS_MODE_INVALID
1046};
1047
1048static struct qcom_icc_node slv_dcc_cfg = {
1049 .name = "slv_dcc_cfg",
1050 .id = MSM8996_SLAVE_DCC_CFG,
1051 .buswidth = 4,
1052 .mas_rpm_id = -1,
1053 .slv_rpm_id = 155,
1054 .qos.ap_owned = true,
1055 .qos.qos_mode = NOC_QOS_MODE_INVALID
1056};
1057
1058static struct qcom_icc_node slv_rbcpr_mx = {
1059 .name = "slv_rbcpr_mx",
1060 .id = MSM8996_SLAVE_RBCPR_MX,
1061 .buswidth = 4,
1062 .mas_rpm_id = -1,
1063 .slv_rpm_id = 170,
1064 .qos.ap_owned = true,
1065 .qos.qos_mode = NOC_QOS_MODE_INVALID
1066};
1067
1068static struct qcom_icc_node slv_qdss_cfg = {
1069 .name = "slv_qdss_cfg",
1070 .id = MSM8996_SLAVE_QDSS_CFG,
1071 .buswidth = 4,
1072 .mas_rpm_id = -1,
1073 .slv_rpm_id = 63,
1074 .qos.ap_owned = true,
1075 .qos.qos_mode = NOC_QOS_MODE_INVALID
1076};
1077
1078static struct qcom_icc_node slv_rbcpr_cx = {
1079 .name = "slv_rbcpr_cx",
1080 .id = MSM8996_SLAVE_RBCPR_CX,
1081 .buswidth = 4,
1082 .mas_rpm_id = -1,
1083 .slv_rpm_id = 169,
1084 .qos.ap_owned = true,
1085 .qos.qos_mode = NOC_QOS_MODE_INVALID
1086};
1087
1088static struct qcom_icc_node slv_cpu_apu_cfg = {
1089 .name = "slv_cpu_apu_cfg",
1090 .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
1091 .buswidth = 4,
1092 .mas_rpm_id = -1,
1093 .slv_rpm_id = 168,
1094 .qos.ap_owned = true,
1095 .qos.qos_mode = NOC_QOS_MODE_INVALID
1096};
1097
1098static const u16 slv_cnoc_mnoc_cfg_links[] = {
1099 MSM8996_MASTER_CNOC_MNOC_CFG
1100};
1101
1102static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
1103 .name = "slv_cnoc_mnoc_cfg",
1104 .id = MSM8996_SLAVE_CNOC_MNOC_CFG,
1105 .buswidth = 4,
1106 .mas_rpm_id = -1,
1107 .slv_rpm_id = 66,
1108 .qos.ap_owned = true,
1109 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1110 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
1111 .links = slv_cnoc_mnoc_cfg_links
1112};
1113
1114static struct qcom_icc_node slv_snoc_cfg = {
1115 .name = "slv_snoc_cfg",
1116 .id = MSM8996_SLAVE_SNOC_CFG,
1117 .buswidth = 4,
1118 .mas_rpm_id = -1,
1119 .slv_rpm_id = 70,
1120 .qos.ap_owned = true,
1121 .qos.qos_mode = NOC_QOS_MODE_INVALID
1122};
1123
1124static struct qcom_icc_node slv_snoc_mpu_cfg = {
1125 .name = "slv_snoc_mpu_cfg",
1126 .id = MSM8996_SLAVE_SNOC_MPU_CFG,
1127 .buswidth = 4,
1128 .mas_rpm_id = -1,
1129 .slv_rpm_id = 67,
1130 .qos.ap_owned = true,
1131 .qos.qos_mode = NOC_QOS_MODE_INVALID
1132};
1133
1134static struct qcom_icc_node slv_ebi1_phy_cfg = {
1135 .name = "slv_ebi1_phy_cfg",
1136 .id = MSM8996_SLAVE_EBI1_PHY_CFG,
1137 .buswidth = 4,
1138 .mas_rpm_id = -1,
1139 .slv_rpm_id = 73,
1140 .qos.ap_owned = true,
1141 .qos.qos_mode = NOC_QOS_MODE_INVALID
1142};
1143
1144static struct qcom_icc_node slv_a0noc_cfg = {
1145 .name = "slv_a0noc_cfg",
1146 .id = MSM8996_SLAVE_A0NOC_CFG,
1147 .buswidth = 4,
1148 .mas_rpm_id = -1,
1149 .slv_rpm_id = 144,
1150 .qos.ap_owned = true,
1151 .qos.qos_mode = NOC_QOS_MODE_INVALID
1152};
1153
1154static struct qcom_icc_node slv_pcie_1_cfg = {
1155 .name = "slv_pcie_1_cfg",
1156 .id = MSM8996_SLAVE_PCIE_1_CFG,
1157 .buswidth = 4,
1158 .mas_rpm_id = -1,
1159 .slv_rpm_id = 89,
1160 .qos.ap_owned = true,
1161 .qos.qos_mode = NOC_QOS_MODE_INVALID
1162};
1163
1164static struct qcom_icc_node slv_pcie_2_cfg = {
1165 .name = "slv_pcie_2_cfg",
1166 .id = MSM8996_SLAVE_PCIE_2_CFG,
1167 .buswidth = 4,
1168 .mas_rpm_id = -1,
1169 .slv_rpm_id = 165,
1170 .qos.ap_owned = true,
1171 .qos.qos_mode = NOC_QOS_MODE_INVALID
1172};
1173
1174static struct qcom_icc_node slv_pcie_0_cfg = {
1175 .name = "slv_pcie_0_cfg",
1176 .id = MSM8996_SLAVE_PCIE_0_CFG,
1177 .buswidth = 4,
1178 .mas_rpm_id = -1,
1179 .slv_rpm_id = 88,
1180 .qos.ap_owned = true,
1181 .qos.qos_mode = NOC_QOS_MODE_INVALID
1182};
1183
1184static struct qcom_icc_node slv_pcie20_ahb2phy = {
1185 .name = "slv_pcie20_ahb2phy",
1186 .id = MSM8996_SLAVE_PCIE20_AHB2PHY,
1187 .buswidth = 4,
1188 .mas_rpm_id = -1,
1189 .slv_rpm_id = 163,
1190 .qos.ap_owned = true,
1191 .qos.qos_mode = NOC_QOS_MODE_INVALID
1192};
1193
1194static struct qcom_icc_node slv_a0noc_mpu_cfg = {
1195 .name = "slv_a0noc_mpu_cfg",
1196 .id = MSM8996_SLAVE_A0NOC_MPU_CFG,
1197 .buswidth = 4,
1198 .mas_rpm_id = -1,
1199 .slv_rpm_id = 145,
1200 .qos.ap_owned = true,
1201 .qos.qos_mode = NOC_QOS_MODE_INVALID
1202};
1203
1204static struct qcom_icc_node slv_ufs_cfg = {
1205 .name = "slv_ufs_cfg",
1206 .id = MSM8996_SLAVE_UFS_CFG,
1207 .buswidth = 4,
1208 .mas_rpm_id = -1,
1209 .slv_rpm_id = 92,
1210 .qos.ap_owned = true,
1211 .qos.qos_mode = NOC_QOS_MODE_INVALID
1212};
1213
1214static struct qcom_icc_node slv_a1noc_cfg = {
1215 .name = "slv_a1noc_cfg",
1216 .id = MSM8996_SLAVE_A1NOC_CFG,
1217 .buswidth = 4,
1218 .mas_rpm_id = -1,
1219 .slv_rpm_id = 147,
1220 .qos.ap_owned = true,
1221 .qos.qos_mode = NOC_QOS_MODE_INVALID
1222};
1223
1224static struct qcom_icc_node slv_a1noc_mpu_cfg = {
1225 .name = "slv_a1noc_mpu_cfg",
1226 .id = MSM8996_SLAVE_A1NOC_MPU_CFG,
1227 .buswidth = 4,
1228 .mas_rpm_id = -1,
1229 .slv_rpm_id = 148,
1230 .qos.ap_owned = true,
1231 .qos.qos_mode = NOC_QOS_MODE_INVALID
1232};
1233
1234static struct qcom_icc_node slv_a2noc_cfg = {
1235 .name = "slv_a2noc_cfg",
1236 .id = MSM8996_SLAVE_A2NOC_CFG,
1237 .buswidth = 4,
1238 .mas_rpm_id = -1,
1239 .slv_rpm_id = 150,
1240 .qos.ap_owned = true,
1241 .qos.qos_mode = NOC_QOS_MODE_INVALID
1242};
1243
1244static struct qcom_icc_node slv_a2noc_mpu_cfg = {
1245 .name = "slv_a2noc_mpu_cfg",
1246 .id = MSM8996_SLAVE_A2NOC_MPU_CFG,
1247 .buswidth = 4,
1248 .mas_rpm_id = -1,
1249 .slv_rpm_id = 151,
1250 .qos.ap_owned = true,
1251 .qos.qos_mode = NOC_QOS_MODE_INVALID
1252};
1253
1254static struct qcom_icc_node slv_ssc_cfg = {
1255 .name = "slv_ssc_cfg",
1256 .id = MSM8996_SLAVE_SSC_CFG,
1257 .buswidth = 4,
1258 .mas_rpm_id = -1,
1259 .slv_rpm_id = 177,
1260 .qos.ap_owned = true,
1261 .qos.qos_mode = NOC_QOS_MODE_INVALID
1262};
1263
1264static struct qcom_icc_node slv_a0noc_smmu_cfg = {
1265 .name = "slv_a0noc_smmu_cfg",
1266 .id = MSM8996_SLAVE_A0NOC_SMMU_CFG,
1267 .buswidth = 8,
1268 .mas_rpm_id = -1,
1269 .slv_rpm_id = 146,
1270 .qos.ap_owned = true,
1271 .qos.qos_mode = NOC_QOS_MODE_INVALID
1272};
1273
1274static struct qcom_icc_node slv_a1noc_smmu_cfg = {
1275 .name = "slv_a1noc_smmu_cfg",
1276 .id = MSM8996_SLAVE_A1NOC_SMMU_CFG,
1277 .buswidth = 8,
1278 .mas_rpm_id = -1,
1279 .slv_rpm_id = 149,
1280 .qos.ap_owned = true,
1281 .qos.qos_mode = NOC_QOS_MODE_INVALID
1282};
1283
1284static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1285 .name = "slv_a2noc_smmu_cfg",
1286 .id = MSM8996_SLAVE_A2NOC_SMMU_CFG,
1287 .buswidth = 8,
1288 .mas_rpm_id = -1,
1289 .slv_rpm_id = 152,
1290 .qos.ap_owned = true,
1291 .qos.qos_mode = NOC_QOS_MODE_INVALID
1292};
1293
1294static struct qcom_icc_node slv_lpass_smmu_cfg = {
1295 .name = "slv_lpass_smmu_cfg",
1296 .id = MSM8996_SLAVE_LPASS_SMMU_CFG,
1297 .buswidth = 8,
1298 .mas_rpm_id = -1,
1299 .slv_rpm_id = 161,
1300 .qos.ap_owned = true,
1301 .qos.qos_mode = NOC_QOS_MODE_INVALID
1302};
1303
1304static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1305 MSM8996_MASTER_CNOC_MNOC_MMSS_CFG
1306};
1307
1308static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1309 .name = "slv_cnoc_mnoc_mmss_cfg",
1310 .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
1311 .buswidth = 8,
1312 .mas_rpm_id = -1,
1313 .slv_rpm_id = 58,
1314 .qos.ap_owned = true,
1315 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1316 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1317 .links = slv_cnoc_mnoc_mmss_cfg_links
1318};
1319
1320static struct qcom_icc_node slv_mmagic_cfg = {
1321 .name = "slv_mmagic_cfg",
1322 .id = MSM8996_SLAVE_MMAGIC_CFG,
1323 .buswidth = 8,
1324 .mas_rpm_id = -1,
1325 .slv_rpm_id = 162,
1326 .qos.ap_owned = true,
1327 .qos.qos_mode = NOC_QOS_MODE_INVALID
1328};
1329
1330static struct qcom_icc_node slv_cpr_cfg = {
1331 .name = "slv_cpr_cfg",
1332 .id = MSM8996_SLAVE_CPR_CFG,
1333 .buswidth = 8,
1334 .mas_rpm_id = -1,
1335 .slv_rpm_id = 6,
1336 .qos.ap_owned = true,
1337 .qos.qos_mode = NOC_QOS_MODE_INVALID
1338};
1339
1340static struct qcom_icc_node slv_misc_cfg = {
1341 .name = "slv_misc_cfg",
1342 .id = MSM8996_SLAVE_MISC_CFG,
1343 .buswidth = 8,
1344 .mas_rpm_id = -1,
1345 .slv_rpm_id = 8,
1346 .qos.ap_owned = true,
1347 .qos.qos_mode = NOC_QOS_MODE_INVALID
1348};
1349
1350static struct qcom_icc_node slv_venus_throttle_cfg = {
1351 .name = "slv_venus_throttle_cfg",
1352 .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG,
1353 .buswidth = 8,
1354 .mas_rpm_id = -1,
1355 .slv_rpm_id = 178,
1356 .qos.ap_owned = true,
1357 .qos.qos_mode = NOC_QOS_MODE_INVALID
1358};
1359
1360static struct qcom_icc_node slv_venus_cfg = {
1361 .name = "slv_venus_cfg",
1362 .id = MSM8996_SLAVE_VENUS_CFG,
1363 .buswidth = 8,
1364 .mas_rpm_id = -1,
1365 .slv_rpm_id = 10,
1366 .qos.ap_owned = true,
1367 .qos.qos_mode = NOC_QOS_MODE_INVALID
1368};
1369
1370static struct qcom_icc_node slv_vmem_cfg = {
1371 .name = "slv_vmem_cfg",
1372 .id = MSM8996_SLAVE_VMEM_CFG,
1373 .buswidth = 8,
1374 .mas_rpm_id = -1,
1375 .slv_rpm_id = 180,
1376 .qos.ap_owned = true,
1377 .qos.qos_mode = NOC_QOS_MODE_INVALID
1378};
1379
1380static struct qcom_icc_node slv_dsa_cfg = {
1381 .name = "slv_dsa_cfg",
1382 .id = MSM8996_SLAVE_DSA_CFG,
1383 .buswidth = 8,
1384 .mas_rpm_id = -1,
1385 .slv_rpm_id = 157,
1386 .qos.ap_owned = true,
1387 .qos.qos_mode = NOC_QOS_MODE_INVALID
1388};
1389
1390static struct qcom_icc_node slv_mnoc_clocks_cfg = {
1391 .name = "slv_mnoc_clocks_cfg",
1392 .id = MSM8996_SLAVE_MMSS_CLK_CFG,
1393 .buswidth = 8,
1394 .mas_rpm_id = -1,
1395 .slv_rpm_id = 12,
1396 .qos.ap_owned = true,
1397 .qos.qos_mode = NOC_QOS_MODE_INVALID
1398};
1399
1400static struct qcom_icc_node slv_dsa_mpu_cfg = {
1401 .name = "slv_dsa_mpu_cfg",
1402 .id = MSM8996_SLAVE_DSA_MPU_CFG,
1403 .buswidth = 8,
1404 .mas_rpm_id = -1,
1405 .slv_rpm_id = 158,
1406 .qos.ap_owned = true,
1407 .qos.qos_mode = NOC_QOS_MODE_INVALID
1408};
1409
1410static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1411 .name = "slv_mnoc_mpu_cfg",
1412 .id = MSM8996_SLAVE_MNOC_MPU_CFG,
1413 .buswidth = 8,
1414 .mas_rpm_id = -1,
1415 .slv_rpm_id = 14,
1416 .qos.ap_owned = true,
1417 .qos.qos_mode = NOC_QOS_MODE_INVALID
1418};
1419
1420static struct qcom_icc_node slv_display_cfg = {
1421 .name = "slv_display_cfg",
1422 .id = MSM8996_SLAVE_DISPLAY_CFG,
1423 .buswidth = 8,
1424 .mas_rpm_id = -1,
1425 .slv_rpm_id = 4,
1426 .qos.ap_owned = true,
1427 .qos.qos_mode = NOC_QOS_MODE_INVALID
1428};
1429
1430static struct qcom_icc_node slv_display_throttle_cfg = {
1431 .name = "slv_display_throttle_cfg",
1432 .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
1433 .buswidth = 8,
1434 .mas_rpm_id = -1,
1435 .slv_rpm_id = 156,
1436 .qos.ap_owned = true,
1437 .qos.qos_mode = NOC_QOS_MODE_INVALID
1438};
1439
1440static struct qcom_icc_node slv_camera_cfg = {
1441 .name = "slv_camera_cfg",
1442 .id = MSM8996_SLAVE_CAMERA_CFG,
1443 .buswidth = 8,
1444 .mas_rpm_id = -1,
1445 .slv_rpm_id = 3,
1446 .qos.ap_owned = true,
1447 .qos.qos_mode = NOC_QOS_MODE_INVALID
1448};
1449
1450static struct qcom_icc_node slv_camera_throttle_cfg = {
1451 .name = "slv_camera_throttle_cfg",
1452 .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
1453 .buswidth = 8,
1454 .mas_rpm_id = -1,
1455 .slv_rpm_id = 154,
1456 .qos.ap_owned = true,
1457 .qos.qos_mode = NOC_QOS_MODE_INVALID
1458};
1459
1460static struct qcom_icc_node slv_oxili_cfg = {
1461 .name = "slv_oxili_cfg",
1462 .id = MSM8996_SLAVE_GRAPHICS_3D_CFG,
1463 .buswidth = 8,
1464 .mas_rpm_id = -1,
1465 .slv_rpm_id = 11,
1466 .qos.ap_owned = true,
1467 .qos.qos_mode = NOC_QOS_MODE_INVALID
1468};
1469
1470static struct qcom_icc_node slv_smmu_mdp_cfg = {
1471 .name = "slv_smmu_mdp_cfg",
1472 .id = MSM8996_SLAVE_SMMU_MDP_CFG,
1473 .buswidth = 8,
1474 .mas_rpm_id = -1,
1475 .slv_rpm_id = 173,
1476 .qos.ap_owned = true,
1477 .qos.qos_mode = NOC_QOS_MODE_INVALID
1478};
1479
1480static struct qcom_icc_node slv_smmu_rot_cfg = {
1481 .name = "slv_smmu_rot_cfg",
1482 .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG,
1483 .buswidth = 8,
1484 .mas_rpm_id = -1,
1485 .slv_rpm_id = 174,
1486 .qos.ap_owned = true,
1487 .qos.qos_mode = NOC_QOS_MODE_INVALID
1488};
1489
1490static struct qcom_icc_node slv_smmu_venus_cfg = {
1491 .name = "slv_smmu_venus_cfg",
1492 .id = MSM8996_SLAVE_SMMU_VENUS_CFG,
1493 .buswidth = 8,
1494 .mas_rpm_id = -1,
1495 .slv_rpm_id = 175,
1496 .qos.ap_owned = true,
1497 .qos.qos_mode = NOC_QOS_MODE_INVALID
1498};
1499
1500static struct qcom_icc_node slv_smmu_cpp_cfg = {
1501 .name = "slv_smmu_cpp_cfg",
1502 .id = MSM8996_SLAVE_SMMU_CPP_CFG,
1503 .buswidth = 8,
1504 .mas_rpm_id = -1,
1505 .slv_rpm_id = 171,
1506 .qos.ap_owned = true,
1507 .qos.qos_mode = NOC_QOS_MODE_INVALID
1508};
1509
1510static struct qcom_icc_node slv_smmu_jpeg_cfg = {
1511 .name = "slv_smmu_jpeg_cfg",
1512 .id = MSM8996_SLAVE_SMMU_JPEG_CFG,
1513 .buswidth = 8,
1514 .mas_rpm_id = -1,
1515 .slv_rpm_id = 172,
1516 .qos.ap_owned = true,
1517 .qos.qos_mode = NOC_QOS_MODE_INVALID
1518};
1519
1520static struct qcom_icc_node slv_smmu_vfe_cfg = {
1521 .name = "slv_smmu_vfe_cfg",
1522 .id = MSM8996_SLAVE_SMMU_VFE_CFG,
1523 .buswidth = 8,
1524 .mas_rpm_id = -1,
1525 .slv_rpm_id = 176,
1526 .qos.ap_owned = true,
1527 .qos.qos_mode = NOC_QOS_MODE_INVALID
1528};
1529
1530static const u16 slv_mnoc_bimc_links[] = {
1531 MSM8996_MASTER_MNOC_BIMC
1532};
1533
1534static struct qcom_icc_node slv_mnoc_bimc = {
1535 .name = "slv_mnoc_bimc",
1536 .id = MSM8996_SLAVE_MNOC_BIMC,
1537 .buswidth = 32,
1538 .mas_rpm_id = -1,
1539 .slv_rpm_id = 16,
1540 .qos.ap_owned = true,
1541 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1542 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1543 .links = slv_mnoc_bimc_links
1544};
1545
1546static struct qcom_icc_node slv_vmem = {
1547 .name = "slv_vmem",
1548 .id = MSM8996_SLAVE_VMEM,
1549 .buswidth = 32,
1550 .mas_rpm_id = -1,
1551 .slv_rpm_id = 179,
1552 .qos.ap_owned = true,
1553 .qos.qos_mode = NOC_QOS_MODE_INVALID
1554};
1555
1556static struct qcom_icc_node slv_srvc_mnoc = {
1557 .name = "slv_srvc_mnoc",
1558 .id = MSM8996_SLAVE_SERVICE_MNOC,
1559 .buswidth = 8,
1560 .mas_rpm_id = -1,
1561 .slv_rpm_id = 17,
1562 .qos.ap_owned = true,
1563 .qos.qos_mode = NOC_QOS_MODE_INVALID
1564};
1565
1566static const u16 slv_pnoc_a1noc_links[] = {
1567 MSM8996_MASTER_PNOC_A1NOC
1568};
1569
1570static struct qcom_icc_node slv_pnoc_a1noc = {
1571 .name = "slv_pnoc_a1noc",
1572 .id = MSM8996_SLAVE_PNOC_A1NOC,
1573 .buswidth = 8,
1574 .mas_rpm_id = -1,
1575 .slv_rpm_id = 139,
1576 .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links),
1577 .links = slv_pnoc_a1noc_links
1578};
1579
1580static struct qcom_icc_node slv_usb_hs = {
1581 .name = "slv_usb_hs",
1582 .id = MSM8996_SLAVE_USB_HS,
1583 .buswidth = 4,
1584 .mas_rpm_id = -1,
1585 .slv_rpm_id = 40
1586};
1587
1588static struct qcom_icc_node slv_sdcc_2 = {
1589 .name = "slv_sdcc_2",
1590 .id = MSM8996_SLAVE_SDCC_2,
1591 .buswidth = 4,
1592 .mas_rpm_id = -1,
1593 .slv_rpm_id = 33
1594};
1595
1596static struct qcom_icc_node slv_sdcc_4 = {
1597 .name = "slv_sdcc_4",
1598 .id = MSM8996_SLAVE_SDCC_4,
1599 .buswidth = 4,
1600 .mas_rpm_id = -1,
1601 .slv_rpm_id = 34
1602};
1603
1604static struct qcom_icc_node slv_tsif = {
1605 .name = "slv_tsif",
1606 .id = MSM8996_SLAVE_TSIF,
1607 .buswidth = 4,
1608 .mas_rpm_id = -1,
1609 .slv_rpm_id = 35
1610};
1611
1612static struct qcom_icc_node slv_blsp_2 = {
1613 .name = "slv_blsp_2",
1614 .id = MSM8996_SLAVE_BLSP_2,
1615 .buswidth = 4,
1616 .mas_rpm_id = -1,
1617 .slv_rpm_id = 37
1618};
1619
1620static struct qcom_icc_node slv_sdcc_1 = {
1621 .name = "slv_sdcc_1",
1622 .id = MSM8996_SLAVE_SDCC_1,
1623 .buswidth = 4,
1624 .mas_rpm_id = -1,
1625 .slv_rpm_id = 31
1626};
1627
1628static struct qcom_icc_node slv_blsp_1 = {
1629 .name = "slv_blsp_1",
1630 .id = MSM8996_SLAVE_BLSP_1,
1631 .buswidth = 4,
1632 .mas_rpm_id = -1,
1633 .slv_rpm_id = 39
1634};
1635
1636static struct qcom_icc_node slv_pdm = {
1637 .name = "slv_pdm",
1638 .id = MSM8996_SLAVE_PDM,
1639 .buswidth = 4,
1640 .mas_rpm_id = -1,
1641 .slv_rpm_id = 41
1642};
1643
1644static struct qcom_icc_node slv_ahb2phy = {
1645 .name = "slv_ahb2phy",
1646 .id = MSM8996_SLAVE_AHB2PHY,
1647 .buswidth = 4,
1648 .mas_rpm_id = -1,
1649 .slv_rpm_id = 153,
1650 .qos.ap_owned = true,
1651 .qos.qos_mode = NOC_QOS_MODE_INVALID
1652};
1653
1654static struct qcom_icc_node slv_hmss = {
1655 .name = "slv_hmss",
1656 .id = MSM8996_SLAVE_APPSS,
1657 .buswidth = 16,
1658 .mas_rpm_id = -1,
1659 .slv_rpm_id = 20,
1660 .qos.ap_owned = true,
1661 .qos.qos_mode = NOC_QOS_MODE_INVALID
1662};
1663
1664static struct qcom_icc_node slv_lpass = {
1665 .name = "slv_lpass",
1666 .id = MSM8996_SLAVE_LPASS,
1667 .buswidth = 16,
1668 .mas_rpm_id = -1,
1669 .slv_rpm_id = 21,
1670 .qos.ap_owned = true,
1671 .qos.qos_mode = NOC_QOS_MODE_INVALID
1672};
1673
1674static struct qcom_icc_node slv_usb3 = {
1675 .name = "slv_usb3",
1676 .id = MSM8996_SLAVE_USB3,
1677 .buswidth = 16,
1678 .mas_rpm_id = -1,
1679 .slv_rpm_id = 22,
1680 .qos.ap_owned = true,
1681 .qos.qos_mode = NOC_QOS_MODE_INVALID
1682};
1683
1684static const u16 slv_snoc_bimc_links[] = {
1685 MSM8996_MASTER_SNOC_BIMC
1686};
1687
1688static struct qcom_icc_node slv_snoc_bimc = {
1689 .name = "slv_snoc_bimc",
1690 .id = MSM8996_SLAVE_SNOC_BIMC,
1691 .buswidth = 32,
1692 .mas_rpm_id = -1,
1693 .slv_rpm_id = 24,
1694 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1695 .links = slv_snoc_bimc_links
1696};
1697
1698static const u16 slv_snoc_cnoc_links[] = {
1699 MSM8996_MASTER_SNOC_CNOC
1700};
1701
1702static struct qcom_icc_node slv_snoc_cnoc = {
1703 .name = "slv_snoc_cnoc",
1704 .id = MSM8996_SLAVE_SNOC_CNOC,
1705 .buswidth = 16,
1706 .mas_rpm_id = -1,
1707 .slv_rpm_id = 25,
1708 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1709 .links = slv_snoc_cnoc_links
1710};
1711
1712static struct qcom_icc_node slv_imem = {
1713 .name = "slv_imem",
1714 .id = MSM8996_SLAVE_OCIMEM,
1715 .buswidth = 16,
1716 .mas_rpm_id = -1,
1717 .slv_rpm_id = 26
1718};
1719
1720static struct qcom_icc_node slv_pimem = {
1721 .name = "slv_pimem",
1722 .id = MSM8996_SLAVE_PIMEM,
1723 .buswidth = 16,
1724 .mas_rpm_id = -1,
1725 .slv_rpm_id = 166
1726};
1727
1728static const u16 slv_snoc_vmem_links[] = {
1729 MSM8996_MASTER_SNOC_VMEM
1730};
1731
1732static struct qcom_icc_node slv_snoc_vmem = {
1733 .name = "slv_snoc_vmem",
1734 .id = MSM8996_SLAVE_SNOC_VMEM,
1735 .buswidth = 16,
1736 .mas_rpm_id = -1,
1737 .slv_rpm_id = 140,
1738 .qos.ap_owned = true,
1739 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1740 .num_links = ARRAY_SIZE(slv_snoc_vmem_links),
1741 .links = slv_snoc_vmem_links
1742};
1743
1744static const u16 slv_snoc_pnoc_links[] = {
1745 MSM8996_MASTER_SNOC_PNOC
1746};
1747
1748static struct qcom_icc_node slv_snoc_pnoc = {
1749 .name = "slv_snoc_pnoc",
1750 .id = MSM8996_SLAVE_SNOC_PNOC,
1751 .buswidth = 16,
1752 .mas_rpm_id = -1,
1753 .slv_rpm_id = 28,
1754 .num_links = ARRAY_SIZE(slv_snoc_pnoc_links),
1755 .links = slv_snoc_pnoc_links
1756};
1757
1758static struct qcom_icc_node slv_qdss_stm = {
1759 .name = "slv_qdss_stm",
1760 .id = MSM8996_SLAVE_QDSS_STM,
1761 .buswidth = 16,
1762 .mas_rpm_id = -1,
1763 .slv_rpm_id = 30
1764};
1765
1766static struct qcom_icc_node slv_pcie_0 = {
1767 .name = "slv_pcie_0",
1768 .id = MSM8996_SLAVE_PCIE_0,
1769 .buswidth = 16,
1770 .mas_rpm_id = -1,
1771 .slv_rpm_id = 84,
1772 .qos.ap_owned = true,
1773 .qos.qos_mode = NOC_QOS_MODE_INVALID
1774};
1775
1776static struct qcom_icc_node slv_pcie_1 = {
1777 .name = "slv_pcie_1",
1778 .id = MSM8996_SLAVE_PCIE_1,
1779 .buswidth = 16,
1780 .mas_rpm_id = -1,
1781 .slv_rpm_id = 85,
1782 .qos.ap_owned = true,
1783 .qos.qos_mode = NOC_QOS_MODE_INVALID
1784};
1785
1786static struct qcom_icc_node slv_pcie_2 = {
1787 .name = "slv_pcie_2",
1788 .id = MSM8996_SLAVE_PCIE_2,
1789 .buswidth = 16,
1790 .mas_rpm_id = -1,
1791 .slv_rpm_id = 164,
1792 .qos.ap_owned = true,
1793 .qos.qos_mode = NOC_QOS_MODE_INVALID
1794};
1795
1796static struct qcom_icc_node slv_srvc_snoc = {
1797 .name = "slv_srvc_snoc",
1798 .id = MSM8996_SLAVE_SERVICE_SNOC,
1799 .buswidth = 16,
1800 .mas_rpm_id = -1,
1801 .slv_rpm_id = 29,
1802 .qos.ap_owned = true,
1803 .qos.qos_mode = NOC_QOS_MODE_INVALID
1804};
1805
1806static struct qcom_icc_node * const a0noc_nodes[] = {
1807 [MASTER_PCIE_0] = &mas_pcie_0,
1808 [MASTER_PCIE_1] = &mas_pcie_1,
1809 [MASTER_PCIE_2] = &mas_pcie_2
1810};
1811
1812static const struct regmap_config msm8996_a0noc_regmap_config = {
1813 .reg_bits = 32,
1814 .reg_stride = 4,
1815 .val_bits = 32,
1816 .max_register = 0x6000,
1817 .fast_io = true
1818};
1819
1820static const struct qcom_icc_desc msm8996_a0noc = {
1821 .type = QCOM_ICC_NOC,
1822 .nodes = a0noc_nodes,
1823 .num_nodes = ARRAY_SIZE(a0noc_nodes),
1824 .clocks = bus_a0noc_clocks,
1825 .num_clocks = ARRAY_SIZE(bus_a0noc_clocks),
1826 .regmap_cfg = &msm8996_a0noc_regmap_config
1827};
1828
1829static struct qcom_icc_node * const a1noc_nodes[] = {
1830 [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc,
1831 [MASTER_CRYPTO_CORE0] = &mas_crypto_c0,
1832 [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc
1833};
1834
1835static const struct regmap_config msm8996_a1noc_regmap_config = {
1836 .reg_bits = 32,
1837 .reg_stride = 4,
1838 .val_bits = 32,
1839 .max_register = 0x5000,
1840 .fast_io = true
1841};
1842
1843static const struct qcom_icc_desc msm8996_a1noc = {
1844 .type = QCOM_ICC_NOC,
1845 .nodes = a1noc_nodes,
1846 .num_nodes = ARRAY_SIZE(a1noc_nodes),
1847 .regmap_cfg = &msm8996_a1noc_regmap_config
1848};
1849
1850static struct qcom_icc_node * const a2noc_nodes[] = {
1851 [MASTER_USB3] = &mas_usb3,
1852 [MASTER_IPA] = &mas_ipa,
1853 [MASTER_UFS] = &mas_ufs
1854};
1855
1856static const struct regmap_config msm8996_a2noc_regmap_config = {
1857 .reg_bits = 32,
1858 .reg_stride = 4,
1859 .val_bits = 32,
1860 .max_register = 0x7000,
1861 .fast_io = true
1862};
1863
1864static const struct qcom_icc_desc msm8996_a2noc = {
1865 .type = QCOM_ICC_NOC,
1866 .nodes = a2noc_nodes,
1867 .num_nodes = ARRAY_SIZE(a2noc_nodes),
1868 .clocks = bus_a2noc_clocks,
1869 .num_clocks = ARRAY_SIZE(bus_a2noc_clocks),
1870 .regmap_cfg = &msm8996_a2noc_regmap_config
1871};
1872
1873static struct qcom_icc_node * const bimc_nodes[] = {
1874 [MASTER_AMPSS_M0] = &mas_apps_proc,
1875 [MASTER_GRAPHICS_3D] = &mas_oxili,
1876 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1877 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1878 [SLAVE_EBI_CH0] = &slv_ebi,
1879 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1880 [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
1881 [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1
1882};
1883
1884static const struct regmap_config msm8996_bimc_regmap_config = {
1885 .reg_bits = 32,
1886 .reg_stride = 4,
1887 .val_bits = 32,
1888 .max_register = 0x5a000,
1889 .fast_io = true
1890};
1891
1892static const struct qcom_icc_desc msm8996_bimc = {
1893 .type = QCOM_ICC_BIMC,
1894 .nodes = bimc_nodes,
1895 .num_nodes = ARRAY_SIZE(bimc_nodes),
1896 .regmap_cfg = &msm8996_bimc_regmap_config
1897};
1898
1899static struct qcom_icc_node * const cnoc_nodes[] = {
1900 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1901 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1902 [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc,
1903 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1904 [SLAVE_TCSR] = &slv_tcsr,
1905 [SLAVE_TLMM] = &slv_tlmm,
1906 [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg,
1907 [SLAVE_MPM] = &slv_mpm,
1908 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1909 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1910 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1911 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1912 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1913 [SLAVE_PRNG] = &slv_prng,
1914 [SLAVE_DCC_CFG] = &slv_dcc_cfg,
1915 [SLAVE_RBCPR_MX] = &slv_rbcpr_mx,
1916 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1917 [SLAVE_RBCPR_CX] = &slv_rbcpr_cx,
1918 [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg,
1919 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1920 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1921 [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
1922 [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
1923 [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg,
1924 [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg,
1925 [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg,
1926 [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg,
1927 [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy,
1928 [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg,
1929 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1930 [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
1931 [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg,
1932 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1933 [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg,
1934 [SLAVE_SSC_CFG] = &slv_ssc_cfg,
1935 [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg,
1936 [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
1937 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1938 [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg,
1939 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg
1940};
1941
1942static const struct regmap_config msm8996_cnoc_regmap_config = {
1943 .reg_bits = 32,
1944 .reg_stride = 4,
1945 .val_bits = 32,
1946 .max_register = 0x1000,
1947 .fast_io = true
1948};
1949
1950static const struct qcom_icc_desc msm8996_cnoc = {
1951 .type = QCOM_ICC_NOC,
1952 .nodes = cnoc_nodes,
1953 .num_nodes = ARRAY_SIZE(cnoc_nodes),
1954 .regmap_cfg = &msm8996_cnoc_regmap_config
1955};
1956
1957static struct qcom_icc_node * const mnoc_nodes[] = {
1958 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1959 [MASTER_CPP] = &mas_cpp,
1960 [MASTER_JPEG] = &mas_jpeg,
1961 [MASTER_MDP_PORT0] = &mas_mdp_p0,
1962 [MASTER_MDP_PORT1] = &mas_mdp_p1,
1963 [MASTER_ROTATOR] = &mas_rotator,
1964 [MASTER_VIDEO_P0] = &mas_venus,
1965 [MASTER_VFE] = &mas_vfe,
1966 [MASTER_SNOC_VMEM] = &mas_snoc_vmem,
1967 [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem,
1968 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1969 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1970 [SLAVE_VMEM] = &slv_vmem,
1971 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1972 [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg,
1973 [SLAVE_CPR_CFG] = &slv_cpr_cfg,
1974 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1975 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1976 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1977 [SLAVE_VMEM_CFG] = &slv_vmem_cfg,
1978 [SLAVE_DSA_CFG] = &slv_dsa_cfg,
1979 [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg,
1980 [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg,
1981 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1982 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1983 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1984 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1985 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1986 [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg,
1987 [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg,
1988 [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg,
1989 [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg,
1990 [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg,
1991 [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg,
1992 [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg
1993};
1994
1995static const struct regmap_config msm8996_mnoc_regmap_config = {
1996 .reg_bits = 32,
1997 .reg_stride = 4,
1998 .val_bits = 32,
1999 .max_register = 0x1c000,
2000 .fast_io = true
2001};
2002
2003static const struct qcom_icc_desc msm8996_mnoc = {
2004 .type = QCOM_ICC_NOC,
2005 .nodes = mnoc_nodes,
2006 .num_nodes = ARRAY_SIZE(mnoc_nodes),
2007 .clocks = bus_mm_clocks,
2008 .num_clocks = ARRAY_SIZE(bus_mm_clocks),
2009 .regmap_cfg = &msm8996_mnoc_regmap_config
2010};
2011
2012static struct qcom_icc_node * const pnoc_nodes[] = {
2013 [MASTER_SNOC_PNOC] = &mas_snoc_pnoc,
2014 [MASTER_SDCC_1] = &mas_sdcc_1,
2015 [MASTER_SDCC_2] = &mas_sdcc_2,
2016 [MASTER_SDCC_4] = &mas_sdcc_4,
2017 [MASTER_USB_HS] = &mas_usb_hs,
2018 [MASTER_BLSP_1] = &mas_blsp_1,
2019 [MASTER_BLSP_2] = &mas_blsp_2,
2020 [MASTER_TSIF] = &mas_tsif,
2021 [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc,
2022 [SLAVE_USB_HS] = &slv_usb_hs,
2023 [SLAVE_SDCC_2] = &slv_sdcc_2,
2024 [SLAVE_SDCC_4] = &slv_sdcc_4,
2025 [SLAVE_TSIF] = &slv_tsif,
2026 [SLAVE_BLSP_2] = &slv_blsp_2,
2027 [SLAVE_SDCC_1] = &slv_sdcc_1,
2028 [SLAVE_BLSP_1] = &slv_blsp_1,
2029 [SLAVE_PDM] = &slv_pdm,
2030 [SLAVE_AHB2PHY] = &slv_ahb2phy
2031};
2032
2033static const struct regmap_config msm8996_pnoc_regmap_config = {
2034 .reg_bits = 32,
2035 .reg_stride = 4,
2036 .val_bits = 32,
2037 .max_register = 0x3000,
2038 .fast_io = true
2039};
2040
2041static const struct qcom_icc_desc msm8996_pnoc = {
2042 .type = QCOM_ICC_NOC,
2043 .nodes = pnoc_nodes,
2044 .num_nodes = ARRAY_SIZE(pnoc_nodes),
2045 .regmap_cfg = &msm8996_pnoc_regmap_config
2046};
2047
2048static struct qcom_icc_node * const snoc_nodes[] = {
2049 [MASTER_HMSS] = &mas_hmss,
2050 [MASTER_QDSS_BAM] = &mas_qdss_bam,
2051 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
2052 [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
2053 [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
2054 [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc,
2055 [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
2056 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
2057 [MASTER_QDSS_ETR] = &mas_qdss_etr,
2058 [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc,
2059 [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
2060 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
2061 [SLAVE_HMSS] = &slv_hmss,
2062 [SLAVE_LPASS] = &slv_lpass,
2063 [SLAVE_USB3] = &slv_usb3,
2064 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
2065 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
2066 [SLAVE_IMEM] = &slv_imem,
2067 [SLAVE_PIMEM] = &slv_pimem,
2068 [SLAVE_SNOC_VMEM] = &slv_snoc_vmem,
2069 [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc,
2070 [SLAVE_QDSS_STM] = &slv_qdss_stm,
2071 [SLAVE_PCIE_0] = &slv_pcie_0,
2072 [SLAVE_PCIE_1] = &slv_pcie_1,
2073 [SLAVE_PCIE_2] = &slv_pcie_2,
2074 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc
2075};
2076
2077static const struct regmap_config msm8996_snoc_regmap_config = {
2078 .reg_bits = 32,
2079 .reg_stride = 4,
2080 .val_bits = 32,
2081 .max_register = 0x20000,
2082 .fast_io = true
2083};
2084
2085static const struct qcom_icc_desc msm8996_snoc = {
2086 .type = QCOM_ICC_NOC,
2087 .nodes = snoc_nodes,
2088 .num_nodes = ARRAY_SIZE(snoc_nodes),
2089 .regmap_cfg = &msm8996_snoc_regmap_config
2090};
2091
2092static const struct of_device_id qnoc_of_match[] = {
2093 { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc},
2094 { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc},
2095 { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc},
2096 { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc},
2097 { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc},
2098 { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc},
2099 { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc},
2100 { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc},
2101 { }
2102};
2103MODULE_DEVICE_TABLE(of, qnoc_of_match);
2104
2105static struct platform_driver qnoc_driver = {
2106 .probe = qnoc_probe,
2107 .remove = qnoc_remove,
2108 .driver = {
2109 .name = "qnoc-msm8996",
2110 .of_match_table = qnoc_of_match,
2111 .sync_state = icc_sync_state,
2112 }
2113};
2114module_platform_driver(qnoc_driver);
2115
2116MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2117MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
2118MODULE_LICENSE("GPL v2");