tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "uvd/uvd_7_0_offset.h"
41#include "gc/gc_9_0_offset.h"
42#include "gc/gc_9_0_sh_mask.h"
43#include "sdma0/sdma0_4_0_offset.h"
44#include "sdma1/sdma1_4_0_offset.h"
45#include "nbio/nbio_7_0_default.h"
46#include "nbio/nbio_7_0_offset.h"
47#include "nbio/nbio_7_0_sh_mask.h"
48#include "nbio/nbio_7_0_smn.h"
49#include "mp/mp_9_0_offset.h"
50
51#include "soc15.h"
52#include "soc15_common.h"
53#include "gfx_v9_0.h"
54#include "gmc_v9_0.h"
55#include "gfxhub_v1_0.h"
56#include "mmhub_v1_0.h"
57#include "df_v1_7.h"
58#include "df_v3_6.h"
59#include "nbio_v6_1.h"
60#include "nbio_v7_0.h"
61#include "nbio_v7_4.h"
62#include "hdp_v4_0.h"
63#include "vega10_ih.h"
64#include "vega20_ih.h"
65#include "navi10_ih.h"
66#include "sdma_v4_0.h"
67#include "uvd_v7_0.h"
68#include "vce_v4_0.h"
69#include "vcn_v1_0.h"
70#include "vcn_v2_0.h"
71#include "jpeg_v2_0.h"
72#include "vcn_v2_5.h"
73#include "jpeg_v2_5.h"
74#include "smuio_v9_0.h"
75#include "smuio_v11_0.h"
76#include "smuio_v13_0.h"
77#include "amdgpu_vkms.h"
78#include "mxgpu_ai.h"
79#include "amdgpu_ras.h"
80#include "amdgpu_xgmi.h"
81#include <uapi/linux/kfd_ioctl.h>
82
83#define mmMP0_MISC_CGTT_CTRL0 0x01b9
84#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88static const struct amd_ip_funcs soc15_common_ip_funcs;
89
90/* Vega, Raven, Arcturus */
91static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92{
93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
95};
96
97static const struct amdgpu_video_codecs vega_video_codecs_encode =
98{
99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 .codec_array = vega_video_codecs_encode_array,
101};
102
103/* Vega */
104static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105{
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
112};
113
114static const struct amdgpu_video_codecs vega_video_codecs_decode =
115{
116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
117 .codec_array = vega_video_codecs_decode_array,
118};
119
120/* Raven */
121static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
122{
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
130};
131
132static const struct amdgpu_video_codecs rv_video_codecs_decode =
133{
134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
135 .codec_array = rv_video_codecs_decode_array,
136};
137
138/* Renoir, Arcturus */
139static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
140{
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
148};
149
150static const struct amdgpu_video_codecs rn_video_codecs_decode =
151{
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154};
155
156static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
157 const struct amdgpu_video_codecs **codecs)
158{
159 if (adev->ip_versions[VCE_HWIP][0]) {
160 switch (adev->ip_versions[VCE_HWIP][0]) {
161 case IP_VERSION(4, 0, 0):
162 case IP_VERSION(4, 1, 0):
163 if (encode)
164 *codecs = &vega_video_codecs_encode;
165 else
166 *codecs = &vega_video_codecs_decode;
167 return 0;
168 default:
169 return -EINVAL;
170 }
171 } else {
172 switch (adev->ip_versions[UVD_HWIP][0]) {
173 case IP_VERSION(1, 0, 0):
174 case IP_VERSION(1, 0, 1):
175 if (encode)
176 *codecs = &vega_video_codecs_encode;
177 else
178 *codecs = &rv_video_codecs_decode;
179 return 0;
180 case IP_VERSION(2, 5, 0):
181 case IP_VERSION(2, 6, 0):
182 case IP_VERSION(2, 2, 0):
183 if (encode)
184 *codecs = &vega_video_codecs_encode;
185 else
186 *codecs = &rn_video_codecs_decode;
187 return 0;
188 default:
189 return -EINVAL;
190 }
191 }
192}
193
194static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
195{
196 unsigned long flags, address, data;
197 u32 r;
198
199 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
200 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
201
202 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
203 WREG32(address, ((reg) & 0x1ff));
204 r = RREG32(data);
205 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
206 return r;
207}
208
209static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
210{
211 unsigned long flags, address, data;
212
213 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
214 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
215
216 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
217 WREG32(address, ((reg) & 0x1ff));
218 WREG32(data, (v));
219 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
220}
221
222static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
223{
224 unsigned long flags, address, data;
225 u32 r;
226
227 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
228 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
229
230 spin_lock_irqsave(&adev->didt_idx_lock, flags);
231 WREG32(address, (reg));
232 r = RREG32(data);
233 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
234 return r;
235}
236
237static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
238{
239 unsigned long flags, address, data;
240
241 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
242 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
243
244 spin_lock_irqsave(&adev->didt_idx_lock, flags);
245 WREG32(address, (reg));
246 WREG32(data, (v));
247 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
248}
249
250static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
251{
252 unsigned long flags;
253 u32 r;
254
255 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
256 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
257 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
258 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
259 return r;
260}
261
262static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
263{
264 unsigned long flags;
265
266 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
267 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
268 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
269 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
270}
271
272static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
273{
274 unsigned long flags;
275 u32 r;
276
277 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
278 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
279 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
280 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
281 return r;
282}
283
284static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
285{
286 unsigned long flags;
287
288 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
289 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
290 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
291 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
292}
293
294static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
295{
296 return adev->nbio.funcs->get_memsize(adev);
297}
298
299static u32 soc15_get_xclk(struct amdgpu_device *adev)
300{
301 u32 reference_clock = adev->clock.spll.reference_freq;
302
303 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
304 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) ||
305 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
306 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
307 return 10000;
308
309 return reference_clock;
310}
311
312
313void soc15_grbm_select(struct amdgpu_device *adev,
314 u32 me, u32 pipe, u32 queue, u32 vmid)
315{
316 u32 grbm_gfx_cntl = 0;
317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
319 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
320 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
321
322 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
323}
324
325static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
326{
327 /* todo */
328}
329
330static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
331{
332 /* todo */
333 return false;
334}
335
336static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
342 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
343 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
344 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
348 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
354 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
355 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
356 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
357};
358
359static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
360 u32 sh_num, u32 reg_offset)
361{
362 uint32_t val;
363
364 mutex_lock(&adev->grbm_idx_mutex);
365 if (se_num != 0xffffffff || sh_num != 0xffffffff)
366 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
367
368 val = RREG32(reg_offset);
369
370 if (se_num != 0xffffffff || sh_num != 0xffffffff)
371 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
372 mutex_unlock(&adev->grbm_idx_mutex);
373 return val;
374}
375
376static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
377 bool indexed, u32 se_num,
378 u32 sh_num, u32 reg_offset)
379{
380 if (indexed) {
381 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
382 } else {
383 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
384 return adev->gfx.config.gb_addr_config;
385 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
386 return adev->gfx.config.db_debug2;
387 return RREG32(reg_offset);
388 }
389}
390
391static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
392 u32 sh_num, u32 reg_offset, u32 *value)
393{
394 uint32_t i;
395 struct soc15_allowed_register_entry *en;
396
397 *value = 0;
398 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
399 en = &soc15_allowed_read_registers[i];
400 if (!adev->reg_offset[en->hwip][en->inst])
401 continue;
402 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
403 + en->reg_offset))
404 continue;
405
406 *value = soc15_get_register_value(adev,
407 soc15_allowed_read_registers[i].grbm_indexed,
408 se_num, sh_num, reg_offset);
409 return 0;
410 }
411 return -EINVAL;
412}
413
414
415/**
416 * soc15_program_register_sequence - program an array of registers.
417 *
418 * @adev: amdgpu_device pointer
419 * @regs: pointer to the register array
420 * @array_size: size of the register array
421 *
422 * Programs an array or registers with and and or masks.
423 * This is a helper for setting golden registers.
424 */
425
426void soc15_program_register_sequence(struct amdgpu_device *adev,
427 const struct soc15_reg_golden *regs,
428 const u32 array_size)
429{
430 const struct soc15_reg_golden *entry;
431 u32 tmp, reg;
432 int i;
433
434 for (i = 0; i < array_size; ++i) {
435 entry = ®s[i];
436 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
437
438 if (entry->and_mask == 0xffffffff) {
439 tmp = entry->or_mask;
440 } else {
441 tmp = (entry->hwip == GC_HWIP) ?
442 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
443
444 tmp &= ~(entry->and_mask);
445 tmp |= (entry->or_mask & entry->and_mask);
446 }
447
448 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
449 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
450 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
451 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
452 WREG32_RLC(reg, tmp);
453 else
454 (entry->hwip == GC_HWIP) ?
455 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
456
457 }
458
459}
460
461static int soc15_asic_baco_reset(struct amdgpu_device *adev)
462{
463 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
464 int ret = 0;
465
466 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
467 if (ras && adev->ras_enabled)
468 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
469
470 ret = amdgpu_dpm_baco_reset(adev);
471 if (ret)
472 return ret;
473
474 /* re-enable doorbell interrupt after BACO exit */
475 if (ras && adev->ras_enabled)
476 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
477
478 return 0;
479}
480
481static enum amd_reset_method
482soc15_asic_reset_method(struct amdgpu_device *adev)
483{
484 bool baco_reset = false;
485 bool connected_to_cpu = false;
486 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
487
488 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
489 connected_to_cpu = true;
490
491 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
492 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
493 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
494 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
495 /* If connected to cpu, driver only support mode2 */
496 if (connected_to_cpu)
497 return AMD_RESET_METHOD_MODE2;
498 return amdgpu_reset_method;
499 }
500
501 if (amdgpu_reset_method != -1)
502 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
503 amdgpu_reset_method);
504
505 switch (adev->ip_versions[MP1_HWIP][0]) {
506 case IP_VERSION(10, 0, 0):
507 case IP_VERSION(10, 0, 1):
508 case IP_VERSION(12, 0, 0):
509 case IP_VERSION(12, 0, 1):
510 return AMD_RESET_METHOD_MODE2;
511 case IP_VERSION(9, 0, 0):
512 case IP_VERSION(11, 0, 2):
513 if (adev->asic_type == CHIP_VEGA20) {
514 if (adev->psp.sos.fw_version >= 0x80067)
515 baco_reset = amdgpu_dpm_is_baco_supported(adev);
516 /*
517 * 1. PMFW version > 0x284300: all cases use baco
518 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
519 */
520 if (ras && adev->ras_enabled &&
521 adev->pm.fw_version <= 0x283400)
522 baco_reset = false;
523 } else {
524 baco_reset = amdgpu_dpm_is_baco_supported(adev);
525 }
526 break;
527 case IP_VERSION(13, 0, 2):
528 /*
529 * 1.connected to cpu: driver issue mode2 reset
530 * 2.discret gpu: driver issue mode1 reset
531 */
532 if (connected_to_cpu)
533 return AMD_RESET_METHOD_MODE2;
534 break;
535 default:
536 break;
537 }
538
539 if (baco_reset)
540 return AMD_RESET_METHOD_BACO;
541 else
542 return AMD_RESET_METHOD_MODE1;
543}
544
545static int soc15_asic_reset(struct amdgpu_device *adev)
546{
547 /* original raven doesn't have full asic reset */
548 if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
549 (adev->apu_flags & AMD_APU_IS_RAVEN2))
550 return 0;
551
552 switch (soc15_asic_reset_method(adev)) {
553 case AMD_RESET_METHOD_PCI:
554 dev_info(adev->dev, "PCI reset\n");
555 return amdgpu_device_pci_reset(adev);
556 case AMD_RESET_METHOD_BACO:
557 dev_info(adev->dev, "BACO reset\n");
558 return soc15_asic_baco_reset(adev);
559 case AMD_RESET_METHOD_MODE2:
560 dev_info(adev->dev, "MODE2 reset\n");
561 return amdgpu_dpm_mode2_reset(adev);
562 default:
563 dev_info(adev->dev, "MODE1 reset\n");
564 return amdgpu_device_mode1_reset(adev);
565 }
566}
567
568static bool soc15_supports_baco(struct amdgpu_device *adev)
569{
570 switch (adev->ip_versions[MP1_HWIP][0]) {
571 case IP_VERSION(9, 0, 0):
572 case IP_VERSION(11, 0, 2):
573 if (adev->asic_type == CHIP_VEGA20) {
574 if (adev->psp.sos.fw_version >= 0x80067)
575 return amdgpu_dpm_is_baco_supported(adev);
576 return false;
577 } else {
578 return amdgpu_dpm_is_baco_supported(adev);
579 }
580 break;
581 default:
582 return false;
583 }
584}
585
586/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
587 u32 cntl_reg, u32 status_reg)
588{
589 return 0;
590}*/
591
592static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
593{
594 /*int r;
595
596 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
597 if (r)
598 return r;
599
600 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
601 */
602 return 0;
603}
604
605static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
606{
607 /* todo */
608
609 return 0;
610}
611
612static void soc15_program_aspm(struct amdgpu_device *adev)
613{
614 if (!amdgpu_device_should_use_aspm(adev))
615 return;
616
617 if (!(adev->flags & AMD_IS_APU) &&
618 (adev->nbio.funcs->program_aspm))
619 adev->nbio.funcs->program_aspm(adev);
620}
621
622const struct amdgpu_ip_block_version vega10_common_ip_block =
623{
624 .type = AMD_IP_BLOCK_TYPE_COMMON,
625 .major = 2,
626 .minor = 0,
627 .rev = 0,
628 .funcs = &soc15_common_ip_funcs,
629};
630
631static void soc15_reg_base_init(struct amdgpu_device *adev)
632{
633 /* Set IP register base before any HW register access */
634 switch (adev->asic_type) {
635 case CHIP_VEGA10:
636 case CHIP_VEGA12:
637 case CHIP_RAVEN:
638 case CHIP_RENOIR:
639 vega10_reg_base_init(adev);
640 break;
641 case CHIP_VEGA20:
642 vega20_reg_base_init(adev);
643 break;
644 case CHIP_ARCTURUS:
645 arct_reg_base_init(adev);
646 break;
647 case CHIP_ALDEBARAN:
648 aldebaran_reg_base_init(adev);
649 break;
650 default:
651 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
652 break;
653 }
654}
655
656void soc15_set_virt_ops(struct amdgpu_device *adev)
657{
658 adev->virt.ops = &xgpu_ai_virt_ops;
659
660 /* init soc15 reg base early enough so we can
661 * request request full access for sriov before
662 * set_ip_blocks. */
663 soc15_reg_base_init(adev);
664}
665
666static bool soc15_need_full_reset(struct amdgpu_device *adev)
667{
668 /* change this when we implement soft reset */
669 return true;
670}
671
672static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
673 uint64_t *count1)
674{
675 uint32_t perfctr = 0;
676 uint64_t cnt0_of, cnt1_of;
677 int tmp;
678
679 /* This reports 0 on APUs, so return to avoid writing/reading registers
680 * that may or may not be different from their GPU counterparts
681 */
682 if (adev->flags & AMD_IS_APU)
683 return;
684
685 /* Set the 2 events that we wish to watch, defined above */
686 /* Reg 40 is # received msgs */
687 /* Reg 104 is # of posted requests sent */
688 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
689 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
690
691 /* Write to enable desired perf counters */
692 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
693 /* Zero out and enable the perf counters
694 * Write 0x5:
695 * Bit 0 = Start all counters(1)
696 * Bit 2 = Global counter reset enable(1)
697 */
698 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
699
700 msleep(1000);
701
702 /* Load the shadow and disable the perf counters
703 * Write 0x2:
704 * Bit 0 = Stop counters(0)
705 * Bit 1 = Load the shadow counters(1)
706 */
707 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
708
709 /* Read register values to get any >32bit overflow */
710 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
711 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
712 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
713
714 /* Get the values and add the overflow */
715 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
716 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
717}
718
719static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
720 uint64_t *count1)
721{
722 uint32_t perfctr = 0;
723 uint64_t cnt0_of, cnt1_of;
724 int tmp;
725
726 /* This reports 0 on APUs, so return to avoid writing/reading registers
727 * that may or may not be different from their GPU counterparts
728 */
729 if (adev->flags & AMD_IS_APU)
730 return;
731
732 /* Set the 2 events that we wish to watch, defined above */
733 /* Reg 40 is # received msgs */
734 /* Reg 108 is # of posted requests sent on VG20 */
735 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
736 EVENT0_SEL, 40);
737 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
738 EVENT1_SEL, 108);
739
740 /* Write to enable desired perf counters */
741 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
742 /* Zero out and enable the perf counters
743 * Write 0x5:
744 * Bit 0 = Start all counters(1)
745 * Bit 2 = Global counter reset enable(1)
746 */
747 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
748
749 msleep(1000);
750
751 /* Load the shadow and disable the perf counters
752 * Write 0x2:
753 * Bit 0 = Stop counters(0)
754 * Bit 1 = Load the shadow counters(1)
755 */
756 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
757
758 /* Read register values to get any >32bit overflow */
759 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
760 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
761 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
762
763 /* Get the values and add the overflow */
764 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
765 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
766}
767
768static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
769{
770 u32 sol_reg;
771
772 /* CP hangs in IGT reloading test on RN, reset to WA */
773 if (adev->asic_type == CHIP_RENOIR)
774 return true;
775
776 /* Just return false for soc15 GPUs. Reset does not seem to
777 * be necessary.
778 */
779 if (!amdgpu_passthrough(adev))
780 return false;
781
782 if (adev->flags & AMD_IS_APU)
783 return false;
784
785 /* Check sOS sign of life register to confirm sys driver and sOS
786 * are already been loaded.
787 */
788 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
789 if (sol_reg)
790 return true;
791
792 return false;
793}
794
795static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
796{
797 uint64_t nak_r, nak_g;
798
799 /* Get the number of NAKs received and generated */
800 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
801 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
802
803 /* Add the total number of NAKs, i.e the number of replays */
804 return (nak_r + nak_g);
805}
806
807static void soc15_pre_asic_init(struct amdgpu_device *adev)
808{
809 gmc_v9_0_restore_registers(adev);
810}
811
812static const struct amdgpu_asic_funcs soc15_asic_funcs =
813{
814 .read_disabled_bios = &soc15_read_disabled_bios,
815 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
816 .read_register = &soc15_read_register,
817 .reset = &soc15_asic_reset,
818 .reset_method = &soc15_asic_reset_method,
819 .set_vga_state = &soc15_vga_set_state,
820 .get_xclk = &soc15_get_xclk,
821 .set_uvd_clocks = &soc15_set_uvd_clocks,
822 .set_vce_clocks = &soc15_set_vce_clocks,
823 .get_config_memsize = &soc15_get_config_memsize,
824 .need_full_reset = &soc15_need_full_reset,
825 .init_doorbell_index = &vega10_doorbell_index_init,
826 .get_pcie_usage = &soc15_get_pcie_usage,
827 .need_reset_on_init = &soc15_need_reset_on_init,
828 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
829 .supports_baco = &soc15_supports_baco,
830 .pre_asic_init = &soc15_pre_asic_init,
831 .query_video_codecs = &soc15_query_video_codecs,
832};
833
834static const struct amdgpu_asic_funcs vega20_asic_funcs =
835{
836 .read_disabled_bios = &soc15_read_disabled_bios,
837 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
838 .read_register = &soc15_read_register,
839 .reset = &soc15_asic_reset,
840 .reset_method = &soc15_asic_reset_method,
841 .set_vga_state = &soc15_vga_set_state,
842 .get_xclk = &soc15_get_xclk,
843 .set_uvd_clocks = &soc15_set_uvd_clocks,
844 .set_vce_clocks = &soc15_set_vce_clocks,
845 .get_config_memsize = &soc15_get_config_memsize,
846 .need_full_reset = &soc15_need_full_reset,
847 .init_doorbell_index = &vega20_doorbell_index_init,
848 .get_pcie_usage = &vega20_get_pcie_usage,
849 .need_reset_on_init = &soc15_need_reset_on_init,
850 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
851 .supports_baco = &soc15_supports_baco,
852 .pre_asic_init = &soc15_pre_asic_init,
853 .query_video_codecs = &soc15_query_video_codecs,
854};
855
856static int soc15_common_early_init(void *handle)
857{
858#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
860
861 if (!amdgpu_sriov_vf(adev)) {
862 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
863 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
864 }
865 adev->smc_rreg = NULL;
866 adev->smc_wreg = NULL;
867 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
868 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
869 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
870 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
871 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
872 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
873 adev->didt_rreg = &soc15_didt_rreg;
874 adev->didt_wreg = &soc15_didt_wreg;
875 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
876 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
877 adev->se_cac_rreg = &soc15_se_cac_rreg;
878 adev->se_cac_wreg = &soc15_se_cac_wreg;
879
880 adev->rev_id = amdgpu_device_get_rev_id(adev);
881 adev->external_rev_id = 0xFF;
882 /* TODO: split the GC and PG flags based on the relevant IP version for which
883 * they are relevant.
884 */
885 switch (adev->ip_versions[GC_HWIP][0]) {
886 case IP_VERSION(9, 0, 1):
887 adev->asic_funcs = &soc15_asic_funcs;
888 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
889 AMD_CG_SUPPORT_GFX_MGLS |
890 AMD_CG_SUPPORT_GFX_RLC_LS |
891 AMD_CG_SUPPORT_GFX_CP_LS |
892 AMD_CG_SUPPORT_GFX_3D_CGCG |
893 AMD_CG_SUPPORT_GFX_3D_CGLS |
894 AMD_CG_SUPPORT_GFX_CGCG |
895 AMD_CG_SUPPORT_GFX_CGLS |
896 AMD_CG_SUPPORT_BIF_MGCG |
897 AMD_CG_SUPPORT_BIF_LS |
898 AMD_CG_SUPPORT_HDP_LS |
899 AMD_CG_SUPPORT_DRM_MGCG |
900 AMD_CG_SUPPORT_DRM_LS |
901 AMD_CG_SUPPORT_ROM_MGCG |
902 AMD_CG_SUPPORT_DF_MGCG |
903 AMD_CG_SUPPORT_SDMA_MGCG |
904 AMD_CG_SUPPORT_SDMA_LS |
905 AMD_CG_SUPPORT_MC_MGCG |
906 AMD_CG_SUPPORT_MC_LS;
907 adev->pg_flags = 0;
908 adev->external_rev_id = 0x1;
909 break;
910 case IP_VERSION(9, 2, 1):
911 adev->asic_funcs = &soc15_asic_funcs;
912 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
913 AMD_CG_SUPPORT_GFX_MGLS |
914 AMD_CG_SUPPORT_GFX_CGCG |
915 AMD_CG_SUPPORT_GFX_CGLS |
916 AMD_CG_SUPPORT_GFX_3D_CGCG |
917 AMD_CG_SUPPORT_GFX_3D_CGLS |
918 AMD_CG_SUPPORT_GFX_CP_LS |
919 AMD_CG_SUPPORT_MC_LS |
920 AMD_CG_SUPPORT_MC_MGCG |
921 AMD_CG_SUPPORT_SDMA_MGCG |
922 AMD_CG_SUPPORT_SDMA_LS |
923 AMD_CG_SUPPORT_BIF_MGCG |
924 AMD_CG_SUPPORT_BIF_LS |
925 AMD_CG_SUPPORT_HDP_MGCG |
926 AMD_CG_SUPPORT_HDP_LS |
927 AMD_CG_SUPPORT_ROM_MGCG |
928 AMD_CG_SUPPORT_VCE_MGCG |
929 AMD_CG_SUPPORT_UVD_MGCG;
930 adev->pg_flags = 0;
931 adev->external_rev_id = adev->rev_id + 0x14;
932 break;
933 case IP_VERSION(9, 4, 0):
934 adev->asic_funcs = &vega20_asic_funcs;
935 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
936 AMD_CG_SUPPORT_GFX_MGLS |
937 AMD_CG_SUPPORT_GFX_CGCG |
938 AMD_CG_SUPPORT_GFX_CGLS |
939 AMD_CG_SUPPORT_GFX_3D_CGCG |
940 AMD_CG_SUPPORT_GFX_3D_CGLS |
941 AMD_CG_SUPPORT_GFX_CP_LS |
942 AMD_CG_SUPPORT_MC_LS |
943 AMD_CG_SUPPORT_MC_MGCG |
944 AMD_CG_SUPPORT_SDMA_MGCG |
945 AMD_CG_SUPPORT_SDMA_LS |
946 AMD_CG_SUPPORT_BIF_MGCG |
947 AMD_CG_SUPPORT_BIF_LS |
948 AMD_CG_SUPPORT_HDP_MGCG |
949 AMD_CG_SUPPORT_HDP_LS |
950 AMD_CG_SUPPORT_ROM_MGCG |
951 AMD_CG_SUPPORT_VCE_MGCG |
952 AMD_CG_SUPPORT_UVD_MGCG;
953 adev->pg_flags = 0;
954 adev->external_rev_id = adev->rev_id + 0x28;
955 break;
956 case IP_VERSION(9, 1, 0):
957 case IP_VERSION(9, 2, 2):
958 adev->asic_funcs = &soc15_asic_funcs;
959
960 if (adev->rev_id >= 0x8)
961 adev->apu_flags |= AMD_APU_IS_RAVEN2;
962
963 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
964 adev->external_rev_id = adev->rev_id + 0x79;
965 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
966 adev->external_rev_id = adev->rev_id + 0x41;
967 else if (adev->rev_id == 1)
968 adev->external_rev_id = adev->rev_id + 0x20;
969 else
970 adev->external_rev_id = adev->rev_id + 0x01;
971
972 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
973 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
974 AMD_CG_SUPPORT_GFX_MGLS |
975 AMD_CG_SUPPORT_GFX_CP_LS |
976 AMD_CG_SUPPORT_GFX_3D_CGCG |
977 AMD_CG_SUPPORT_GFX_3D_CGLS |
978 AMD_CG_SUPPORT_GFX_CGCG |
979 AMD_CG_SUPPORT_GFX_CGLS |
980 AMD_CG_SUPPORT_BIF_LS |
981 AMD_CG_SUPPORT_HDP_LS |
982 AMD_CG_SUPPORT_MC_MGCG |
983 AMD_CG_SUPPORT_MC_LS |
984 AMD_CG_SUPPORT_SDMA_MGCG |
985 AMD_CG_SUPPORT_SDMA_LS |
986 AMD_CG_SUPPORT_VCN_MGCG;
987
988 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
989 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
990 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
991 AMD_CG_SUPPORT_GFX_MGLS |
992 AMD_CG_SUPPORT_GFX_CP_LS |
993 AMD_CG_SUPPORT_GFX_3D_CGLS |
994 AMD_CG_SUPPORT_GFX_CGCG |
995 AMD_CG_SUPPORT_GFX_CGLS |
996 AMD_CG_SUPPORT_BIF_LS |
997 AMD_CG_SUPPORT_HDP_LS |
998 AMD_CG_SUPPORT_MC_MGCG |
999 AMD_CG_SUPPORT_MC_LS |
1000 AMD_CG_SUPPORT_SDMA_MGCG |
1001 AMD_CG_SUPPORT_SDMA_LS |
1002 AMD_CG_SUPPORT_VCN_MGCG;
1003
1004 /*
1005 * MMHUB PG needs to be disabled for Picasso for
1006 * stability reasons.
1007 */
1008 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1009 AMD_PG_SUPPORT_VCN;
1010 } else {
1011 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1012 AMD_CG_SUPPORT_GFX_MGLS |
1013 AMD_CG_SUPPORT_GFX_RLC_LS |
1014 AMD_CG_SUPPORT_GFX_CP_LS |
1015 AMD_CG_SUPPORT_GFX_3D_CGLS |
1016 AMD_CG_SUPPORT_GFX_CGCG |
1017 AMD_CG_SUPPORT_GFX_CGLS |
1018 AMD_CG_SUPPORT_BIF_MGCG |
1019 AMD_CG_SUPPORT_BIF_LS |
1020 AMD_CG_SUPPORT_HDP_MGCG |
1021 AMD_CG_SUPPORT_HDP_LS |
1022 AMD_CG_SUPPORT_DRM_MGCG |
1023 AMD_CG_SUPPORT_DRM_LS |
1024 AMD_CG_SUPPORT_MC_MGCG |
1025 AMD_CG_SUPPORT_MC_LS |
1026 AMD_CG_SUPPORT_SDMA_MGCG |
1027 AMD_CG_SUPPORT_SDMA_LS |
1028 AMD_CG_SUPPORT_VCN_MGCG;
1029
1030 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1031 }
1032 break;
1033 case IP_VERSION(9, 4, 1):
1034 adev->asic_funcs = &vega20_asic_funcs;
1035 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1036 AMD_CG_SUPPORT_GFX_MGLS |
1037 AMD_CG_SUPPORT_GFX_CGCG |
1038 AMD_CG_SUPPORT_GFX_CGLS |
1039 AMD_CG_SUPPORT_GFX_CP_LS |
1040 AMD_CG_SUPPORT_HDP_MGCG |
1041 AMD_CG_SUPPORT_HDP_LS |
1042 AMD_CG_SUPPORT_SDMA_MGCG |
1043 AMD_CG_SUPPORT_SDMA_LS |
1044 AMD_CG_SUPPORT_MC_MGCG |
1045 AMD_CG_SUPPORT_MC_LS |
1046 AMD_CG_SUPPORT_IH_CG |
1047 AMD_CG_SUPPORT_VCN_MGCG |
1048 AMD_CG_SUPPORT_JPEG_MGCG;
1049 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1050 adev->external_rev_id = adev->rev_id + 0x32;
1051 break;
1052 case IP_VERSION(9, 3, 0):
1053 adev->asic_funcs = &soc15_asic_funcs;
1054
1055 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1056 adev->external_rev_id = adev->rev_id + 0x91;
1057 else
1058 adev->external_rev_id = adev->rev_id + 0xa1;
1059 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1060 AMD_CG_SUPPORT_GFX_MGLS |
1061 AMD_CG_SUPPORT_GFX_3D_CGCG |
1062 AMD_CG_SUPPORT_GFX_3D_CGLS |
1063 AMD_CG_SUPPORT_GFX_CGCG |
1064 AMD_CG_SUPPORT_GFX_CGLS |
1065 AMD_CG_SUPPORT_GFX_CP_LS |
1066 AMD_CG_SUPPORT_MC_MGCG |
1067 AMD_CG_SUPPORT_MC_LS |
1068 AMD_CG_SUPPORT_SDMA_MGCG |
1069 AMD_CG_SUPPORT_SDMA_LS |
1070 AMD_CG_SUPPORT_BIF_LS |
1071 AMD_CG_SUPPORT_HDP_LS |
1072 AMD_CG_SUPPORT_VCN_MGCG |
1073 AMD_CG_SUPPORT_JPEG_MGCG |
1074 AMD_CG_SUPPORT_IH_CG |
1075 AMD_CG_SUPPORT_ATHUB_LS |
1076 AMD_CG_SUPPORT_ATHUB_MGCG |
1077 AMD_CG_SUPPORT_DF_MGCG;
1078 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1079 AMD_PG_SUPPORT_VCN |
1080 AMD_PG_SUPPORT_JPEG |
1081 AMD_PG_SUPPORT_VCN_DPG;
1082 break;
1083 case IP_VERSION(9, 4, 2):
1084 adev->asic_funcs = &vega20_asic_funcs;
1085 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1086 AMD_CG_SUPPORT_GFX_MGLS |
1087 AMD_CG_SUPPORT_GFX_CP_LS |
1088 AMD_CG_SUPPORT_HDP_LS |
1089 AMD_CG_SUPPORT_SDMA_MGCG |
1090 AMD_CG_SUPPORT_SDMA_LS |
1091 AMD_CG_SUPPORT_IH_CG |
1092 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1093 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1094 adev->external_rev_id = adev->rev_id + 0x3c;
1095 break;
1096 case IP_VERSION(9, 4, 3):
1097 adev->asic_funcs = &vega20_asic_funcs;
1098 adev->cg_flags = 0;
1099 adev->pg_flags = 0;
1100 break;
1101 default:
1102 /* FIXME: not supported yet */
1103 return -EINVAL;
1104 }
1105
1106 if (amdgpu_sriov_vf(adev)) {
1107 amdgpu_virt_init_setting(adev);
1108 xgpu_ai_mailbox_set_irq_funcs(adev);
1109 }
1110
1111 return 0;
1112}
1113
1114static int soc15_common_late_init(void *handle)
1115{
1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1117
1118 if (amdgpu_sriov_vf(adev))
1119 xgpu_ai_mailbox_get_irq(adev);
1120
1121 /* Enable selfring doorbell aperture late because doorbell BAR
1122 * aperture will change if resize BAR successfully in gmc sw_init.
1123 */
1124 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1125
1126 return 0;
1127}
1128
1129static int soc15_common_sw_init(void *handle)
1130{
1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133 if (amdgpu_sriov_vf(adev))
1134 xgpu_ai_mailbox_add_irq_id(adev);
1135
1136 if (adev->df.funcs &&
1137 adev->df.funcs->sw_init)
1138 adev->df.funcs->sw_init(adev);
1139
1140 return 0;
1141}
1142
1143static int soc15_common_sw_fini(void *handle)
1144{
1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146
1147 if (adev->df.funcs &&
1148 adev->df.funcs->sw_fini)
1149 adev->df.funcs->sw_fini(adev);
1150 return 0;
1151}
1152
1153static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1154{
1155 int i;
1156
1157 /* sdma doorbell range is programed by hypervisor */
1158 if (!amdgpu_sriov_vf(adev)) {
1159 for (i = 0; i < adev->sdma.num_instances; i++) {
1160 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1161 true, adev->doorbell_index.sdma_engine[i] << 1,
1162 adev->doorbell_index.sdma_doorbell_range);
1163 }
1164 }
1165}
1166
1167static int soc15_common_hw_init(void *handle)
1168{
1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1170
1171 /* enable aspm */
1172 soc15_program_aspm(adev);
1173 /* setup nbio registers */
1174 adev->nbio.funcs->init_registers(adev);
1175 /* remap HDP registers to a hole in mmio space,
1176 * for the purpose of expose those registers
1177 * to process space
1178 */
1179 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1180 adev->nbio.funcs->remap_hdp_registers(adev);
1181
1182 /* enable the doorbell aperture */
1183 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1184
1185 /* HW doorbell routing policy: doorbell writing not
1186 * in SDMA/IH/MM/ACV range will be routed to CP. So
1187 * we need to init SDMA doorbell range prior
1188 * to CP ip block init and ring test. IH already
1189 * happens before CP.
1190 */
1191 soc15_sdma_doorbell_range_init(adev);
1192
1193 return 0;
1194}
1195
1196static int soc15_common_hw_fini(void *handle)
1197{
1198 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199
1200 /* Disable the doorbell aperture and selfring doorbell aperture
1201 * separately in hw_fini because soc15_enable_doorbell_aperture
1202 * has been removed and there is no need to delay disabling
1203 * selfring doorbell.
1204 */
1205 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1206 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1207
1208 if (amdgpu_sriov_vf(adev))
1209 xgpu_ai_mailbox_put_irq(adev);
1210
1211 if (adev->nbio.ras_if &&
1212 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1213 if (adev->nbio.ras &&
1214 adev->nbio.ras->init_ras_controller_interrupt)
1215 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1216 if (adev->nbio.ras &&
1217 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1218 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1219 }
1220
1221 return 0;
1222}
1223
1224static int soc15_common_suspend(void *handle)
1225{
1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228 return soc15_common_hw_fini(adev);
1229}
1230
1231static int soc15_common_resume(void *handle)
1232{
1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235 return soc15_common_hw_init(adev);
1236}
1237
1238static bool soc15_common_is_idle(void *handle)
1239{
1240 return true;
1241}
1242
1243static int soc15_common_wait_for_idle(void *handle)
1244{
1245 return 0;
1246}
1247
1248static int soc15_common_soft_reset(void *handle)
1249{
1250 return 0;
1251}
1252
1253static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1254{
1255 uint32_t def, data;
1256
1257 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1258
1259 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1260 data &= ~(0x01000000 |
1261 0x02000000 |
1262 0x04000000 |
1263 0x08000000 |
1264 0x10000000 |
1265 0x20000000 |
1266 0x40000000 |
1267 0x80000000);
1268 else
1269 data |= (0x01000000 |
1270 0x02000000 |
1271 0x04000000 |
1272 0x08000000 |
1273 0x10000000 |
1274 0x20000000 |
1275 0x40000000 |
1276 0x80000000);
1277
1278 if (def != data)
1279 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1280}
1281
1282static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1283{
1284 uint32_t def, data;
1285
1286 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1287
1288 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1289 data |= 1;
1290 else
1291 data &= ~1;
1292
1293 if (def != data)
1294 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1295}
1296
1297static int soc15_common_set_clockgating_state(void *handle,
1298 enum amd_clockgating_state state)
1299{
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301
1302 if (amdgpu_sriov_vf(adev))
1303 return 0;
1304
1305 switch (adev->ip_versions[NBIO_HWIP][0]) {
1306 case IP_VERSION(6, 1, 0):
1307 case IP_VERSION(6, 2, 0):
1308 case IP_VERSION(7, 4, 0):
1309 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1310 state == AMD_CG_STATE_GATE);
1311 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1312 state == AMD_CG_STATE_GATE);
1313 adev->hdp.funcs->update_clock_gating(adev,
1314 state == AMD_CG_STATE_GATE);
1315 soc15_update_drm_clock_gating(adev,
1316 state == AMD_CG_STATE_GATE);
1317 soc15_update_drm_light_sleep(adev,
1318 state == AMD_CG_STATE_GATE);
1319 adev->smuio.funcs->update_rom_clock_gating(adev,
1320 state == AMD_CG_STATE_GATE);
1321 adev->df.funcs->update_medium_grain_clock_gating(adev,
1322 state == AMD_CG_STATE_GATE);
1323 break;
1324 case IP_VERSION(7, 0, 0):
1325 case IP_VERSION(7, 0, 1):
1326 case IP_VERSION(2, 5, 0):
1327 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1328 state == AMD_CG_STATE_GATE);
1329 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1330 state == AMD_CG_STATE_GATE);
1331 adev->hdp.funcs->update_clock_gating(adev,
1332 state == AMD_CG_STATE_GATE);
1333 soc15_update_drm_clock_gating(adev,
1334 state == AMD_CG_STATE_GATE);
1335 soc15_update_drm_light_sleep(adev,
1336 state == AMD_CG_STATE_GATE);
1337 break;
1338 case IP_VERSION(7, 4, 1):
1339 case IP_VERSION(7, 4, 4):
1340 adev->hdp.funcs->update_clock_gating(adev,
1341 state == AMD_CG_STATE_GATE);
1342 break;
1343 default:
1344 break;
1345 }
1346 return 0;
1347}
1348
1349static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1350{
1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352 int data;
1353
1354 if (amdgpu_sriov_vf(adev))
1355 *flags = 0;
1356
1357 adev->nbio.funcs->get_clockgating_state(adev, flags);
1358
1359 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1360
1361 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1362
1363 /* AMD_CG_SUPPORT_DRM_MGCG */
1364 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1365 if (!(data & 0x01000000))
1366 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1367
1368 /* AMD_CG_SUPPORT_DRM_LS */
1369 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1370 if (data & 0x1)
1371 *flags |= AMD_CG_SUPPORT_DRM_LS;
1372 }
1373
1374 /* AMD_CG_SUPPORT_ROM_MGCG */
1375 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1376
1377 adev->df.funcs->get_clockgating_state(adev, flags);
1378}
1379
1380static int soc15_common_set_powergating_state(void *handle,
1381 enum amd_powergating_state state)
1382{
1383 /* todo */
1384 return 0;
1385}
1386
1387static const struct amd_ip_funcs soc15_common_ip_funcs = {
1388 .name = "soc15_common",
1389 .early_init = soc15_common_early_init,
1390 .late_init = soc15_common_late_init,
1391 .sw_init = soc15_common_sw_init,
1392 .sw_fini = soc15_common_sw_fini,
1393 .hw_init = soc15_common_hw_init,
1394 .hw_fini = soc15_common_hw_fini,
1395 .suspend = soc15_common_suspend,
1396 .resume = soc15_common_resume,
1397 .is_idle = soc15_common_is_idle,
1398 .wait_for_idle = soc15_common_wait_for_idle,
1399 .soft_reset = soc15_common_soft_reset,
1400 .set_clockgating_state = soc15_common_set_clockgating_state,
1401 .set_powergating_state = soc15_common_set_powergating_state,
1402 .get_clockgating_state= soc15_common_get_clockgating_state,
1403};