tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy
8
9maintainers:
10 - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13 compatible:
14 enum:
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
17
18 reg:
19 maxItems: 1
20
21 clocks:
22 items:
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
26
27 clock-names:
28 items:
29 - const: ref
30 - const: apb
31 - const: pipe
32
33 resets:
34 items:
35 - description: exclusive PHY reset line
36
37 rockchip,enable-ssc:
38 type: boolean
39 description:
40 The option SSC can be enabled for U3, SATA and PCIE.
41 Most commercially available platforms use SSC to reduce EMI.
42
43 rockchip,ext-refclk:
44 type: boolean
45 description:
46 Many PCIe connections, especially backplane connections,
47 require a synchronous reference clock between the two link partners.
48 To achieve this a common clock source, referred to as REFCLK in
49 the PCI Express Card Electromechanical Specification,
50 should be used by both ends of the PCIe link.
51 In PCIe mode one can choose to use an internal or an external reference
52 clock.
53 By default the internal clock is selected. The PCIe PHY provides a 100MHz
54 differential clock output(optional with SSC) for system applications.
55 When selecting this option an externally 100MHz differential
56 reference clock needs to be provided to the PCIe PHY.
57
58 rockchip,pipe-grf:
59 $ref: /schemas/types.yaml#/definitions/phandle
60 description:
61 Some additional phy settings are accessed through GRF regs.
62
63 rockchip,pipe-phy-grf:
64 $ref: /schemas/types.yaml#/definitions/phandle
65 description:
66 Some additional pipe settings are accessed through GRF regs.
67
68 "#phy-cells":
69 const: 1
70
71required:
72 - compatible
73 - reg
74 - clocks
75 - clock-names
76 - resets
77 - rockchip,pipe-grf
78 - rockchip,pipe-phy-grf
79 - "#phy-cells"
80
81additionalProperties: false
82
83examples:
84 - |
85 #include <dt-bindings/clock/rk3568-cru.h>
86
87 pipegrf: syscon@fdc50000 {
88 compatible = "rockchip,rk3568-pipe-grf", "syscon";
89 reg = <0xfdc50000 0x1000>;
90 };
91
92 pipe_phy_grf0: syscon@fdc70000 {
93 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
94 reg = <0xfdc70000 0x1000>;
95 };
96
97 combphy0: phy@fe820000 {
98 compatible = "rockchip,rk3568-naneng-combphy";
99 reg = <0xfe820000 0x100>;
100 clocks = <&pmucru CLK_PCIEPHY0_REF>,
101 <&cru PCLK_PIPEPHY0>,
102 <&cru PCLK_PIPE>;
103 clock-names = "ref", "apb", "pipe";
104 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
105 assigned-clock-rates = <100000000>;
106 resets = <&cru SRST_PIPEPHY0>;
107 rockchip,pipe-grf = <&pipegrf>;
108 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
109 #phy-cells = <1>;
110 };