tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/console.h>
8#include <linux/delay.h>
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/dma/sprd-dma.h>
12#include <linux/io.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24/* device name */
25#define UART_NR_MAX 8
26#define SPRD_TTY_NAME "ttyS"
27#define SPRD_FIFO_SIZE 128
28#define SPRD_DEF_RATE 26000000
29#define SPRD_BAUD_IO_LIMIT 3000000
30#define SPRD_TIMEOUT 256000
31
32/* the offset of serial registers and BITs for them */
33/* data registers */
34#define SPRD_TXD 0x0000
35#define SPRD_RXD 0x0004
36
37/* line status register and its BITs */
38#define SPRD_LSR 0x0008
39#define SPRD_LSR_OE BIT(4)
40#define SPRD_LSR_FE BIT(3)
41#define SPRD_LSR_PE BIT(2)
42#define SPRD_LSR_BI BIT(7)
43#define SPRD_LSR_TX_OVER BIT(15)
44
45/* data number in TX and RX fifo */
46#define SPRD_STS1 0x000C
47#define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
48#define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
49
50/* interrupt enable register and its BITs */
51#define SPRD_IEN 0x0010
52#define SPRD_IEN_RX_FULL BIT(0)
53#define SPRD_IEN_TX_EMPTY BIT(1)
54#define SPRD_IEN_BREAK_DETECT BIT(7)
55#define SPRD_IEN_TIMEOUT BIT(13)
56
57/* interrupt clear register */
58#define SPRD_ICLR 0x0014
59#define SPRD_ICLR_TIMEOUT BIT(13)
60
61/* line control register */
62#define SPRD_LCR 0x0018
63#define SPRD_LCR_STOP_1BIT 0x10
64#define SPRD_LCR_STOP_2BIT 0x30
65#define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
66#define SPRD_LCR_DATA_LEN5 0x0
67#define SPRD_LCR_DATA_LEN6 0x4
68#define SPRD_LCR_DATA_LEN7 0x8
69#define SPRD_LCR_DATA_LEN8 0xc
70#define SPRD_LCR_PARITY (BIT(0) | BIT(1))
71#define SPRD_LCR_PARITY_EN 0x2
72#define SPRD_LCR_EVEN_PAR 0x0
73#define SPRD_LCR_ODD_PAR 0x1
74
75/* control register 1 */
76#define SPRD_CTL1 0x001C
77#define SPRD_DMA_EN BIT(15)
78#define SPRD_LOOPBACK_EN BIT(14)
79#define RX_HW_FLOW_CTL_THLD BIT(6)
80#define RX_HW_FLOW_CTL_EN BIT(7)
81#define TX_HW_FLOW_CTL_EN BIT(8)
82#define RX_TOUT_THLD_DEF 0x3E00
83#define RX_HFC_THLD_DEF 0x40
84
85/* fifo threshold register */
86#define SPRD_CTL2 0x0020
87#define THLD_TX_EMPTY 0x40
88#define THLD_TX_EMPTY_SHIFT 8
89#define THLD_RX_FULL 0x40
90#define THLD_RX_FULL_MASK GENMASK(6, 0)
91
92/* config baud rate register */
93#define SPRD_CLKD0 0x0024
94#define SPRD_CLKD0_MASK GENMASK(15, 0)
95#define SPRD_CLKD1 0x0028
96#define SPRD_CLKD1_MASK GENMASK(20, 16)
97#define SPRD_CLKD1_SHIFT 16
98
99/* interrupt mask status register */
100#define SPRD_IMSR 0x002C
101#define SPRD_IMSR_RX_FIFO_FULL BIT(0)
102#define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
103#define SPRD_IMSR_BREAK_DETECT BIT(7)
104#define SPRD_IMSR_TIMEOUT BIT(13)
105#define SPRD_DEFAULT_SOURCE_CLK 26000000
106
107#define SPRD_RX_DMA_STEP 1
108#define SPRD_RX_FIFO_FULL 1
109#define SPRD_TX_FIFO_FULL 0x20
110#define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
111
112struct sprd_uart_dma {
113 struct dma_chan *chn;
114 unsigned char *virt;
115 dma_addr_t phys_addr;
116 dma_cookie_t cookie;
117 u32 trans_len;
118 bool enable;
119};
120
121struct sprd_uart_port {
122 struct uart_port port;
123 char name[16];
124 struct clk *clk;
125 struct sprd_uart_dma tx_dma;
126 struct sprd_uart_dma rx_dma;
127 dma_addr_t pos;
128 unsigned char *rx_buf_tail;
129};
130
131static struct sprd_uart_port *sprd_port[UART_NR_MAX];
132static int sprd_ports_num;
133
134static int sprd_start_dma_rx(struct uart_port *port);
135static int sprd_tx_dma_config(struct uart_port *port);
136
137static inline unsigned int serial_in(struct uart_port *port,
138 unsigned int offset)
139{
140 return readl_relaxed(port->membase + offset);
141}
142
143static inline void serial_out(struct uart_port *port, unsigned int offset,
144 int value)
145{
146 writel_relaxed(value, port->membase + offset);
147}
148
149static unsigned int sprd_tx_empty(struct uart_port *port)
150{
151 if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
152 return 0;
153 else
154 return TIOCSER_TEMT;
155}
156
157static unsigned int sprd_get_mctrl(struct uart_port *port)
158{
159 return TIOCM_DSR | TIOCM_CTS;
160}
161
162static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
163{
164 u32 val = serial_in(port, SPRD_CTL1);
165
166 if (mctrl & TIOCM_LOOP)
167 val |= SPRD_LOOPBACK_EN;
168 else
169 val &= ~SPRD_LOOPBACK_EN;
170
171 serial_out(port, SPRD_CTL1, val);
172}
173
174static void sprd_stop_rx(struct uart_port *port)
175{
176 struct sprd_uart_port *sp =
177 container_of(port, struct sprd_uart_port, port);
178 unsigned int ien, iclr;
179
180 if (sp->rx_dma.enable)
181 dmaengine_terminate_all(sp->rx_dma.chn);
182
183 iclr = serial_in(port, SPRD_ICLR);
184 ien = serial_in(port, SPRD_IEN);
185
186 ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
187 iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
188
189 serial_out(port, SPRD_IEN, ien);
190 serial_out(port, SPRD_ICLR, iclr);
191}
192
193static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
194{
195 u32 val = serial_in(port, SPRD_CTL1);
196
197 if (enable)
198 val |= SPRD_DMA_EN;
199 else
200 val &= ~SPRD_DMA_EN;
201
202 serial_out(port, SPRD_CTL1, val);
203}
204
205static void sprd_stop_tx_dma(struct uart_port *port)
206{
207 struct sprd_uart_port *sp =
208 container_of(port, struct sprd_uart_port, port);
209 struct dma_tx_state state;
210 u32 trans_len;
211
212 dmaengine_pause(sp->tx_dma.chn);
213
214 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
215 if (state.residue) {
216 trans_len = state.residue - sp->tx_dma.phys_addr;
217 uart_xmit_advance(port, trans_len);
218 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
219 sp->tx_dma.trans_len, DMA_TO_DEVICE);
220 }
221
222 dmaengine_terminate_all(sp->tx_dma.chn);
223 sp->tx_dma.trans_len = 0;
224}
225
226static int sprd_tx_buf_remap(struct uart_port *port)
227{
228 struct sprd_uart_port *sp =
229 container_of(port, struct sprd_uart_port, port);
230 struct circ_buf *xmit = &port->state->xmit;
231
232 sp->tx_dma.trans_len =
233 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
234
235 sp->tx_dma.phys_addr = dma_map_single(port->dev,
236 (void *)&(xmit->buf[xmit->tail]),
237 sp->tx_dma.trans_len,
238 DMA_TO_DEVICE);
239 return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
240}
241
242static void sprd_complete_tx_dma(void *data)
243{
244 struct uart_port *port = (struct uart_port *)data;
245 struct sprd_uart_port *sp =
246 container_of(port, struct sprd_uart_port, port);
247 struct circ_buf *xmit = &port->state->xmit;
248 unsigned long flags;
249
250 spin_lock_irqsave(&port->lock, flags);
251 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
252 sp->tx_dma.trans_len, DMA_TO_DEVICE);
253
254 uart_xmit_advance(port, sp->tx_dma.trans_len);
255
256 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
257 uart_write_wakeup(port);
258
259 if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
260 sprd_tx_dma_config(port))
261 sp->tx_dma.trans_len = 0;
262
263 spin_unlock_irqrestore(&port->lock, flags);
264}
265
266static int sprd_uart_dma_submit(struct uart_port *port,
267 struct sprd_uart_dma *ud, u32 trans_len,
268 enum dma_transfer_direction direction,
269 dma_async_tx_callback callback)
270{
271 struct dma_async_tx_descriptor *dma_des;
272 unsigned long flags;
273
274 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
275 SPRD_DMA_NO_TRG,
276 SPRD_DMA_FRAG_REQ,
277 SPRD_DMA_TRANS_INT);
278
279 dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
280 direction, flags);
281 if (!dma_des)
282 return -ENODEV;
283
284 dma_des->callback = callback;
285 dma_des->callback_param = port;
286
287 ud->cookie = dmaengine_submit(dma_des);
288 if (dma_submit_error(ud->cookie))
289 return dma_submit_error(ud->cookie);
290
291 dma_async_issue_pending(ud->chn);
292
293 return 0;
294}
295
296static int sprd_tx_dma_config(struct uart_port *port)
297{
298 struct sprd_uart_port *sp =
299 container_of(port, struct sprd_uart_port, port);
300 u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
301 SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
302 int ret;
303 struct dma_slave_config cfg = {
304 .dst_addr = port->mapbase + SPRD_TXD,
305 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
306 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
307 .src_maxburst = burst,
308 };
309
310 ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
311 if (ret < 0)
312 return ret;
313
314 return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
315 DMA_MEM_TO_DEV, sprd_complete_tx_dma);
316}
317
318static void sprd_start_tx_dma(struct uart_port *port)
319{
320 struct sprd_uart_port *sp =
321 container_of(port, struct sprd_uart_port, port);
322 struct circ_buf *xmit = &port->state->xmit;
323
324 if (port->x_char) {
325 serial_out(port, SPRD_TXD, port->x_char);
326 port->icount.tx++;
327 port->x_char = 0;
328 return;
329 }
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
332 sprd_stop_tx_dma(port);
333 return;
334 }
335
336 if (sp->tx_dma.trans_len)
337 return;
338
339 if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
340 sp->tx_dma.trans_len = 0;
341}
342
343static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
344{
345 u32 val = serial_in(port, SPRD_CTL2);
346
347 val &= ~THLD_RX_FULL_MASK;
348 val |= thld & THLD_RX_FULL_MASK;
349 serial_out(port, SPRD_CTL2, val);
350}
351
352static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
353{
354 sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
355 &sp->rx_dma.phys_addr, GFP_KERNEL);
356 if (!sp->rx_dma.virt)
357 return -ENOMEM;
358
359 return 0;
360}
361
362static void sprd_rx_free_buf(struct sprd_uart_port *sp)
363{
364 if (sp->rx_dma.virt)
365 dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
366 sp->rx_dma.virt, sp->rx_dma.phys_addr);
367
368}
369
370static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
371{
372 struct sprd_uart_port *sp =
373 container_of(port, struct sprd_uart_port, port);
374 struct dma_slave_config cfg = {
375 .src_addr = port->mapbase + SPRD_RXD,
376 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
377 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
378 .src_maxburst = burst,
379 };
380
381 return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
382}
383
384static void sprd_uart_dma_rx(struct uart_port *port)
385{
386 struct sprd_uart_port *sp =
387 container_of(port, struct sprd_uart_port, port);
388 struct tty_port *tty = &port->state->port;
389
390 port->icount.rx += sp->rx_dma.trans_len;
391 tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
392 tty_flip_buffer_push(tty);
393}
394
395static void sprd_uart_dma_irq(struct uart_port *port)
396{
397 struct sprd_uart_port *sp =
398 container_of(port, struct sprd_uart_port, port);
399 struct dma_tx_state state;
400 enum dma_status status;
401
402 status = dmaengine_tx_status(sp->rx_dma.chn,
403 sp->rx_dma.cookie, &state);
404 if (status == DMA_ERROR)
405 sprd_stop_rx(port);
406
407 if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
408 return;
409
410 if (!state.residue) {
411 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
412 sp->rx_dma.phys_addr - sp->pos;
413 sp->pos = sp->rx_dma.phys_addr;
414 } else {
415 sp->rx_dma.trans_len = state.residue - sp->pos;
416 sp->pos = state.residue;
417 }
418
419 sprd_uart_dma_rx(port);
420 sp->rx_buf_tail += sp->rx_dma.trans_len;
421}
422
423static void sprd_complete_rx_dma(void *data)
424{
425 struct uart_port *port = (struct uart_port *)data;
426 struct sprd_uart_port *sp =
427 container_of(port, struct sprd_uart_port, port);
428 struct dma_tx_state state;
429 enum dma_status status;
430 unsigned long flags;
431
432 spin_lock_irqsave(&port->lock, flags);
433
434 status = dmaengine_tx_status(sp->rx_dma.chn,
435 sp->rx_dma.cookie, &state);
436 if (status != DMA_COMPLETE) {
437 sprd_stop_rx(port);
438 spin_unlock_irqrestore(&port->lock, flags);
439 return;
440 }
441
442 if (sp->pos != sp->rx_dma.phys_addr) {
443 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
444 sp->rx_dma.phys_addr - sp->pos;
445 sprd_uart_dma_rx(port);
446 sp->rx_buf_tail += sp->rx_dma.trans_len;
447 }
448
449 if (sprd_start_dma_rx(port))
450 sprd_stop_rx(port);
451
452 spin_unlock_irqrestore(&port->lock, flags);
453}
454
455static int sprd_start_dma_rx(struct uart_port *port)
456{
457 struct sprd_uart_port *sp =
458 container_of(port, struct sprd_uart_port, port);
459 int ret;
460
461 if (!sp->rx_dma.enable)
462 return 0;
463
464 sp->pos = sp->rx_dma.phys_addr;
465 sp->rx_buf_tail = sp->rx_dma.virt;
466 sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
467 ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
468 if (ret)
469 return ret;
470
471 return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
472 DMA_DEV_TO_MEM, sprd_complete_rx_dma);
473}
474
475static void sprd_release_dma(struct uart_port *port)
476{
477 struct sprd_uart_port *sp =
478 container_of(port, struct sprd_uart_port, port);
479
480 sprd_uart_dma_enable(port, false);
481
482 if (sp->rx_dma.enable)
483 dma_release_channel(sp->rx_dma.chn);
484
485 if (sp->tx_dma.enable)
486 dma_release_channel(sp->tx_dma.chn);
487
488 sp->tx_dma.enable = false;
489 sp->rx_dma.enable = false;
490}
491
492static void sprd_request_dma(struct uart_port *port)
493{
494 struct sprd_uart_port *sp =
495 container_of(port, struct sprd_uart_port, port);
496
497 sp->tx_dma.enable = true;
498 sp->rx_dma.enable = true;
499
500 sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
501 if (IS_ERR(sp->tx_dma.chn)) {
502 dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
503 PTR_ERR(sp->tx_dma.chn));
504 sp->tx_dma.enable = false;
505 }
506
507 sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
508 if (IS_ERR(sp->rx_dma.chn)) {
509 dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
510 PTR_ERR(sp->rx_dma.chn));
511 sp->rx_dma.enable = false;
512 }
513}
514
515static void sprd_stop_tx(struct uart_port *port)
516{
517 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
518 port);
519 unsigned int ien, iclr;
520
521 if (sp->tx_dma.enable) {
522 sprd_stop_tx_dma(port);
523 return;
524 }
525
526 iclr = serial_in(port, SPRD_ICLR);
527 ien = serial_in(port, SPRD_IEN);
528
529 iclr |= SPRD_IEN_TX_EMPTY;
530 ien &= ~SPRD_IEN_TX_EMPTY;
531
532 serial_out(port, SPRD_IEN, ien);
533 serial_out(port, SPRD_ICLR, iclr);
534}
535
536static void sprd_start_tx(struct uart_port *port)
537{
538 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
539 port);
540 unsigned int ien;
541
542 if (sp->tx_dma.enable) {
543 sprd_start_tx_dma(port);
544 return;
545 }
546
547 ien = serial_in(port, SPRD_IEN);
548 if (!(ien & SPRD_IEN_TX_EMPTY)) {
549 ien |= SPRD_IEN_TX_EMPTY;
550 serial_out(port, SPRD_IEN, ien);
551 }
552}
553
554/* The Sprd serial does not support this function. */
555static void sprd_break_ctl(struct uart_port *port, int break_state)
556{
557 /* nothing to do */
558}
559
560static int handle_lsr_errors(struct uart_port *port,
561 unsigned int *flag,
562 unsigned int *lsr)
563{
564 int ret = 0;
565
566 /* statistics */
567 if (*lsr & SPRD_LSR_BI) {
568 *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
569 port->icount.brk++;
570 ret = uart_handle_break(port);
571 if (ret)
572 return ret;
573 } else if (*lsr & SPRD_LSR_PE)
574 port->icount.parity++;
575 else if (*lsr & SPRD_LSR_FE)
576 port->icount.frame++;
577 if (*lsr & SPRD_LSR_OE)
578 port->icount.overrun++;
579
580 /* mask off conditions which should be ignored */
581 *lsr &= port->read_status_mask;
582 if (*lsr & SPRD_LSR_BI)
583 *flag = TTY_BREAK;
584 else if (*lsr & SPRD_LSR_PE)
585 *flag = TTY_PARITY;
586 else if (*lsr & SPRD_LSR_FE)
587 *flag = TTY_FRAME;
588
589 return ret;
590}
591
592static inline void sprd_rx(struct uart_port *port)
593{
594 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
595 port);
596 struct tty_port *tty = &port->state->port;
597 unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
598
599 if (sp->rx_dma.enable) {
600 sprd_uart_dma_irq(port);
601 return;
602 }
603
604 while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
605 max_count--) {
606 lsr = serial_in(port, SPRD_LSR);
607 ch = serial_in(port, SPRD_RXD);
608 flag = TTY_NORMAL;
609 port->icount.rx++;
610
611 if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
612 SPRD_LSR_FE | SPRD_LSR_OE))
613 if (handle_lsr_errors(port, &flag, &lsr))
614 continue;
615 if (uart_handle_sysrq_char(port, ch))
616 continue;
617
618 uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
619 }
620
621 tty_flip_buffer_push(tty);
622}
623
624static inline void sprd_tx(struct uart_port *port)
625{
626 u8 ch;
627
628 uart_port_tx_limited(port, ch, THLD_TX_EMPTY,
629 true,
630 serial_out(port, SPRD_TXD, ch),
631 ({}));
632}
633
634/* this handles the interrupt from one port */
635static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
636{
637 struct uart_port *port = dev_id;
638 unsigned int ims;
639
640 spin_lock(&port->lock);
641
642 ims = serial_in(port, SPRD_IMSR);
643
644 if (!ims) {
645 spin_unlock(&port->lock);
646 return IRQ_NONE;
647 }
648
649 if (ims & SPRD_IMSR_TIMEOUT)
650 serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
651
652 if (ims & SPRD_IMSR_BREAK_DETECT)
653 serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
654
655 if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
656 SPRD_IMSR_TIMEOUT))
657 sprd_rx(port);
658
659 if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
660 sprd_tx(port);
661
662 spin_unlock(&port->lock);
663
664 return IRQ_HANDLED;
665}
666
667static void sprd_uart_dma_startup(struct uart_port *port,
668 struct sprd_uart_port *sp)
669{
670 int ret;
671
672 sprd_request_dma(port);
673 if (!(sp->rx_dma.enable || sp->tx_dma.enable))
674 return;
675
676 ret = sprd_start_dma_rx(port);
677 if (ret) {
678 sp->rx_dma.enable = false;
679 dma_release_channel(sp->rx_dma.chn);
680 dev_warn(port->dev, "fail to start RX dma mode\n");
681 }
682
683 sprd_uart_dma_enable(port, true);
684}
685
686static int sprd_startup(struct uart_port *port)
687{
688 int ret = 0;
689 unsigned int ien, fc;
690 unsigned int timeout;
691 struct sprd_uart_port *sp;
692 unsigned long flags;
693
694 serial_out(port, SPRD_CTL2,
695 THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
696
697 /* clear rx fifo */
698 timeout = SPRD_TIMEOUT;
699 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
700 serial_in(port, SPRD_RXD);
701
702 /* clear tx fifo */
703 timeout = SPRD_TIMEOUT;
704 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
705 cpu_relax();
706
707 /* clear interrupt */
708 serial_out(port, SPRD_IEN, 0);
709 serial_out(port, SPRD_ICLR, ~0);
710
711 /* allocate irq */
712 sp = container_of(port, struct sprd_uart_port, port);
713 snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
714
715 sprd_uart_dma_startup(port, sp);
716
717 ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
718 IRQF_SHARED, sp->name, port);
719 if (ret) {
720 dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
721 port->irq, ret);
722 return ret;
723 }
724 fc = serial_in(port, SPRD_CTL1);
725 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
726 serial_out(port, SPRD_CTL1, fc);
727
728 /* enable interrupt */
729 spin_lock_irqsave(&port->lock, flags);
730 ien = serial_in(port, SPRD_IEN);
731 ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
732 if (!sp->rx_dma.enable)
733 ien |= SPRD_IEN_RX_FULL;
734 serial_out(port, SPRD_IEN, ien);
735 spin_unlock_irqrestore(&port->lock, flags);
736
737 return 0;
738}
739
740static void sprd_shutdown(struct uart_port *port)
741{
742 sprd_release_dma(port);
743 serial_out(port, SPRD_IEN, 0);
744 serial_out(port, SPRD_ICLR, ~0);
745 devm_free_irq(port->dev, port->irq, port);
746}
747
748static void sprd_set_termios(struct uart_port *port, struct ktermios *termios,
749 const struct ktermios *old)
750{
751 unsigned int baud, quot;
752 unsigned int lcr = 0, fc;
753 unsigned long flags;
754
755 /* ask the core to calculate the divisor for us */
756 baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
757
758 quot = port->uartclk / baud;
759
760 /* set data length */
761 switch (termios->c_cflag & CSIZE) {
762 case CS5:
763 lcr |= SPRD_LCR_DATA_LEN5;
764 break;
765 case CS6:
766 lcr |= SPRD_LCR_DATA_LEN6;
767 break;
768 case CS7:
769 lcr |= SPRD_LCR_DATA_LEN7;
770 break;
771 case CS8:
772 default:
773 lcr |= SPRD_LCR_DATA_LEN8;
774 break;
775 }
776
777 /* calculate stop bits */
778 lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
779 if (termios->c_cflag & CSTOPB)
780 lcr |= SPRD_LCR_STOP_2BIT;
781 else
782 lcr |= SPRD_LCR_STOP_1BIT;
783
784 /* calculate parity */
785 lcr &= ~SPRD_LCR_PARITY;
786 termios->c_cflag &= ~CMSPAR; /* no support mark/space */
787 if (termios->c_cflag & PARENB) {
788 lcr |= SPRD_LCR_PARITY_EN;
789 if (termios->c_cflag & PARODD)
790 lcr |= SPRD_LCR_ODD_PAR;
791 else
792 lcr |= SPRD_LCR_EVEN_PAR;
793 }
794
795 spin_lock_irqsave(&port->lock, flags);
796
797 /* update the per-port timeout */
798 uart_update_timeout(port, termios->c_cflag, baud);
799
800 port->read_status_mask = SPRD_LSR_OE;
801 if (termios->c_iflag & INPCK)
802 port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
803 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
804 port->read_status_mask |= SPRD_LSR_BI;
805
806 /* characters to ignore */
807 port->ignore_status_mask = 0;
808 if (termios->c_iflag & IGNPAR)
809 port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
810 if (termios->c_iflag & IGNBRK) {
811 port->ignore_status_mask |= SPRD_LSR_BI;
812 /*
813 * If we're ignoring parity and break indicators,
814 * ignore overruns too (for real raw support).
815 */
816 if (termios->c_iflag & IGNPAR)
817 port->ignore_status_mask |= SPRD_LSR_OE;
818 }
819
820 /* flow control */
821 fc = serial_in(port, SPRD_CTL1);
822 fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
823 if (termios->c_cflag & CRTSCTS) {
824 fc |= RX_HW_FLOW_CTL_THLD;
825 fc |= RX_HW_FLOW_CTL_EN;
826 fc |= TX_HW_FLOW_CTL_EN;
827 }
828
829 /* clock divider bit0~bit15 */
830 serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
831
832 /* clock divider bit16~bit20 */
833 serial_out(port, SPRD_CLKD1,
834 (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
835 serial_out(port, SPRD_LCR, lcr);
836 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
837 serial_out(port, SPRD_CTL1, fc);
838
839 spin_unlock_irqrestore(&port->lock, flags);
840
841 /* Don't rewrite B0 */
842 if (tty_termios_baud_rate(termios))
843 tty_termios_encode_baud_rate(termios, baud, baud);
844}
845
846static const char *sprd_type(struct uart_port *port)
847{
848 return "SPX";
849}
850
851static void sprd_release_port(struct uart_port *port)
852{
853 /* nothing to do */
854}
855
856static int sprd_request_port(struct uart_port *port)
857{
858 return 0;
859}
860
861static void sprd_config_port(struct uart_port *port, int flags)
862{
863 if (flags & UART_CONFIG_TYPE)
864 port->type = PORT_SPRD;
865}
866
867static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
868{
869 if (ser->type != PORT_SPRD)
870 return -EINVAL;
871 if (port->irq != ser->irq)
872 return -EINVAL;
873 if (port->iotype != ser->io_type)
874 return -EINVAL;
875 return 0;
876}
877
878static void sprd_pm(struct uart_port *port, unsigned int state,
879 unsigned int oldstate)
880{
881 struct sprd_uart_port *sup =
882 container_of(port, struct sprd_uart_port, port);
883
884 switch (state) {
885 case UART_PM_STATE_ON:
886 clk_prepare_enable(sup->clk);
887 break;
888 case UART_PM_STATE_OFF:
889 clk_disable_unprepare(sup->clk);
890 break;
891 }
892}
893
894#ifdef CONFIG_CONSOLE_POLL
895static int sprd_poll_init(struct uart_port *port)
896{
897 if (port->state->pm_state != UART_PM_STATE_ON) {
898 sprd_pm(port, UART_PM_STATE_ON, 0);
899 port->state->pm_state = UART_PM_STATE_ON;
900 }
901
902 return 0;
903}
904
905static int sprd_poll_get_char(struct uart_port *port)
906{
907 while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
908 cpu_relax();
909
910 return serial_in(port, SPRD_RXD);
911}
912
913static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
914{
915 while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
916 cpu_relax();
917
918 serial_out(port, SPRD_TXD, ch);
919}
920#endif
921
922static const struct uart_ops serial_sprd_ops = {
923 .tx_empty = sprd_tx_empty,
924 .get_mctrl = sprd_get_mctrl,
925 .set_mctrl = sprd_set_mctrl,
926 .stop_tx = sprd_stop_tx,
927 .start_tx = sprd_start_tx,
928 .stop_rx = sprd_stop_rx,
929 .break_ctl = sprd_break_ctl,
930 .startup = sprd_startup,
931 .shutdown = sprd_shutdown,
932 .set_termios = sprd_set_termios,
933 .type = sprd_type,
934 .release_port = sprd_release_port,
935 .request_port = sprd_request_port,
936 .config_port = sprd_config_port,
937 .verify_port = sprd_verify_port,
938 .pm = sprd_pm,
939#ifdef CONFIG_CONSOLE_POLL
940 .poll_init = sprd_poll_init,
941 .poll_get_char = sprd_poll_get_char,
942 .poll_put_char = sprd_poll_put_char,
943#endif
944};
945
946#ifdef CONFIG_SERIAL_SPRD_CONSOLE
947static void wait_for_xmitr(struct uart_port *port)
948{
949 unsigned int status, tmout = 10000;
950
951 /* wait up to 10ms for the character(s) to be sent */
952 do {
953 status = serial_in(port, SPRD_STS1);
954 if (--tmout == 0)
955 break;
956 udelay(1);
957 } while (status & SPRD_TX_FIFO_CNT_MASK);
958}
959
960static void sprd_console_putchar(struct uart_port *port, unsigned char ch)
961{
962 wait_for_xmitr(port);
963 serial_out(port, SPRD_TXD, ch);
964}
965
966static void sprd_console_write(struct console *co, const char *s,
967 unsigned int count)
968{
969 struct uart_port *port = &sprd_port[co->index]->port;
970 int locked = 1;
971 unsigned long flags;
972
973 if (port->sysrq)
974 locked = 0;
975 else if (oops_in_progress)
976 locked = spin_trylock_irqsave(&port->lock, flags);
977 else
978 spin_lock_irqsave(&port->lock, flags);
979
980 uart_console_write(port, s, count, sprd_console_putchar);
981
982 /* wait for transmitter to become empty */
983 wait_for_xmitr(port);
984
985 if (locked)
986 spin_unlock_irqrestore(&port->lock, flags);
987}
988
989static int sprd_console_setup(struct console *co, char *options)
990{
991 struct sprd_uart_port *sprd_uart_port;
992 int baud = 115200;
993 int bits = 8;
994 int parity = 'n';
995 int flow = 'n';
996
997 if (co->index >= UART_NR_MAX || co->index < 0)
998 co->index = 0;
999
1000 sprd_uart_port = sprd_port[co->index];
1001 if (!sprd_uart_port || !sprd_uart_port->port.membase) {
1002 pr_info("serial port %d not yet initialized\n", co->index);
1003 return -ENODEV;
1004 }
1005
1006 if (options)
1007 uart_parse_options(options, &baud, &parity, &bits, &flow);
1008
1009 return uart_set_options(&sprd_uart_port->port, co, baud,
1010 parity, bits, flow);
1011}
1012
1013static struct uart_driver sprd_uart_driver;
1014static struct console sprd_console = {
1015 .name = SPRD_TTY_NAME,
1016 .write = sprd_console_write,
1017 .device = uart_console_device,
1018 .setup = sprd_console_setup,
1019 .flags = CON_PRINTBUFFER,
1020 .index = -1,
1021 .data = &sprd_uart_driver,
1022};
1023
1024static int __init sprd_serial_console_init(void)
1025{
1026 register_console(&sprd_console);
1027 return 0;
1028}
1029console_initcall(sprd_serial_console_init);
1030
1031#define SPRD_CONSOLE (&sprd_console)
1032
1033/* Support for earlycon */
1034static void sprd_putc(struct uart_port *port, unsigned char c)
1035{
1036 unsigned int timeout = SPRD_TIMEOUT;
1037
1038 while (timeout-- &&
1039 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
1040 cpu_relax();
1041
1042 writeb(c, port->membase + SPRD_TXD);
1043}
1044
1045static void sprd_early_write(struct console *con, const char *s, unsigned int n)
1046{
1047 struct earlycon_device *dev = con->data;
1048
1049 uart_console_write(&dev->port, s, n, sprd_putc);
1050}
1051
1052static int __init sprd_early_console_setup(struct earlycon_device *device,
1053 const char *opt)
1054{
1055 if (!device->port.membase)
1056 return -ENODEV;
1057
1058 device->con->write = sprd_early_write;
1059 return 0;
1060}
1061OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
1062 sprd_early_console_setup);
1063
1064#else /* !CONFIG_SERIAL_SPRD_CONSOLE */
1065#define SPRD_CONSOLE NULL
1066#endif
1067
1068static struct uart_driver sprd_uart_driver = {
1069 .owner = THIS_MODULE,
1070 .driver_name = "sprd_serial",
1071 .dev_name = SPRD_TTY_NAME,
1072 .major = 0,
1073 .minor = 0,
1074 .nr = UART_NR_MAX,
1075 .cons = SPRD_CONSOLE,
1076};
1077
1078static int sprd_remove(struct platform_device *dev)
1079{
1080 struct sprd_uart_port *sup = platform_get_drvdata(dev);
1081
1082 if (sup) {
1083 uart_remove_one_port(&sprd_uart_driver, &sup->port);
1084 sprd_port[sup->port.line] = NULL;
1085 sprd_rx_free_buf(sup);
1086 sprd_ports_num--;
1087 }
1088
1089 if (!sprd_ports_num)
1090 uart_unregister_driver(&sprd_uart_driver);
1091
1092 return 0;
1093}
1094
1095static bool sprd_uart_is_console(struct uart_port *uport)
1096{
1097 struct console *cons = sprd_uart_driver.cons;
1098
1099 if ((cons && cons->index >= 0 && cons->index == uport->line) ||
1100 of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
1101 return true;
1102
1103 return false;
1104}
1105
1106static int sprd_clk_init(struct uart_port *uport)
1107{
1108 struct clk *clk_uart, *clk_parent;
1109 struct sprd_uart_port *u = sprd_port[uport->line];
1110
1111 clk_uart = devm_clk_get(uport->dev, "uart");
1112 if (IS_ERR(clk_uart)) {
1113 dev_warn(uport->dev, "uart%d can't get uart clock\n",
1114 uport->line);
1115 clk_uart = NULL;
1116 }
1117
1118 clk_parent = devm_clk_get(uport->dev, "source");
1119 if (IS_ERR(clk_parent)) {
1120 dev_warn(uport->dev, "uart%d can't get source clock\n",
1121 uport->line);
1122 clk_parent = NULL;
1123 }
1124
1125 if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
1126 uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
1127 else
1128 uport->uartclk = clk_get_rate(clk_uart);
1129
1130 u->clk = devm_clk_get(uport->dev, "enable");
1131 if (IS_ERR(u->clk)) {
1132 if (PTR_ERR(u->clk) == -EPROBE_DEFER)
1133 return -EPROBE_DEFER;
1134
1135 dev_warn(uport->dev, "uart%d can't get enable clock\n",
1136 uport->line);
1137
1138 /* To keep console alive even if the error occurred */
1139 if (!sprd_uart_is_console(uport))
1140 return PTR_ERR(u->clk);
1141
1142 u->clk = NULL;
1143 }
1144
1145 return 0;
1146}
1147
1148static int sprd_probe(struct platform_device *pdev)
1149{
1150 struct resource *res;
1151 struct uart_port *up;
1152 int irq;
1153 int index;
1154 int ret;
1155
1156 index = of_alias_get_id(pdev->dev.of_node, "serial");
1157 if (index < 0 || index >= ARRAY_SIZE(sprd_port)) {
1158 dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
1159 return -EINVAL;
1160 }
1161
1162 sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]),
1163 GFP_KERNEL);
1164 if (!sprd_port[index])
1165 return -ENOMEM;
1166
1167 up = &sprd_port[index]->port;
1168 up->dev = &pdev->dev;
1169 up->line = index;
1170 up->type = PORT_SPRD;
1171 up->iotype = UPIO_MEM;
1172 up->uartclk = SPRD_DEF_RATE;
1173 up->fifosize = SPRD_FIFO_SIZE;
1174 up->ops = &serial_sprd_ops;
1175 up->flags = UPF_BOOT_AUTOCONF;
1176 up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
1177
1178 ret = sprd_clk_init(up);
1179 if (ret)
1180 return ret;
1181
1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 up->membase = devm_ioremap_resource(&pdev->dev, res);
1184 if (IS_ERR(up->membase))
1185 return PTR_ERR(up->membase);
1186
1187 up->mapbase = res->start;
1188
1189 irq = platform_get_irq(pdev, 0);
1190 if (irq < 0)
1191 return irq;
1192 up->irq = irq;
1193
1194 /*
1195 * Allocate one dma buffer to prepare for receive transfer, in case
1196 * memory allocation failure at runtime.
1197 */
1198 ret = sprd_rx_alloc_buf(sprd_port[index]);
1199 if (ret)
1200 return ret;
1201
1202 if (!sprd_ports_num) {
1203 ret = uart_register_driver(&sprd_uart_driver);
1204 if (ret < 0) {
1205 pr_err("Failed to register SPRD-UART driver\n");
1206 return ret;
1207 }
1208 }
1209 sprd_ports_num++;
1210
1211 ret = uart_add_one_port(&sprd_uart_driver, up);
1212 if (ret)
1213 sprd_remove(pdev);
1214
1215 platform_set_drvdata(pdev, up);
1216
1217 return ret;
1218}
1219
1220#ifdef CONFIG_PM_SLEEP
1221static int sprd_suspend(struct device *dev)
1222{
1223 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1224
1225 uart_suspend_port(&sprd_uart_driver, &sup->port);
1226
1227 return 0;
1228}
1229
1230static int sprd_resume(struct device *dev)
1231{
1232 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1233
1234 uart_resume_port(&sprd_uart_driver, &sup->port);
1235
1236 return 0;
1237}
1238#endif
1239
1240static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
1241
1242static const struct of_device_id serial_ids[] = {
1243 {.compatible = "sprd,sc9836-uart",},
1244 {}
1245};
1246MODULE_DEVICE_TABLE(of, serial_ids);
1247
1248static struct platform_driver sprd_platform_driver = {
1249 .probe = sprd_probe,
1250 .remove = sprd_remove,
1251 .driver = {
1252 .name = "sprd_serial",
1253 .of_match_table = of_match_ptr(serial_ids),
1254 .pm = &sprd_pm_ops,
1255 },
1256};
1257
1258module_platform_driver(sprd_platform_driver);
1259
1260MODULE_LICENSE("GPL v2");
1261MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");