tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>
9#include <linux/net_tstamp.h>
10#include <linux/if_vlan.h>
11#include <linux/regmap.h>
12#include <net/dsa.h>
13
14/* Port Group IDs (PGID) are masks of destination ports.
15 *
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
18 * AND of all 3 PGIDs.
19 *
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
25 * that matched.
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
37 * ports mask.
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53/* Reserve some destination PGIDs at the end of the range:
54 * PGID_BLACKHOLE: used for not forwarding the frames
55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
56 * of the switch port net devices, towards the CPU port module.
57 * PGID_UC: the flooding destinations for unknown unicast traffic.
58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 * PGID_BC: the flooding destinations for broadcast traffic.
62 */
63#define PGID_BLACKHOLE 57
64#define PGID_CPU 58
65#define PGID_UC 59
66#define PGID_MC 60
67#define PGID_MCIPV4 61
68#define PGID_MCIPV6 62
69#define PGID_BC 63
70
71#define for_each_unicast_dest_pgid(ocelot, pgid) \
72 for ((pgid) = 0; \
73 (pgid) < (ocelot)->num_phys_ports; \
74 (pgid)++)
75
76#define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
77 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 (pgid) < PGID_BLACKHOLE; \
79 (pgid)++)
80
81#define for_each_aggr_pgid(ocelot, pgid) \
82 for ((pgid) = PGID_AGGR; \
83 (pgid) < PGID_SRC; \
84 (pgid)++)
85
86/* Aggregation PGIDs, one per Link Aggregation Code */
87#define PGID_AGGR 64
88
89/* Source PGIDs, one per physical port */
90#define PGID_SRC 80
91
92#define OCELOT_NUM_TC 8
93
94#define OCELOT_SPEED_2500 0
95#define OCELOT_SPEED_1000 1
96#define OCELOT_SPEED_100 2
97#define OCELOT_SPEED_10 3
98
99#define OCELOT_PTP_PINS_NUM 4
100
101#define TARGET_OFFSET 24
102#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
103#define REG(reg, offset) [reg & REG_MASK] = offset
104
105#define REG_RESERVED_ADDR 0xffffffff
106#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
107
108enum ocelot_target {
109 ANA = 1,
110 QS,
111 QSYS,
112 REW,
113 SYS,
114 S0,
115 S1,
116 S2,
117 HSIO,
118 PTP,
119 FDMA,
120 GCB,
121 DEV_GMII,
122 TARGET_MAX,
123};
124
125enum ocelot_reg {
126 ANA_ADVLEARN = ANA << TARGET_OFFSET,
127 ANA_VLANMASK,
128 ANA_PORT_B_DOMAIN,
129 ANA_ANAGEFIL,
130 ANA_ANEVENTS,
131 ANA_STORMLIMIT_BURST,
132 ANA_STORMLIMIT_CFG,
133 ANA_ISOLATED_PORTS,
134 ANA_COMMUNITY_PORTS,
135 ANA_AUTOAGE,
136 ANA_MACTOPTIONS,
137 ANA_LEARNDISC,
138 ANA_AGENCTRL,
139 ANA_MIRRORPORTS,
140 ANA_EMIRRORPORTS,
141 ANA_FLOODING,
142 ANA_FLOODING_IPMC,
143 ANA_SFLOW_CFG,
144 ANA_PORT_MODE,
145 ANA_CUT_THRU_CFG,
146 ANA_PGID_PGID,
147 ANA_TABLES_ANMOVED,
148 ANA_TABLES_MACHDATA,
149 ANA_TABLES_MACLDATA,
150 ANA_TABLES_STREAMDATA,
151 ANA_TABLES_MACACCESS,
152 ANA_TABLES_MACTINDX,
153 ANA_TABLES_VLANACCESS,
154 ANA_TABLES_VLANTIDX,
155 ANA_TABLES_ISDXACCESS,
156 ANA_TABLES_ISDXTIDX,
157 ANA_TABLES_ENTRYLIM,
158 ANA_TABLES_PTP_ID_HIGH,
159 ANA_TABLES_PTP_ID_LOW,
160 ANA_TABLES_STREAMACCESS,
161 ANA_TABLES_STREAMTIDX,
162 ANA_TABLES_SEQ_HISTORY,
163 ANA_TABLES_SEQ_MASK,
164 ANA_TABLES_SFID_MASK,
165 ANA_TABLES_SFIDACCESS,
166 ANA_TABLES_SFIDTIDX,
167 ANA_MSTI_STATE,
168 ANA_OAM_UPM_LM_CNT,
169 ANA_SG_ACCESS_CTRL,
170 ANA_SG_CONFIG_REG_1,
171 ANA_SG_CONFIG_REG_2,
172 ANA_SG_CONFIG_REG_3,
173 ANA_SG_CONFIG_REG_4,
174 ANA_SG_CONFIG_REG_5,
175 ANA_SG_GCL_GS_CONFIG,
176 ANA_SG_GCL_TI_CONFIG,
177 ANA_SG_STATUS_REG_1,
178 ANA_SG_STATUS_REG_2,
179 ANA_SG_STATUS_REG_3,
180 ANA_PORT_VLAN_CFG,
181 ANA_PORT_DROP_CFG,
182 ANA_PORT_QOS_CFG,
183 ANA_PORT_VCAP_CFG,
184 ANA_PORT_VCAP_S1_KEY_CFG,
185 ANA_PORT_VCAP_S2_CFG,
186 ANA_PORT_PCP_DEI_MAP,
187 ANA_PORT_CPU_FWD_CFG,
188 ANA_PORT_CPU_FWD_BPDU_CFG,
189 ANA_PORT_CPU_FWD_GARP_CFG,
190 ANA_PORT_CPU_FWD_CCM_CFG,
191 ANA_PORT_PORT_CFG,
192 ANA_PORT_POL_CFG,
193 ANA_PORT_PTP_CFG,
194 ANA_PORT_PTP_DLY1_CFG,
195 ANA_PORT_PTP_DLY2_CFG,
196 ANA_PORT_SFID_CFG,
197 ANA_PFC_PFC_CFG,
198 ANA_PFC_PFC_TIMER,
199 ANA_IPT_OAM_MEP_CFG,
200 ANA_IPT_IPT,
201 ANA_PPT_PPT,
202 ANA_FID_MAP_FID_MAP,
203 ANA_AGGR_CFG,
204 ANA_CPUQ_CFG,
205 ANA_CPUQ_CFG2,
206 ANA_CPUQ_8021_CFG,
207 ANA_DSCP_CFG,
208 ANA_DSCP_REWR_CFG,
209 ANA_VCAP_RNG_TYPE_CFG,
210 ANA_VCAP_RNG_VAL_CFG,
211 ANA_VRAP_CFG,
212 ANA_VRAP_HDR_DATA,
213 ANA_VRAP_HDR_MASK,
214 ANA_DISCARD_CFG,
215 ANA_FID_CFG,
216 ANA_POL_PIR_CFG,
217 ANA_POL_CIR_CFG,
218 ANA_POL_MODE_CFG,
219 ANA_POL_PIR_STATE,
220 ANA_POL_CIR_STATE,
221 ANA_POL_STATE,
222 ANA_POL_FLOWC,
223 ANA_POL_HYST,
224 ANA_POL_MISC_CFG,
225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
226 QS_XTR_RD,
227 QS_XTR_FRM_PRUNING,
228 QS_XTR_FLUSH,
229 QS_XTR_DATA_PRESENT,
230 QS_XTR_CFG,
231 QS_INJ_GRP_CFG,
232 QS_INJ_WR,
233 QS_INJ_CTRL,
234 QS_INJ_STATUS,
235 QS_INJ_ERR,
236 QS_INH_DBG,
237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
238 QSYS_SWITCH_PORT_MODE,
239 QSYS_STAT_CNT_CFG,
240 QSYS_EEE_CFG,
241 QSYS_EEE_THRES,
242 QSYS_IGR_NO_SHARING,
243 QSYS_EGR_NO_SHARING,
244 QSYS_SW_STATUS,
245 QSYS_EXT_CPU_CFG,
246 QSYS_PAD_CFG,
247 QSYS_CPU_GROUP_MAP,
248 QSYS_QMAP,
249 QSYS_ISDX_SGRP,
250 QSYS_TIMED_FRAME_ENTRY,
251 QSYS_TFRM_MISC,
252 QSYS_TFRM_PORT_DLY,
253 QSYS_TFRM_TIMER_CFG_1,
254 QSYS_TFRM_TIMER_CFG_2,
255 QSYS_TFRM_TIMER_CFG_3,
256 QSYS_TFRM_TIMER_CFG_4,
257 QSYS_TFRM_TIMER_CFG_5,
258 QSYS_TFRM_TIMER_CFG_6,
259 QSYS_TFRM_TIMER_CFG_7,
260 QSYS_TFRM_TIMER_CFG_8,
261 QSYS_RED_PROFILE,
262 QSYS_RES_QOS_MODE,
263 QSYS_RES_CFG,
264 QSYS_RES_STAT,
265 QSYS_EGR_DROP_MODE,
266 QSYS_EQ_CTRL,
267 QSYS_EVENTS_CORE,
268 QSYS_QMAXSDU_CFG_0,
269 QSYS_QMAXSDU_CFG_1,
270 QSYS_QMAXSDU_CFG_2,
271 QSYS_QMAXSDU_CFG_3,
272 QSYS_QMAXSDU_CFG_4,
273 QSYS_QMAXSDU_CFG_5,
274 QSYS_QMAXSDU_CFG_6,
275 QSYS_QMAXSDU_CFG_7,
276 QSYS_PREEMPTION_CFG,
277 QSYS_CIR_CFG,
278 QSYS_EIR_CFG,
279 QSYS_SE_CFG,
280 QSYS_SE_DWRR_CFG,
281 QSYS_SE_CONNECT,
282 QSYS_SE_DLB_SENSE,
283 QSYS_CIR_STATE,
284 QSYS_EIR_STATE,
285 QSYS_SE_STATE,
286 QSYS_HSCH_MISC_CFG,
287 QSYS_TAG_CONFIG,
288 QSYS_TAS_PARAM_CFG_CTRL,
289 QSYS_PORT_MAX_SDU,
290 QSYS_PARAM_CFG_REG_1,
291 QSYS_PARAM_CFG_REG_2,
292 QSYS_PARAM_CFG_REG_3,
293 QSYS_PARAM_CFG_REG_4,
294 QSYS_PARAM_CFG_REG_5,
295 QSYS_GCL_CFG_REG_1,
296 QSYS_GCL_CFG_REG_2,
297 QSYS_PARAM_STATUS_REG_1,
298 QSYS_PARAM_STATUS_REG_2,
299 QSYS_PARAM_STATUS_REG_3,
300 QSYS_PARAM_STATUS_REG_4,
301 QSYS_PARAM_STATUS_REG_5,
302 QSYS_PARAM_STATUS_REG_6,
303 QSYS_PARAM_STATUS_REG_7,
304 QSYS_PARAM_STATUS_REG_8,
305 QSYS_PARAM_STATUS_REG_9,
306 QSYS_GCL_STATUS_REG_1,
307 QSYS_GCL_STATUS_REG_2,
308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
309 REW_TAG_CFG,
310 REW_PORT_CFG,
311 REW_DSCP_CFG,
312 REW_PCP_DEI_QOS_MAP_CFG,
313 REW_PTP_CFG,
314 REW_PTP_DLY1_CFG,
315 REW_RED_TAG_CFG,
316 REW_DSCP_REMAP_DP1_CFG,
317 REW_DSCP_REMAP_CFG,
318 REW_STAT_CFG,
319 REW_REW_STICKY,
320 REW_PPT,
321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
322 SYS_COUNT_RX_UNICAST,
323 SYS_COUNT_RX_MULTICAST,
324 SYS_COUNT_RX_BROADCAST,
325 SYS_COUNT_RX_SHORTS,
326 SYS_COUNT_RX_FRAGMENTS,
327 SYS_COUNT_RX_JABBERS,
328 SYS_COUNT_RX_CRC_ALIGN_ERRS,
329 SYS_COUNT_RX_SYM_ERRS,
330 SYS_COUNT_RX_64,
331 SYS_COUNT_RX_65_127,
332 SYS_COUNT_RX_128_255,
333 SYS_COUNT_RX_256_511,
334 SYS_COUNT_RX_512_1023,
335 SYS_COUNT_RX_1024_1526,
336 SYS_COUNT_RX_1527_MAX,
337 SYS_COUNT_RX_PAUSE,
338 SYS_COUNT_RX_CONTROL,
339 SYS_COUNT_RX_LONGS,
340 SYS_COUNT_RX_CLASSIFIED_DROPS,
341 SYS_COUNT_RX_RED_PRIO_0,
342 SYS_COUNT_RX_RED_PRIO_1,
343 SYS_COUNT_RX_RED_PRIO_2,
344 SYS_COUNT_RX_RED_PRIO_3,
345 SYS_COUNT_RX_RED_PRIO_4,
346 SYS_COUNT_RX_RED_PRIO_5,
347 SYS_COUNT_RX_RED_PRIO_6,
348 SYS_COUNT_RX_RED_PRIO_7,
349 SYS_COUNT_RX_YELLOW_PRIO_0,
350 SYS_COUNT_RX_YELLOW_PRIO_1,
351 SYS_COUNT_RX_YELLOW_PRIO_2,
352 SYS_COUNT_RX_YELLOW_PRIO_3,
353 SYS_COUNT_RX_YELLOW_PRIO_4,
354 SYS_COUNT_RX_YELLOW_PRIO_5,
355 SYS_COUNT_RX_YELLOW_PRIO_6,
356 SYS_COUNT_RX_YELLOW_PRIO_7,
357 SYS_COUNT_RX_GREEN_PRIO_0,
358 SYS_COUNT_RX_GREEN_PRIO_1,
359 SYS_COUNT_RX_GREEN_PRIO_2,
360 SYS_COUNT_RX_GREEN_PRIO_3,
361 SYS_COUNT_RX_GREEN_PRIO_4,
362 SYS_COUNT_RX_GREEN_PRIO_5,
363 SYS_COUNT_RX_GREEN_PRIO_6,
364 SYS_COUNT_RX_GREEN_PRIO_7,
365 SYS_COUNT_TX_OCTETS,
366 SYS_COUNT_TX_UNICAST,
367 SYS_COUNT_TX_MULTICAST,
368 SYS_COUNT_TX_BROADCAST,
369 SYS_COUNT_TX_COLLISION,
370 SYS_COUNT_TX_DROPS,
371 SYS_COUNT_TX_PAUSE,
372 SYS_COUNT_TX_64,
373 SYS_COUNT_TX_65_127,
374 SYS_COUNT_TX_128_255,
375 SYS_COUNT_TX_256_511,
376 SYS_COUNT_TX_512_1023,
377 SYS_COUNT_TX_1024_1526,
378 SYS_COUNT_TX_1527_MAX,
379 SYS_COUNT_TX_YELLOW_PRIO_0,
380 SYS_COUNT_TX_YELLOW_PRIO_1,
381 SYS_COUNT_TX_YELLOW_PRIO_2,
382 SYS_COUNT_TX_YELLOW_PRIO_3,
383 SYS_COUNT_TX_YELLOW_PRIO_4,
384 SYS_COUNT_TX_YELLOW_PRIO_5,
385 SYS_COUNT_TX_YELLOW_PRIO_6,
386 SYS_COUNT_TX_YELLOW_PRIO_7,
387 SYS_COUNT_TX_GREEN_PRIO_0,
388 SYS_COUNT_TX_GREEN_PRIO_1,
389 SYS_COUNT_TX_GREEN_PRIO_2,
390 SYS_COUNT_TX_GREEN_PRIO_3,
391 SYS_COUNT_TX_GREEN_PRIO_4,
392 SYS_COUNT_TX_GREEN_PRIO_5,
393 SYS_COUNT_TX_GREEN_PRIO_6,
394 SYS_COUNT_TX_GREEN_PRIO_7,
395 SYS_COUNT_TX_AGED,
396 SYS_COUNT_DROP_LOCAL,
397 SYS_COUNT_DROP_TAIL,
398 SYS_COUNT_DROP_YELLOW_PRIO_0,
399 SYS_COUNT_DROP_YELLOW_PRIO_1,
400 SYS_COUNT_DROP_YELLOW_PRIO_2,
401 SYS_COUNT_DROP_YELLOW_PRIO_3,
402 SYS_COUNT_DROP_YELLOW_PRIO_4,
403 SYS_COUNT_DROP_YELLOW_PRIO_5,
404 SYS_COUNT_DROP_YELLOW_PRIO_6,
405 SYS_COUNT_DROP_YELLOW_PRIO_7,
406 SYS_COUNT_DROP_GREEN_PRIO_0,
407 SYS_COUNT_DROP_GREEN_PRIO_1,
408 SYS_COUNT_DROP_GREEN_PRIO_2,
409 SYS_COUNT_DROP_GREEN_PRIO_3,
410 SYS_COUNT_DROP_GREEN_PRIO_4,
411 SYS_COUNT_DROP_GREEN_PRIO_5,
412 SYS_COUNT_DROP_GREEN_PRIO_6,
413 SYS_COUNT_DROP_GREEN_PRIO_7,
414 SYS_COUNT_SF_MATCHING_FRAMES,
415 SYS_COUNT_SF_NOT_PASSING_FRAMES,
416 SYS_COUNT_SF_NOT_PASSING_SDU,
417 SYS_COUNT_SF_RED_FRAMES,
418 SYS_RESET_CFG,
419 SYS_SR_ETYPE_CFG,
420 SYS_VLAN_ETYPE_CFG,
421 SYS_PORT_MODE,
422 SYS_FRONT_PORT_MODE,
423 SYS_FRM_AGING,
424 SYS_STAT_CFG,
425 SYS_SW_STATUS,
426 SYS_MISC_CFG,
427 SYS_REW_MAC_HIGH_CFG,
428 SYS_REW_MAC_LOW_CFG,
429 SYS_TIMESTAMP_OFFSET,
430 SYS_CMID,
431 SYS_PAUSE_CFG,
432 SYS_PAUSE_TOT_CFG,
433 SYS_ATOP,
434 SYS_ATOP_TOT_CFG,
435 SYS_MAC_FC_CFG,
436 SYS_MMGT,
437 SYS_MMGT_FAST,
438 SYS_EVENTS_DIF,
439 SYS_EVENTS_CORE,
440 SYS_PTP_STATUS,
441 SYS_PTP_TXSTAMP,
442 SYS_PTP_NXT,
443 SYS_PTP_CFG,
444 SYS_RAM_INIT,
445 SYS_CM_ADDR,
446 SYS_CM_DATA_WR,
447 SYS_CM_DATA_RD,
448 SYS_CM_OP,
449 SYS_CM_DATA,
450 PTP_PIN_CFG = PTP << TARGET_OFFSET,
451 PTP_PIN_TOD_SEC_MSB,
452 PTP_PIN_TOD_SEC_LSB,
453 PTP_PIN_TOD_NSEC,
454 PTP_PIN_WF_HIGH_PERIOD,
455 PTP_PIN_WF_LOW_PERIOD,
456 PTP_CFG_MISC,
457 PTP_CLK_CFG_ADJ_CFG,
458 PTP_CLK_CFG_ADJ_FREQ,
459 GCB_SOFT_RST = GCB << TARGET_OFFSET,
460 GCB_MIIM_MII_STATUS,
461 GCB_MIIM_MII_CMD,
462 GCB_MIIM_MII_DATA,
463 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
464 DEV_PORT_MISC,
465 DEV_EVENTS,
466 DEV_EEE_CFG,
467 DEV_RX_PATH_DELAY,
468 DEV_TX_PATH_DELAY,
469 DEV_PTP_PREDICT_CFG,
470 DEV_MAC_ENA_CFG,
471 DEV_MAC_MODE_CFG,
472 DEV_MAC_MAXLEN_CFG,
473 DEV_MAC_TAGS_CFG,
474 DEV_MAC_ADV_CHK_CFG,
475 DEV_MAC_IFG_CFG,
476 DEV_MAC_HDX_CFG,
477 DEV_MAC_DBG_CFG,
478 DEV_MAC_FC_MAC_LOW_CFG,
479 DEV_MAC_FC_MAC_HIGH_CFG,
480 DEV_MAC_STICKY,
481 PCS1G_CFG,
482 PCS1G_MODE_CFG,
483 PCS1G_SD_CFG,
484 PCS1G_ANEG_CFG,
485 PCS1G_ANEG_NP_CFG,
486 PCS1G_LB_CFG,
487 PCS1G_DBG_CFG,
488 PCS1G_CDET_CFG,
489 PCS1G_ANEG_STATUS,
490 PCS1G_ANEG_NP_STATUS,
491 PCS1G_LINK_STATUS,
492 PCS1G_LINK_DOWN_CNT,
493 PCS1G_STICKY,
494 PCS1G_DEBUG_STATUS,
495 PCS1G_LPI_CFG,
496 PCS1G_LPI_WAKE_ERROR_CNT,
497 PCS1G_LPI_STATUS,
498 PCS1G_TSTPAT_MODE_CFG,
499 PCS1G_TSTPAT_STATUS,
500 DEV_PCS_FX100_CFG,
501 DEV_PCS_FX100_STATUS,
502};
503
504enum ocelot_regfield {
505 ANA_ADVLEARN_VLAN_CHK,
506 ANA_ADVLEARN_LEARN_MIRROR,
507 ANA_ANEVENTS_FLOOD_DISCARD,
508 ANA_ANEVENTS_MSTI_DROP,
509 ANA_ANEVENTS_ACLKILL,
510 ANA_ANEVENTS_ACLUSED,
511 ANA_ANEVENTS_AUTOAGE,
512 ANA_ANEVENTS_VS2TTL1,
513 ANA_ANEVENTS_STORM_DROP,
514 ANA_ANEVENTS_LEARN_DROP,
515 ANA_ANEVENTS_AGED_ENTRY,
516 ANA_ANEVENTS_CPU_LEARN_FAILED,
517 ANA_ANEVENTS_AUTO_LEARN_FAILED,
518 ANA_ANEVENTS_LEARN_REMOVE,
519 ANA_ANEVENTS_AUTO_LEARNED,
520 ANA_ANEVENTS_AUTO_MOVED,
521 ANA_ANEVENTS_DROPPED,
522 ANA_ANEVENTS_CLASSIFIED_DROP,
523 ANA_ANEVENTS_CLASSIFIED_COPY,
524 ANA_ANEVENTS_VLAN_DISCARD,
525 ANA_ANEVENTS_FWD_DISCARD,
526 ANA_ANEVENTS_MULTICAST_FLOOD,
527 ANA_ANEVENTS_UNICAST_FLOOD,
528 ANA_ANEVENTS_DEST_KNOWN,
529 ANA_ANEVENTS_BUCKET3_MATCH,
530 ANA_ANEVENTS_BUCKET2_MATCH,
531 ANA_ANEVENTS_BUCKET1_MATCH,
532 ANA_ANEVENTS_BUCKET0_MATCH,
533 ANA_ANEVENTS_CPU_OPERATION,
534 ANA_ANEVENTS_DMAC_LOOKUP,
535 ANA_ANEVENTS_SMAC_LOOKUP,
536 ANA_ANEVENTS_SEQ_GEN_ERR_0,
537 ANA_ANEVENTS_SEQ_GEN_ERR_1,
538 ANA_TABLES_MACACCESS_B_DOM,
539 ANA_TABLES_MACTINDX_BUCKET,
540 ANA_TABLES_MACTINDX_M_INDEX,
541 QSYS_SWITCH_PORT_MODE_PORT_ENA,
542 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
543 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
544 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
545 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
546 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
547 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
548 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
549 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
550 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
551 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
552 SYS_PORT_MODE_DATA_WO_TS,
553 SYS_PORT_MODE_INCL_INJ_HDR,
554 SYS_PORT_MODE_INCL_XTR_HDR,
555 SYS_PORT_MODE_INCL_HDR_ERR,
556 SYS_RESET_CFG_CORE_ENA,
557 SYS_RESET_CFG_MEM_ENA,
558 SYS_RESET_CFG_MEM_INIT,
559 GCB_SOFT_RST_SWC_RST,
560 GCB_MIIM_MII_STATUS_PENDING,
561 GCB_MIIM_MII_STATUS_BUSY,
562 SYS_PAUSE_CFG_PAUSE_START,
563 SYS_PAUSE_CFG_PAUSE_STOP,
564 SYS_PAUSE_CFG_PAUSE_ENA,
565 REGFIELD_MAX
566};
567
568enum {
569 /* VCAP_CORE_CFG */
570 VCAP_CORE_UPDATE_CTRL,
571 VCAP_CORE_MV_CFG,
572 /* VCAP_CORE_CACHE */
573 VCAP_CACHE_ENTRY_DAT,
574 VCAP_CACHE_MASK_DAT,
575 VCAP_CACHE_ACTION_DAT,
576 VCAP_CACHE_CNT_DAT,
577 VCAP_CACHE_TG_DAT,
578 /* VCAP_CONST */
579 VCAP_CONST_VCAP_VER,
580 VCAP_CONST_ENTRY_WIDTH,
581 VCAP_CONST_ENTRY_CNT,
582 VCAP_CONST_ENTRY_SWCNT,
583 VCAP_CONST_ENTRY_TG_WIDTH,
584 VCAP_CONST_ACTION_DEF_CNT,
585 VCAP_CONST_ACTION_WIDTH,
586 VCAP_CONST_CNT_WIDTH,
587 VCAP_CONST_CORE_CNT,
588 VCAP_CONST_IF_CNT,
589};
590
591enum ocelot_ptp_pins {
592 PTP_PIN_0,
593 PTP_PIN_1,
594 PTP_PIN_2,
595 PTP_PIN_3,
596 TOD_ACC_PIN
597};
598
599enum ocelot_tag_prefix {
600 OCELOT_TAG_PREFIX_DISABLED = 0,
601 OCELOT_TAG_PREFIX_NONE,
602 OCELOT_TAG_PREFIX_SHORT,
603 OCELOT_TAG_PREFIX_LONG,
604};
605
606struct ocelot;
607
608struct ocelot_ops {
609 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
610 int (*netdev_to_port)(struct net_device *dev);
611 int (*reset)(struct ocelot *ocelot);
612 u16 (*wm_enc)(u16 value);
613 u16 (*wm_dec)(u16 value);
614 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
615 void (*psfp_init)(struct ocelot *ocelot);
616 int (*psfp_filter_add)(struct ocelot *ocelot, int port,
617 struct flow_cls_offload *f);
618 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
619 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
620 struct flow_stats *stats);
621 void (*cut_through_fwd)(struct ocelot *ocelot);
622 void (*tas_clock_adjust)(struct ocelot *ocelot);
623 void (*update_stats)(struct ocelot *ocelot);
624};
625
626struct ocelot_vcap_policer {
627 struct list_head pol_list;
628 u16 base;
629 u16 max;
630 u16 base2;
631 u16 max2;
632};
633
634struct ocelot_vcap_block {
635 struct list_head rules;
636 int count;
637};
638
639struct ocelot_bridge_vlan {
640 u16 vid;
641 unsigned long portmask;
642 unsigned long untagged;
643 struct list_head list;
644};
645
646enum ocelot_port_tag_config {
647 /* all VLANs are egress-untagged */
648 OCELOT_PORT_TAG_DISABLED = 0,
649 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
650 OCELOT_PORT_TAG_NATIVE = 1,
651 /* all VLANs except VID 0 are egress-tagged */
652 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
653 /* all VLANs are egress-tagged */
654 OCELOT_PORT_TAG_TRUNK = 3,
655};
656
657struct ocelot_psfp_list {
658 struct list_head stream_list;
659 struct list_head sfi_list;
660 struct list_head sgi_list;
661 /* Serialize access to the lists */
662 struct mutex lock;
663};
664
665enum ocelot_sb {
666 OCELOT_SB_BUF,
667 OCELOT_SB_REF,
668 OCELOT_SB_NUM,
669};
670
671enum ocelot_sb_pool {
672 OCELOT_SB_POOL_ING,
673 OCELOT_SB_POOL_EGR,
674 OCELOT_SB_POOL_NUM,
675};
676
677/* MAC table entry types.
678 * ENTRYTYPE_NORMAL is subject to aging.
679 * ENTRYTYPE_LOCKED is not subject to aging.
680 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
681 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
682 */
683enum macaccess_entry_type {
684 ENTRYTYPE_NORMAL = 0,
685 ENTRYTYPE_LOCKED,
686 ENTRYTYPE_MACv4,
687 ENTRYTYPE_MACv6,
688};
689
690#define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
691#define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
692
693struct ocelot_lag_fdb {
694 unsigned char addr[ETH_ALEN];
695 u16 vid;
696 struct net_device *bond;
697 struct list_head list;
698};
699
700struct ocelot_mirror {
701 refcount_t refcount;
702 int to;
703};
704
705struct ocelot_port;
706
707struct ocelot_port {
708 struct ocelot *ocelot;
709
710 struct regmap *target;
711
712 struct net_device *bond;
713 struct net_device *bridge;
714
715 struct ocelot_port *dsa_8021q_cpu;
716
717 /* VLAN that untagged frames are classified to, on ingress */
718 const struct ocelot_bridge_vlan *pvid_vlan;
719
720 struct tc_taprio_qopt_offload *taprio;
721
722 phy_interface_t phy_mode;
723
724 unsigned int ptp_skbs_in_flight;
725 struct sk_buff_head tx_skbs;
726
727 u16 mrp_ring_id;
728
729 u8 ptp_cmd;
730 u8 ts_id;
731
732 u8 index;
733
734 u8 stp_state;
735 bool vlan_aware;
736 bool is_dsa_8021q_cpu;
737 bool learn_ena;
738
739 bool lag_tx_active;
740
741 int bridge_num;
742
743 int speed;
744};
745
746struct ocelot {
747 struct device *dev;
748 struct devlink *devlink;
749 struct devlink_port *devlink_ports;
750
751 const struct ocelot_ops *ops;
752 struct regmap *targets[TARGET_MAX];
753 struct regmap_field *regfields[REGFIELD_MAX];
754 const u32 *const *map;
755 struct list_head stats_regions;
756
757 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
758 int packet_buffer_size;
759 int num_frame_refs;
760 int num_mact_rows;
761
762 struct ocelot_port **ports;
763
764 u8 base_mac[ETH_ALEN];
765
766 struct list_head vlans;
767 struct list_head traps;
768 struct list_head lag_fdbs;
769
770 /* Switches like VSC9959 have flooding per traffic class */
771 int num_flooding_pgids;
772
773 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
774 * the CPU is located after the physical ports (at the
775 * num_phys_ports index).
776 */
777 u8 num_phys_ports;
778
779 int npi;
780
781 enum ocelot_tag_prefix npi_inj_prefix;
782 enum ocelot_tag_prefix npi_xtr_prefix;
783
784 unsigned long bridges;
785
786 struct list_head multicast;
787 struct list_head pgids;
788
789 struct list_head dummy_rules;
790 struct ocelot_vcap_block block[3];
791 struct ocelot_vcap_policer vcap_pol;
792 struct vcap_props *vcap;
793 struct ocelot_mirror *mirror;
794
795 struct ocelot_psfp_list psfp;
796
797 /* Workqueue to check statistics for overflow */
798 struct delayed_work stats_work;
799 struct workqueue_struct *stats_queue;
800 /* Lock for serializing access to the statistics array */
801 spinlock_t stats_lock;
802 u64 *stats;
803
804 /* Lock for serializing indirect access to STAT_VIEW registers */
805 struct mutex stat_view_lock;
806 /* Lock for serializing access to the MAC table */
807 struct mutex mact_lock;
808 /* Lock for serializing forwarding domain changes */
809 struct mutex fwd_domain_lock;
810
811 /* Lock for serializing Time-Aware Shaper changes */
812 struct mutex tas_lock;
813
814 struct workqueue_struct *owq;
815
816 u8 ptp:1;
817 struct ptp_clock *ptp_clock;
818 struct ptp_clock_info ptp_info;
819 struct hwtstamp_config hwtstamp_config;
820 unsigned int ptp_skbs_in_flight;
821 /* Protects the 2-step TX timestamp ID logic */
822 spinlock_t ts_id_lock;
823 /* Protects the PTP interface state */
824 struct mutex ptp_lock;
825 /* Protects the PTP clock */
826 spinlock_t ptp_clock_lock;
827 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
828
829 struct ocelot_fdma *fdma;
830};
831
832struct ocelot_policer {
833 u32 rate; /* kilobit per second */
834 u32 burst; /* bytes */
835};
836
837#define ocelot_bulk_read(ocelot, reg, buf, count) \
838 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count)
839
840#define ocelot_read_ix(ocelot, reg, gi, ri) \
841 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
842#define ocelot_read_gix(ocelot, reg, gi) \
843 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
844#define ocelot_read_rix(ocelot, reg, ri) \
845 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
846#define ocelot_read(ocelot, reg) \
847 __ocelot_read_ix(ocelot, reg, 0)
848
849#define ocelot_write_ix(ocelot, val, reg, gi, ri) \
850 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
851#define ocelot_write_gix(ocelot, val, reg, gi) \
852 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
853#define ocelot_write_rix(ocelot, val, reg, ri) \
854 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
855#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
856
857#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
858 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
859#define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
860 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
861#define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
862 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
863#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
864
865#define ocelot_field_write(ocelot, reg, val) \
866 regmap_field_write((ocelot)->regfields[(reg)], (val))
867#define ocelot_field_read(ocelot, reg, val) \
868 regmap_field_read((ocelot)->regfields[(reg)], (val))
869#define ocelot_fields_write(ocelot, id, reg, val) \
870 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
871#define ocelot_fields_read(ocelot, id, reg, val) \
872 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
873
874#define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
875 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
876#define ocelot_target_read_gix(ocelot, target, reg, gi) \
877 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
878#define ocelot_target_read_rix(ocelot, target, reg, ri) \
879 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
880#define ocelot_target_read(ocelot, target, reg) \
881 __ocelot_target_read_ix(ocelot, target, reg, 0)
882
883#define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
884 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
885#define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
886 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
887#define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
888 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
889#define ocelot_target_write(ocelot, target, val, reg) \
890 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
891
892/* I/O */
893u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
894void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
895void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
896int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf,
897 int count);
898u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
899void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
900void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
901 u32 offset);
902u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
903 u32 reg, u32 offset);
904void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
905 u32 val, u32 reg, u32 offset);
906
907/* Packet I/O */
908bool ocelot_can_inject(struct ocelot *ocelot, int grp);
909void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
910 u32 rew_op, struct sk_buff *skb);
911void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
912int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
913void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
914void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
915 u64 timestamp);
916
917/* Hardware initialization */
918int ocelot_regfields_init(struct ocelot *ocelot,
919 const struct reg_field *const regfields);
920struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
921int ocelot_init(struct ocelot *ocelot);
922void ocelot_deinit(struct ocelot *ocelot);
923void ocelot_init_port(struct ocelot *ocelot, int port);
924void ocelot_deinit_port(struct ocelot *ocelot, int port);
925
926void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
927void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
928void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
929void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
930u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
931
932/* DSA callbacks */
933void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
934void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
935int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
936void ocelot_port_get_stats64(struct ocelot *ocelot, int port,
937 struct rtnl_link_stats64 *stats);
938void ocelot_port_get_pause_stats(struct ocelot *ocelot, int port,
939 struct ethtool_pause_stats *pause_stats);
940void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port,
941 struct ethtool_rmon_stats *rmon_stats,
942 const struct ethtool_rmon_hist_range **ranges);
943void ocelot_port_get_eth_ctrl_stats(struct ocelot *ocelot, int port,
944 struct ethtool_eth_ctrl_stats *ctrl_stats);
945void ocelot_port_get_eth_mac_stats(struct ocelot *ocelot, int port,
946 struct ethtool_eth_mac_stats *mac_stats);
947void ocelot_port_get_eth_phy_stats(struct ocelot *ocelot, int port,
948 struct ethtool_eth_phy_stats *phy_stats);
949int ocelot_get_ts_info(struct ocelot *ocelot, int port,
950 struct ethtool_ts_info *info);
951void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
952int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
953 struct netlink_ext_ack *extack);
954void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
955u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
956int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
957 struct switchdev_brport_flags val);
958void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
959 struct switchdev_brport_flags val);
960int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
961int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
962int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
963int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
964int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
965int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
966 struct net_device *bridge, int bridge_num,
967 struct netlink_ext_ack *extack);
968void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
969 struct net_device *bridge);
970int ocelot_mact_flush(struct ocelot *ocelot, int port);
971int ocelot_fdb_dump(struct ocelot *ocelot, int port,
972 dsa_fdb_dump_cb_t *cb, void *data);
973int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
974 u16 vid, const struct net_device *bridge);
975int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
976 u16 vid, const struct net_device *bridge);
977int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
978 const unsigned char *addr, u16 vid,
979 const struct net_device *bridge);
980int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
981 const unsigned char *addr, u16 vid,
982 const struct net_device *bridge);
983int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
984 bool untagged, struct netlink_ext_ack *extack);
985int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
986 bool untagged);
987int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
988int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
989int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
990int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
991 struct sk_buff *skb,
992 struct sk_buff **clone);
993void ocelot_get_txtstamp(struct ocelot *ocelot);
994void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
995int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
996int ocelot_port_policer_add(struct ocelot *ocelot, int port,
997 struct ocelot_policer *pol);
998int ocelot_port_policer_del(struct ocelot *ocelot, int port);
999int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
1000 bool ingress, struct netlink_ext_ack *extack);
1001void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
1002int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
1003 struct flow_cls_offload *f, bool ingress);
1004int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
1005 struct flow_cls_offload *f, bool ingress);
1006int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
1007 struct flow_cls_offload *f, bool ingress);
1008int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1009 const struct switchdev_obj_port_mdb *mdb,
1010 const struct net_device *bridge);
1011int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1012 const struct switchdev_obj_port_mdb *mdb,
1013 const struct net_device *bridge);
1014int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1015 struct net_device *bond,
1016 struct netdev_lag_upper_info *info,
1017 struct netlink_ext_ack *extack);
1018void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1019 struct net_device *bond);
1020void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
1021int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond);
1022
1023int ocelot_devlink_sb_register(struct ocelot *ocelot);
1024void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
1025int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
1026 u16 pool_index,
1027 struct devlink_sb_pool_info *pool_info);
1028int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
1029 u16 pool_index, u32 size,
1030 enum devlink_sb_threshold_type threshold_type,
1031 struct netlink_ext_ack *extack);
1032int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
1033 unsigned int sb_index, u16 pool_index,
1034 u32 *p_threshold);
1035int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
1036 unsigned int sb_index, u16 pool_index,
1037 u32 threshold, struct netlink_ext_ack *extack);
1038int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
1039 unsigned int sb_index, u16 tc_index,
1040 enum devlink_sb_pool_type pool_type,
1041 u16 *p_pool_index, u32 *p_threshold);
1042int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
1043 unsigned int sb_index, u16 tc_index,
1044 enum devlink_sb_pool_type pool_type,
1045 u16 pool_index, u32 threshold,
1046 struct netlink_ext_ack *extack);
1047int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
1048int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
1049int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
1050 unsigned int sb_index, u16 pool_index,
1051 u32 *p_cur, u32 *p_max);
1052int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
1053 unsigned int sb_index, u16 tc_index,
1054 enum devlink_sb_pool_type pool_type,
1055 u32 *p_cur, u32 *p_max);
1056
1057void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1058 unsigned int link_an_mode,
1059 phy_interface_t interface,
1060 unsigned long quirks);
1061void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1062 struct phy_device *phydev,
1063 unsigned int link_an_mode,
1064 phy_interface_t interface,
1065 int speed, int duplex,
1066 bool tx_pause, bool rx_pause,
1067 unsigned long quirks);
1068
1069int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
1070 const unsigned char mac[ETH_ALEN],
1071 unsigned int vid, enum macaccess_entry_type *type);
1072int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1073 const unsigned char mac[ETH_ALEN],
1074 unsigned int vid,
1075 enum macaccess_entry_type type,
1076 int sfid, int ssid);
1077
1078int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1079 unsigned long to_mask);
1080
1081int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1082 struct ocelot_policer *pol);
1083int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1084
1085#if IS_ENABLED(CONFIG_BRIDGE_MRP)
1086int ocelot_mrp_add(struct ocelot *ocelot, int port,
1087 const struct switchdev_obj_mrp *mrp);
1088int ocelot_mrp_del(struct ocelot *ocelot, int port,
1089 const struct switchdev_obj_mrp *mrp);
1090int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1091 const struct switchdev_obj_ring_role_mrp *mrp);
1092int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1093 const struct switchdev_obj_ring_role_mrp *mrp);
1094#else
1095static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1096 const struct switchdev_obj_mrp *mrp)
1097{
1098 return -EOPNOTSUPP;
1099}
1100
1101static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1102 const struct switchdev_obj_mrp *mrp)
1103{
1104 return -EOPNOTSUPP;
1105}
1106
1107static inline int
1108ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1109 const struct switchdev_obj_ring_role_mrp *mrp)
1110{
1111 return -EOPNOTSUPP;
1112}
1113
1114static inline int
1115ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1116 const struct switchdev_obj_ring_role_mrp *mrp)
1117{
1118 return -EOPNOTSUPP;
1119}
1120#endif
1121
1122#endif