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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16#include <linux/phylink.h>
17
18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
20#define STMMAC_CH_MAX 8
21
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
37
38/* MTL algorithms identifiers */
39#define MTL_TX_ALGORITHM_WRR 0x0
40#define MTL_TX_ALGORITHM_WFQ 0x1
41#define MTL_TX_ALGORITHM_DWRR 0x2
42#define MTL_TX_ALGORITHM_SP 0x3
43#define MTL_RX_ALGORITHM_SP 0x4
44#define MTL_RX_ALGORITHM_WSP 0x5
45
46/* RX/TX Queue Mode */
47#define MTL_QUEUE_AVB 0x0
48#define MTL_QUEUE_DCB 0x1
49
50/* The MDC clock could be set higher than the IEEE 802.3
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
52 * of value different than the above defined values. The resultant MDIO
53 * clock frequency of 12.5 MHz is applicable for the interfacing chips
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
56 * of 12.5 MHz, corresponding to the following selection.
57 */
58#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
59#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
60#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
61#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
62#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
63#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
64#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
65#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
66
67/* AXI DMA Burst length supported */
68#define DMA_AXI_BLEN_4 (1 << 1)
69#define DMA_AXI_BLEN_8 (1 << 2)
70#define DMA_AXI_BLEN_16 (1 << 3)
71#define DMA_AXI_BLEN_32 (1 << 4)
72#define DMA_AXI_BLEN_64 (1 << 5)
73#define DMA_AXI_BLEN_128 (1 << 6)
74#define DMA_AXI_BLEN_256 (1 << 7)
75#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
78
79struct stmmac_priv;
80
81/* Platfrom data for platform device structure's platform_data field */
82
83struct stmmac_mdio_bus_data {
84 unsigned int phy_mask;
85 unsigned int pcs_mask;
86 unsigned int default_an_inband;
87 int *irqs;
88 int probed_phy_irq;
89 bool needs_reset;
90};
91
92struct stmmac_dma_cfg {
93 int pbl;
94 int txpbl;
95 int rxpbl;
96 bool pblx8;
97 int fixed_burst;
98 int mixed_burst;
99 bool aal;
100 bool eame;
101 bool multi_msi_en;
102 bool dche;
103};
104
105#define AXI_BLEN 7
106struct stmmac_axi {
107 bool axi_lpi_en;
108 bool axi_xit_frm;
109 u32 axi_wr_osr_lmt;
110 u32 axi_rd_osr_lmt;
111 bool axi_kbbe;
112 u32 axi_blen[AXI_BLEN];
113 bool axi_fb;
114 bool axi_mb;
115 bool axi_rb;
116};
117
118struct stmmac_rxq_cfg {
119 u8 mode_to_use;
120 u32 chan;
121 u8 pkt_route;
122 bool use_prio;
123 u32 prio;
124};
125
126struct stmmac_txq_cfg {
127 u32 weight;
128 bool coe_unsupported;
129 u8 mode_to_use;
130 /* Credit Base Shaper parameters */
131 u32 send_slope;
132 u32 idle_slope;
133 u32 high_credit;
134 u32 low_credit;
135 bool use_prio;
136 u32 prio;
137 int tbs_en;
138};
139
140/* FPE link state */
141enum stmmac_fpe_state {
142 FPE_STATE_OFF = 0,
143 FPE_STATE_CAPABLE = 1,
144 FPE_STATE_ENTERING_ON = 2,
145 FPE_STATE_ON = 3,
146};
147
148/* FPE link-partner hand-shaking mPacket type */
149enum stmmac_mpacket_type {
150 MPACKET_VERIFY = 0,
151 MPACKET_RESPONSE = 1,
152};
153
154enum stmmac_fpe_task_state_t {
155 __FPE_REMOVING,
156 __FPE_TASK_SCHED,
157};
158
159struct stmmac_fpe_cfg {
160 bool enable; /* FPE enable */
161 bool hs_enable; /* FPE handshake enable */
162 enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
163 enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
164 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
165};
166
167struct stmmac_safety_feature_cfg {
168 u32 tsoee;
169 u32 mrxpee;
170 u32 mestee;
171 u32 mrxee;
172 u32 mtxee;
173 u32 epsi;
174 u32 edpp;
175 u32 prtyen;
176 u32 tmouten;
177};
178
179/* Addresses that may be customized by a platform */
180struct dwmac4_addrs {
181 u32 dma_chan;
182 u32 dma_chan_offset;
183 u32 mtl_chan;
184 u32 mtl_chan_offset;
185 u32 mtl_ets_ctrl;
186 u32 mtl_ets_ctrl_offset;
187 u32 mtl_txq_weight;
188 u32 mtl_txq_weight_offset;
189 u32 mtl_send_slp_cred;
190 u32 mtl_send_slp_cred_offset;
191 u32 mtl_high_cred;
192 u32 mtl_high_cred_offset;
193 u32 mtl_low_cred;
194 u32 mtl_low_cred_offset;
195};
196
197#define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
198#define STMMAC_FLAG_SPH_DISABLE BIT(1)
199#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
200#define STMMAC_FLAG_HAS_SUN8I BIT(3)
201#define STMMAC_FLAG_TSO_EN BIT(4)
202#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
203#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
204#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
205#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
206#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
207#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
208#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
209#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
210
211struct plat_stmmacenet_data {
212 int bus_id;
213 int phy_addr;
214 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
215 * ^ ^
216 * mac_interface phy_interface
217 *
218 * mac_interface is the MAC-side interface, which may be the same
219 * as phy_interface if there is no intervening PCS. If there is a
220 * PCS, then mac_interface describes the interface mode between the
221 * MAC and PCS, and phy_interface describes the interface mode
222 * between the PCS and PHY.
223 */
224 phy_interface_t mac_interface;
225 /* phy_interface is the PHY-side interface - the interface used by
226 * an attached PHY.
227 */
228 phy_interface_t phy_interface;
229 struct stmmac_mdio_bus_data *mdio_bus_data;
230 struct device_node *phy_node;
231 struct fwnode_handle *port_node;
232 struct device_node *mdio_node;
233 struct stmmac_dma_cfg *dma_cfg;
234 struct stmmac_fpe_cfg *fpe_cfg;
235 struct stmmac_safety_feature_cfg *safety_feat_cfg;
236 int clk_csr;
237 int has_gmac;
238 int enh_desc;
239 int tx_coe;
240 int rx_coe;
241 int bugged_jumbo;
242 int pmt;
243 int force_sf_dma_mode;
244 int force_thresh_dma_mode;
245 int riwt_off;
246 int max_speed;
247 int maxmtu;
248 int multicast_filter_bins;
249 int unicast_filter_entries;
250 int tx_fifo_size;
251 int rx_fifo_size;
252 u32 host_dma_width;
253 u32 rx_queues_to_use;
254 u32 tx_queues_to_use;
255 u8 rx_sched_algorithm;
256 u8 tx_sched_algorithm;
257 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
258 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
259 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
260 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
261 int (*serdes_powerup)(struct net_device *ndev, void *priv);
262 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
263 void (*speed_mode_2500)(struct net_device *ndev, void *priv);
264 void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
265 int (*init)(struct platform_device *pdev, void *priv);
266 void (*exit)(struct platform_device *pdev, void *priv);
267 struct mac_device_info *(*setup)(void *priv);
268 int (*clks_config)(void *priv, bool enabled);
269 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
270 void *ctx);
271 void (*dump_debug_regs)(void *priv);
272 int (*pcs_init)(struct stmmac_priv *priv);
273 void (*pcs_exit)(struct stmmac_priv *priv);
274 struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
275 phy_interface_t interface);
276 void *bsp_priv;
277 struct clk *stmmac_clk;
278 struct clk *pclk;
279 struct clk *clk_ptp_ref;
280 unsigned int clk_ptp_rate;
281 unsigned int clk_ref_rate;
282 unsigned int mult_fact_100ns;
283 s32 ptp_max_adj;
284 u32 cdc_error_adj;
285 struct reset_control *stmmac_rst;
286 struct reset_control *stmmac_ahb_rst;
287 struct stmmac_axi *axi;
288 int has_gmac4;
289 int rss_en;
290 int mac_port_sel_speed;
291 int has_xgmac;
292 u8 vlan_fail_q;
293 unsigned int eee_usecs_rate;
294 struct pci_dev *pdev;
295 int int_snapshot_num;
296 int msi_mac_vec;
297 int msi_wol_vec;
298 int msi_lpi_vec;
299 int msi_sfty_ce_vec;
300 int msi_sfty_ue_vec;
301 int msi_rx_base_vec;
302 int msi_tx_base_vec;
303 const struct dwmac4_addrs *dwmac4_addrs;
304 unsigned int flags;
305};
306#endif