tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef _I915_PCIIDS_H
26#define _I915_PCIIDS_H
27
28/*
29 * A pci_device_id struct {
30 * __u32 vendor, device;
31 * __u32 subvendor, subdevice;
32 * __u32 class, class_mask;
33 * kernel_ulong_t driver_data;
34 * };
35 * Don't use C99 here because "class" is reserved and we want to
36 * give userspace flexibility.
37 */
38#define INTEL_VGA_DEVICE(id, info) { \
39 0x8086, id, \
40 ~0, ~0, \
41 0x030000, 0xff0000, \
42 (unsigned long) info }
43
44#define INTEL_QUANTA_VGA_DEVICE(info) { \
45 0x8086, 0x16a, \
46 0x152d, 0x8990, \
47 0x030000, 0xff0000, \
48 (unsigned long) info }
49
50#define INTEL_I810_IDS(MACRO__, ...) \
51 MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
52 MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
53 MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
54
55#define INTEL_I815_IDS(MACRO__, ...) \
56 MACRO__(0x1132, ## __VA_ARGS__) /* I815*/
57
58#define INTEL_I830_IDS(MACRO__, ...) \
59 MACRO__(0x3577, ## __VA_ARGS__)
60
61#define INTEL_I845G_IDS(MACRO__, ...) \
62 MACRO__(0x2562, ## __VA_ARGS__)
63
64#define INTEL_I85X_IDS(MACRO__, ...) \
65 MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
66 MACRO__(0x358e, ## __VA_ARGS__)
67
68#define INTEL_I865G_IDS(MACRO__, ...) \
69 MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */
70
71#define INTEL_I915G_IDS(MACRO__, ...) \
72 MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
73 MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
74
75#define INTEL_I915GM_IDS(MACRO__, ...) \
76 MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */
77
78#define INTEL_I945G_IDS(MACRO__, ...) \
79 MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */
80
81#define INTEL_I945GM_IDS(MACRO__, ...) \
82 MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
83 MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
84
85#define INTEL_I965G_IDS(MACRO__, ...) \
86 MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
87 MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
88 MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
89 MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
90
91#define INTEL_G33_IDS(MACRO__, ...) \
92 MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
93 MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
94 MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
95
96#define INTEL_I965GM_IDS(MACRO__, ...) \
97 MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
98 MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
99
100#define INTEL_GM45_IDS(MACRO__, ...) \
101 MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */
102
103#define INTEL_G45_IDS(MACRO__, ...) \
104 MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
105 MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
106 MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
107 MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
108 MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
109 MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
110
111#define INTEL_PNV_G_IDS(MACRO__, ...) \
112 MACRO__(0xa001, ## __VA_ARGS__)
113
114#define INTEL_PNV_M_IDS(MACRO__, ...) \
115 MACRO__(0xa011, ## __VA_ARGS__)
116
117#define INTEL_PNV_IDS(MACRO__, ...) \
118 INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
119 INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
120
121#define INTEL_ILK_D_IDS(MACRO__, ...) \
122 MACRO__(0x0042, ## __VA_ARGS__)
123
124#define INTEL_ILK_M_IDS(MACRO__, ...) \
125 MACRO__(0x0046, ## __VA_ARGS__)
126
127#define INTEL_ILK_IDS(MACRO__, ...) \
128 INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
129 INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
130
131#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
132 MACRO__(0x0102, ## __VA_ARGS__), \
133 MACRO__(0x010A, ## __VA_ARGS__)
134
135#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
136 MACRO__(0x0112, ## __VA_ARGS__), \
137 MACRO__(0x0122, ## __VA_ARGS__)
138
139#define INTEL_SNB_D_IDS(MACRO__, ...) \
140 INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
141 INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
142
143#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \
144 MACRO__(0x0106, ## __VA_ARGS__)
145
146#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
147 MACRO__(0x0116, ## __VA_ARGS__), \
148 MACRO__(0x0126, ## __VA_ARGS__)
149
150#define INTEL_SNB_M_IDS(MACRO__, ...) \
151 INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
152 INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
153
154#define INTEL_SNB_IDS(MACRO__, ...) \
155 INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
156 INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
157
158#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \
159 MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */
160
161#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \
162 MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */
163
164#define INTEL_IVB_M_IDS(MACRO__, ...) \
165 INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
166 INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
167
168#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
169 MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
170 MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
171
172#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
173 MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
174 MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
175
176#define INTEL_IVB_D_IDS(MACRO__, ...) \
177 INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
178 INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
179
180#define INTEL_IVB_IDS(MACRO__, ...) \
181 INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
182 INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
183
184#define INTEL_IVB_Q_IDS(MACRO__, ...) \
185 INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */
186
187#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
188 MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
189 MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
190 MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
191 MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
192
193#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \
194 MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */
195
196#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
197 INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
198 INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
199 MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
200 MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
201 MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
202 MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
203 MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
204 MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
205 MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
206 MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
207 MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
208 MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
209 MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
210 MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
211 MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
212 MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
213 MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
214
215#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
216 MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
217 MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
218 MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
219 MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
220
221#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \
222 MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \
223
224#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
225 INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
226 INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
227 MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
228 MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
229 MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
230 MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
231 MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
232 MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
233 MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
234 MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
235 MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
236 MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
237 MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
238 MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
239 MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
240 MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
241 MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
242
243#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
244 MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
245 MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
246 MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
247 MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
248 MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
249
250#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
251 INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
252 MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
253 MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
254 MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
255 MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
256 MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
257 MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
258 MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
259 MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
260 MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
261 MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
262 MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
263 MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
264 MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
265 MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
266 MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
267
268#define INTEL_HSW_IDS(MACRO__, ...) \
269 INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
270 INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
271 INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
272
273#define INTEL_VLV_IDS(MACRO__, ...) \
274 MACRO__(0x0f30, ## __VA_ARGS__), \
275 MACRO__(0x0f31, ## __VA_ARGS__), \
276 MACRO__(0x0f32, ## __VA_ARGS__), \
277 MACRO__(0x0f33, ## __VA_ARGS__)
278
279#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
280 MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
281 MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
282
283#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \
284 MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */
285
286#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
287 INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
288 INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
289 MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
290 MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
291 MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
292
293#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
294 MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
295 MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
296
297#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \
298 MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */
299
300#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
301 INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
302 INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
303 MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
304 MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
305 MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
306
307#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
308 MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
309 MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
310
311#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \
312 MACRO__(0x162E, ## __VA_ARGS__) /* ULX */
313
314#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
315 INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
316 INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
317 MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
318 MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
319 MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
320
321#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
322 MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
323 MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
324
325#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \
326 MACRO__(0x163E, ## __VA_ARGS__) /* ULX */
327
328#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
329 INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
330 INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
331 MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
332 MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
333 MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
334
335#define INTEL_BDW_IDS(MACRO__, ...) \
336 INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
337 INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
338 INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
339 INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
340
341#define INTEL_CHV_IDS(MACRO__, ...) \
342 MACRO__(0x22b0, ## __VA_ARGS__), \
343 MACRO__(0x22b1, ## __VA_ARGS__), \
344 MACRO__(0x22b2, ## __VA_ARGS__), \
345 MACRO__(0x22b3, ## __VA_ARGS__)
346
347#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
348 MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
349 MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
350
351#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
352 MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
353 MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
354
355#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
356 INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
357 INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
358 MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
359 MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
360 MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
361 MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
362
363#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
364 MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
365 MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
366
367#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \
368 MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */
369
370#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
371 INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
372 INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
373 MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
374 MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
375 MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
376 MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
377
378#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
379 MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
380 MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
381 MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
382
383#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
384 INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
385 MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
386 MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
387 MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
388
389#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
390 MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
391 MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
392 MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
393 MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
394
395#define INTEL_SKL_IDS(MACRO__, ...) \
396 INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
397 INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
398 INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
399 INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
400
401#define INTEL_BXT_IDS(MACRO__, ...) \
402 MACRO__(0x0A84, ## __VA_ARGS__), \
403 MACRO__(0x1A84, ## __VA_ARGS__), \
404 MACRO__(0x1A85, ## __VA_ARGS__), \
405 MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
406 MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
407
408#define INTEL_GLK_IDS(MACRO__, ...) \
409 MACRO__(0x3184, ## __VA_ARGS__), \
410 MACRO__(0x3185, ## __VA_ARGS__)
411
412#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
413 MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
414 MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
415
416#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
417 MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
418 MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
419
420#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
421 INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
422 INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
423 MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
424 MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
425 MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
426 MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
427
428#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
429 MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
430 MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
431
432#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \
433 MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */
434
435#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
436 INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
437 INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
438 MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
439 MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
440 MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
441 MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
442 MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
443
444#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \
445 MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */
446
447#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
448 INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
449 MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
450 MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
451
452#define INTEL_KBL_GT4_IDS(MACRO__, ...) \
453 MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */
454
455/* AML/KBL Y GT2 */
456#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
457 MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
458 MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
459
460/* AML/CFL Y GT2 */
461#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \
462 MACRO__(0x87CA, ## __VA_ARGS__)
463
464/* CML GT1 */
465#define INTEL_CML_GT1_IDS(MACRO__, ...) \
466 MACRO__(0x9BA2, ## __VA_ARGS__), \
467 MACRO__(0x9BA4, ## __VA_ARGS__), \
468 MACRO__(0x9BA5, ## __VA_ARGS__), \
469 MACRO__(0x9BA8, ## __VA_ARGS__)
470
471#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
472 MACRO__(0x9B21, ## __VA_ARGS__), \
473 MACRO__(0x9BAA, ## __VA_ARGS__), \
474 MACRO__(0x9BAC, ## __VA_ARGS__)
475
476/* CML GT2 */
477#define INTEL_CML_GT2_IDS(MACRO__, ...) \
478 MACRO__(0x9BC2, ## __VA_ARGS__), \
479 MACRO__(0x9BC4, ## __VA_ARGS__), \
480 MACRO__(0x9BC5, ## __VA_ARGS__), \
481 MACRO__(0x9BC6, ## __VA_ARGS__), \
482 MACRO__(0x9BC8, ## __VA_ARGS__), \
483 MACRO__(0x9BE6, ## __VA_ARGS__), \
484 MACRO__(0x9BF6, ## __VA_ARGS__)
485
486#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
487 MACRO__(0x9B41, ## __VA_ARGS__), \
488 MACRO__(0x9BCA, ## __VA_ARGS__), \
489 MACRO__(0x9BCC, ## __VA_ARGS__)
490
491#define INTEL_CML_IDS(MACRO__, ...) \
492 INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
493 INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
494 INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
495 INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
496
497#define INTEL_KBL_IDS(MACRO__, ...) \
498 INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
499 INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
500 INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
501 INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
502 INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
503
504/* CFL S */
505#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
506 MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
507 MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
508 MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
509
510#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
511 MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
512 MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
513 MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
514 MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
515 MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
516
517/* CFL H */
518#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \
519 MACRO__(0x3E9C, ## __VA_ARGS__)
520
521#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
522 MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
523 MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
524
525/* CFL U GT2 */
526#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \
527 MACRO__(0x3EA9, ## __VA_ARGS__)
528
529/* CFL U GT3 */
530#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
531 MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
532 MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
533 MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
534 MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
535
536#define INTEL_CFL_IDS(MACRO__, ...) \
537 INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
538 INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
539 INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
540 INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
541 INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
542 INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
543 INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
544
545/* WHL/CFL U GT1 */
546#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
547 MACRO__(0x3EA1, ## __VA_ARGS__), \
548 MACRO__(0x3EA4, ## __VA_ARGS__)
549
550/* WHL/CFL U GT2 */
551#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
552 MACRO__(0x3EA0, ## __VA_ARGS__), \
553 MACRO__(0x3EA3, ## __VA_ARGS__)
554
555/* WHL/CFL U GT3 */
556#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \
557 MACRO__(0x3EA2, ## __VA_ARGS__)
558
559#define INTEL_WHL_IDS(MACRO__, ...) \
560 INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
561 INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
562 INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
563
564/* CNL */
565#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
566 MACRO__(0x5A44, ## __VA_ARGS__), \
567 MACRO__(0x5A4C, ## __VA_ARGS__), \
568 MACRO__(0x5A54, ## __VA_ARGS__), \
569 MACRO__(0x5A5C, ## __VA_ARGS__)
570
571#define INTEL_CNL_IDS(MACRO__, ...) \
572 INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
573 MACRO__(0x5A40, ## __VA_ARGS__), \
574 MACRO__(0x5A41, ## __VA_ARGS__), \
575 MACRO__(0x5A42, ## __VA_ARGS__), \
576 MACRO__(0x5A49, ## __VA_ARGS__), \
577 MACRO__(0x5A4A, ## __VA_ARGS__), \
578 MACRO__(0x5A50, ## __VA_ARGS__), \
579 MACRO__(0x5A51, ## __VA_ARGS__), \
580 MACRO__(0x5A52, ## __VA_ARGS__), \
581 MACRO__(0x5A59, ## __VA_ARGS__), \
582 MACRO__(0x5A5A, ## __VA_ARGS__)
583
584/* ICL */
585#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
586 MACRO__(0x8A50, ## __VA_ARGS__), \
587 MACRO__(0x8A52, ## __VA_ARGS__), \
588 MACRO__(0x8A53, ## __VA_ARGS__), \
589 MACRO__(0x8A54, ## __VA_ARGS__), \
590 MACRO__(0x8A56, ## __VA_ARGS__), \
591 MACRO__(0x8A57, ## __VA_ARGS__), \
592 MACRO__(0x8A58, ## __VA_ARGS__), \
593 MACRO__(0x8A59, ## __VA_ARGS__), \
594 MACRO__(0x8A5A, ## __VA_ARGS__), \
595 MACRO__(0x8A5B, ## __VA_ARGS__), \
596 MACRO__(0x8A5C, ## __VA_ARGS__), \
597 MACRO__(0x8A70, ## __VA_ARGS__), \
598 MACRO__(0x8A71, ## __VA_ARGS__)
599
600#define INTEL_ICL_IDS(MACRO__, ...) \
601 INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
602 MACRO__(0x8A51, ## __VA_ARGS__), \
603 MACRO__(0x8A5D, ## __VA_ARGS__)
604
605/* EHL */
606#define INTEL_EHL_IDS(MACRO__, ...) \
607 MACRO__(0x4541, ## __VA_ARGS__), \
608 MACRO__(0x4551, ## __VA_ARGS__), \
609 MACRO__(0x4555, ## __VA_ARGS__), \
610 MACRO__(0x4557, ## __VA_ARGS__), \
611 MACRO__(0x4570, ## __VA_ARGS__), \
612 MACRO__(0x4571, ## __VA_ARGS__)
613
614/* JSL */
615#define INTEL_JSL_IDS(MACRO__, ...) \
616 MACRO__(0x4E51, ## __VA_ARGS__), \
617 MACRO__(0x4E55, ## __VA_ARGS__), \
618 MACRO__(0x4E57, ## __VA_ARGS__), \
619 MACRO__(0x4E61, ## __VA_ARGS__), \
620 MACRO__(0x4E71, ## __VA_ARGS__)
621
622/* TGL */
623#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
624 MACRO__(0x9A60, ## __VA_ARGS__), \
625 MACRO__(0x9A68, ## __VA_ARGS__), \
626 MACRO__(0x9A70, ## __VA_ARGS__)
627
628#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
629 MACRO__(0x9A40, ## __VA_ARGS__), \
630 MACRO__(0x9A49, ## __VA_ARGS__), \
631 MACRO__(0x9A59, ## __VA_ARGS__), \
632 MACRO__(0x9A78, ## __VA_ARGS__), \
633 MACRO__(0x9AC0, ## __VA_ARGS__), \
634 MACRO__(0x9AC9, ## __VA_ARGS__), \
635 MACRO__(0x9AD9, ## __VA_ARGS__), \
636 MACRO__(0x9AF8, ## __VA_ARGS__)
637
638#define INTEL_TGL_IDS(MACRO__, ...) \
639 INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
640 INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
641
642/* RKL */
643#define INTEL_RKL_IDS(MACRO__, ...) \
644 MACRO__(0x4C80, ## __VA_ARGS__), \
645 MACRO__(0x4C8A, ## __VA_ARGS__), \
646 MACRO__(0x4C8B, ## __VA_ARGS__), \
647 MACRO__(0x4C8C, ## __VA_ARGS__), \
648 MACRO__(0x4C90, ## __VA_ARGS__), \
649 MACRO__(0x4C9A, ## __VA_ARGS__)
650
651/* DG1 */
652#define INTEL_DG1_IDS(MACRO__, ...) \
653 MACRO__(0x4905, ## __VA_ARGS__), \
654 MACRO__(0x4906, ## __VA_ARGS__), \
655 MACRO__(0x4907, ## __VA_ARGS__), \
656 MACRO__(0x4908, ## __VA_ARGS__), \
657 MACRO__(0x4909, ## __VA_ARGS__)
658
659/* ADL-S */
660#define INTEL_ADLS_IDS(MACRO__, ...) \
661 MACRO__(0x4680, ## __VA_ARGS__), \
662 MACRO__(0x4682, ## __VA_ARGS__), \
663 MACRO__(0x4688, ## __VA_ARGS__), \
664 MACRO__(0x468A, ## __VA_ARGS__), \
665 MACRO__(0x468B, ## __VA_ARGS__), \
666 MACRO__(0x4690, ## __VA_ARGS__), \
667 MACRO__(0x4692, ## __VA_ARGS__), \
668 MACRO__(0x4693, ## __VA_ARGS__)
669
670/* ADL-P */
671#define INTEL_ADLP_IDS(MACRO__, ...) \
672 MACRO__(0x46A0, ## __VA_ARGS__), \
673 MACRO__(0x46A1, ## __VA_ARGS__), \
674 MACRO__(0x46A2, ## __VA_ARGS__), \
675 MACRO__(0x46A3, ## __VA_ARGS__), \
676 MACRO__(0x46A6, ## __VA_ARGS__), \
677 MACRO__(0x46A8, ## __VA_ARGS__), \
678 MACRO__(0x46AA, ## __VA_ARGS__), \
679 MACRO__(0x462A, ## __VA_ARGS__), \
680 MACRO__(0x4626, ## __VA_ARGS__), \
681 MACRO__(0x4628, ## __VA_ARGS__), \
682 MACRO__(0x46B0, ## __VA_ARGS__), \
683 MACRO__(0x46B1, ## __VA_ARGS__), \
684 MACRO__(0x46B2, ## __VA_ARGS__), \
685 MACRO__(0x46B3, ## __VA_ARGS__), \
686 MACRO__(0x46C0, ## __VA_ARGS__), \
687 MACRO__(0x46C1, ## __VA_ARGS__), \
688 MACRO__(0x46C2, ## __VA_ARGS__), \
689 MACRO__(0x46C3, ## __VA_ARGS__)
690
691/* ADL-N */
692#define INTEL_ADLN_IDS(MACRO__, ...) \
693 MACRO__(0x46D0, ## __VA_ARGS__), \
694 MACRO__(0x46D1, ## __VA_ARGS__), \
695 MACRO__(0x46D2, ## __VA_ARGS__), \
696 MACRO__(0x46D3, ## __VA_ARGS__), \
697 MACRO__(0x46D4, ## __VA_ARGS__)
698
699/* RPL-S */
700#define INTEL_RPLS_IDS(MACRO__, ...) \
701 MACRO__(0xA780, ## __VA_ARGS__), \
702 MACRO__(0xA781, ## __VA_ARGS__), \
703 MACRO__(0xA782, ## __VA_ARGS__), \
704 MACRO__(0xA783, ## __VA_ARGS__), \
705 MACRO__(0xA788, ## __VA_ARGS__), \
706 MACRO__(0xA789, ## __VA_ARGS__), \
707 MACRO__(0xA78A, ## __VA_ARGS__), \
708 MACRO__(0xA78B, ## __VA_ARGS__)
709
710/* RPL-U */
711#define INTEL_RPLU_IDS(MACRO__, ...) \
712 MACRO__(0xA721, ## __VA_ARGS__), \
713 MACRO__(0xA7A1, ## __VA_ARGS__), \
714 MACRO__(0xA7A9, ## __VA_ARGS__), \
715 MACRO__(0xA7AC, ## __VA_ARGS__), \
716 MACRO__(0xA7AD, ## __VA_ARGS__)
717
718/* RPL-P */
719#define INTEL_RPLP_IDS(MACRO__, ...) \
720 MACRO__(0xA720, ## __VA_ARGS__), \
721 MACRO__(0xA7A0, ## __VA_ARGS__), \
722 MACRO__(0xA7A8, ## __VA_ARGS__), \
723 MACRO__(0xA7AA, ## __VA_ARGS__), \
724 MACRO__(0xA7AB, ## __VA_ARGS__)
725
726/* DG2 */
727#define INTEL_DG2_G10_IDS(MACRO__, ...) \
728 MACRO__(0x5690, ## __VA_ARGS__), \
729 MACRO__(0x5691, ## __VA_ARGS__), \
730 MACRO__(0x5692, ## __VA_ARGS__), \
731 MACRO__(0x56A0, ## __VA_ARGS__), \
732 MACRO__(0x56A1, ## __VA_ARGS__), \
733 MACRO__(0x56A2, ## __VA_ARGS__), \
734 MACRO__(0x56BE, ## __VA_ARGS__), \
735 MACRO__(0x56BF, ## __VA_ARGS__)
736
737#define INTEL_DG2_G11_IDS(MACRO__, ...) \
738 MACRO__(0x5693, ## __VA_ARGS__), \
739 MACRO__(0x5694, ## __VA_ARGS__), \
740 MACRO__(0x5695, ## __VA_ARGS__), \
741 MACRO__(0x56A5, ## __VA_ARGS__), \
742 MACRO__(0x56A6, ## __VA_ARGS__), \
743 MACRO__(0x56B0, ## __VA_ARGS__), \
744 MACRO__(0x56B1, ## __VA_ARGS__), \
745 MACRO__(0x56BA, ## __VA_ARGS__), \
746 MACRO__(0x56BB, ## __VA_ARGS__), \
747 MACRO__(0x56BC, ## __VA_ARGS__), \
748 MACRO__(0x56BD, ## __VA_ARGS__)
749
750#define INTEL_DG2_G12_IDS(MACRO__, ...) \
751 MACRO__(0x5696, ## __VA_ARGS__), \
752 MACRO__(0x5697, ## __VA_ARGS__), \
753 MACRO__(0x56A3, ## __VA_ARGS__), \
754 MACRO__(0x56A4, ## __VA_ARGS__), \
755 MACRO__(0x56B2, ## __VA_ARGS__), \
756 MACRO__(0x56B3, ## __VA_ARGS__)
757
758#define INTEL_DG2_IDS(MACRO__, ...) \
759 INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
760 INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
761 INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
762
763#define INTEL_ATS_M150_IDS(MACRO__, ...) \
764 MACRO__(0x56C0, ## __VA_ARGS__), \
765 MACRO__(0x56C2, ## __VA_ARGS__)
766
767#define INTEL_ATS_M75_IDS(MACRO__, ...) \
768 MACRO__(0x56C1, ## __VA_ARGS__)
769
770#define INTEL_ATS_M_IDS(MACRO__, ...) \
771 INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
772 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
773
774/* MTL */
775#define INTEL_ARL_IDS(MACRO__, ...) \
776 MACRO__(0x7D41, ## __VA_ARGS__), \
777 MACRO__(0x7D51, ## __VA_ARGS__), \
778 MACRO__(0x7D67, ## __VA_ARGS__), \
779 MACRO__(0x7DD1, ## __VA_ARGS__)
780
781#define INTEL_MTL_IDS(MACRO__, ...) \
782 INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
783 MACRO__(0x7D40, ## __VA_ARGS__), \
784 MACRO__(0x7D45, ## __VA_ARGS__), \
785 MACRO__(0x7D55, ## __VA_ARGS__), \
786 MACRO__(0x7D60, ## __VA_ARGS__), \
787 MACRO__(0x7DD5, ## __VA_ARGS__)
788
789/* LNL */
790#define INTEL_LNL_IDS(MACRO__, ...) \
791 MACRO__(0x6420, ## __VA_ARGS__), \
792 MACRO__(0x64A0, ## __VA_ARGS__), \
793 MACRO__(0x64B0, ## __VA_ARGS__)
794
795/* BMG */
796#define INTEL_BMG_IDS(MACRO__, ...) \
797 MACRO__(0xE202, ## __VA_ARGS__), \
798 MACRO__(0xE20B, ## __VA_ARGS__), \
799 MACRO__(0xE20C, ## __VA_ARGS__), \
800 MACRO__(0xE20D, ## __VA_ARGS__), \
801 MACRO__(0xE212, ## __VA_ARGS__)
802
803#endif /* _I915_PCIIDS_H */