tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_COMMON_H_
5#define _ICE_COMMON_H_
6
7#include <linux/bitfield.h>
8
9#include "ice.h"
10#include "ice_type.h"
11#include "ice_nvm.h"
12#include "ice_flex_pipe.h"
13#include <linux/avf/virtchnl.h>
14#include "ice_switch.h"
15#include "ice_fdir.h"
16
17#define ICE_SQ_SEND_DELAY_TIME_MS 10
18#define ICE_SQ_SEND_MAX_EXECUTE 3
19
20#define FEC_REG_SHIFT 2
21#define FEC_RECV_ID_SHIFT 4
22#define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT)
23#define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT)
24#define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT)
25#define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT)
26#define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT)
27#define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT)
28#define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT)
29#define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT)
30#define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT)
31#define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT)
32#define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT)
33#define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT)
34#define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT)
35#define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT)
36#define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT)
37#define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT)
38#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
39#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
40
41int ice_init_hw(struct ice_hw *hw);
42void ice_deinit_hw(struct ice_hw *hw);
43int ice_check_reset(struct ice_hw *hw);
44int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
45int ice_create_all_ctrlq(struct ice_hw *hw);
46int ice_init_all_ctrlq(struct ice_hw *hw);
47void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);
48void ice_destroy_all_ctrlq(struct ice_hw *hw);
49int
50ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
51 struct ice_rq_event_info *e, u16 *pending);
52int
53ice_get_link_status(struct ice_port_info *pi, bool *link_up);
54int ice_update_link_info(struct ice_port_info *pi);
55int
56ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
57 enum ice_aq_res_access_type access, u32 timeout);
58void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
59int
60ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
61int
62ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
63int ice_aq_alloc_free_res(struct ice_hw *hw,
64 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
65 enum ice_adminq_opc opc);
66bool ice_is_sbq_supported(struct ice_hw *hw);
67struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
68int
69ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
70 struct ice_aq_desc *desc, void *buf, u16 buf_size,
71 struct ice_sq_cd *cd);
72void ice_clear_pxe_mode(struct ice_hw *hw);
73int ice_get_caps(struct ice_hw *hw);
74
75void ice_set_safe_mode_caps(struct ice_hw *hw);
76
77int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
78 u32 rxq_index);
79
80int
81ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
82int
83ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
84int
85ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
86 struct ice_aqc_get_set_rss_keys *keys);
87int
88ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
89 struct ice_aqc_get_set_rss_keys *keys);
90
91bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
92int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
93void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
94extern const struct ice_ctx_ele ice_tlan_ctx_info[];
95int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
96 const struct ice_ctx_ele *ce_info);
97
98extern struct mutex ice_global_cfg_lock_sw;
99
100int
101ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
102 void *buf, u16 buf_size, struct ice_sq_cd *cd);
103int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
104
105int
106ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
107 struct ice_sq_cd *cd);
108int
109ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
110 struct ice_sq_cd *cd);
111int
112ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
113 struct ice_aqc_get_phy_caps_data *caps,
114 struct ice_sq_cd *cd);
115bool ice_is_pf_c827(struct ice_hw *hw);
116bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
117bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
118bool ice_is_cgu_in_netlist(struct ice_hw *hw);
119bool ice_is_gps_in_netlist(struct ice_hw *hw);
120int
121ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
122 u8 *node_part_number, u16 *node_handle);
123int
124ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
125 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
126int
127ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);
128void
129ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
130 u16 link_speeds_bitmap);
131int
132ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
133 struct ice_sq_cd *cd);
134bool ice_is_generic_mac(struct ice_hw *hw);
135bool ice_is_e810(struct ice_hw *hw);
136int ice_clear_pf_cfg(struct ice_hw *hw);
137int
138ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
139 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
140bool ice_fw_supports_link_override(struct ice_hw *hw);
141int
142ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
143 struct ice_port_info *pi);
144bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
145int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
146 u8 serdes_num, int *output);
147int
148ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
149 enum ice_fec_stats_types fec_type, u32 *output);
150
151enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
152enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
153int
154ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
155 bool ena_auto_link_update);
156int
157ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
158 enum ice_fc_mode req_mode);
159bool
160ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
161 struct ice_aqc_set_phy_cfg_data *cfg);
162void
163ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
164 struct ice_aqc_get_phy_caps_data *caps,
165 struct ice_aqc_set_phy_cfg_data *cfg);
166int
167ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
168 enum ice_fec_mode fec);
169int
170ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
171 struct ice_sq_cd *cd);
172int
173ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
174int
175ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
176 struct ice_link_status *link, struct ice_sq_cd *cd);
177int
178ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
179 struct ice_sq_cd *cd);
180int
181ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
182
183int
184ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
185 struct ice_sq_cd *cd);
186int
187ice_aq_get_port_options(struct ice_hw *hw,
188 struct ice_aqc_get_port_options_elem *options,
189 u8 *option_count, u8 lport, bool lport_valid,
190 u8 *active_option_idx, bool *active_option_valid,
191 u8 *pending_option_idx, bool *pending_option_valid);
192int
193ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
194 u8 new_option);
195int
196ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
197 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
198 bool write, struct ice_sq_cd *cd);
199u32 ice_get_link_speed(u16 index);
200
201int
202ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
203 u16 *max_rdmaqs);
204int
205ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
206 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);
207int
208ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
209 u16 *q_id);
210int
211ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
212 u16 *q_handle, u16 *q_ids, u32 *q_teids,
213 enum ice_disq_rst_src rst_src, u16 vmvf_num,
214 struct ice_sq_cd *cd);
215int
216ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
217 u16 *max_lanqs);
218int
219ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
220 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
221 struct ice_sq_cd *cd);
222int
223ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
224 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
225 struct ice_sq_cd *cd);
226int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
227void ice_replay_post(struct ice_hw *hw);
228struct ice_q_ctx *
229ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
230int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag);
231int
232ice_aq_get_cgu_abilities(struct ice_hw *hw,
233 struct ice_aqc_get_cgu_abilities *abilities);
234int
235ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
236 u32 freq, s32 phase_delay);
237int
238ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
239 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);
240int
241ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
242 u8 src_sel, u32 freq, s32 phase_delay);
243int
244ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
245 u8 *src_sel, u32 *freq, u32 *src_freq);
246int
247ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
248 u8 *dpll_state, u8 *config, s64 *phase_offset,
249 u8 *eec_mode);
250int
251ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
252 u8 config, u8 eec_mode);
253int
254ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
255 u8 ref_priority);
256int
257ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
258 u8 *ref_prio);
259int
260ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
261 u32 *cgu_fw_ver);
262
263int
264ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
265 u32 *freq);
266int
267ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
268 u8 *flags, u16 *node_handle);
269int ice_aq_get_sensor_reading(struct ice_hw *hw,
270 struct ice_aqc_get_sensor_reading_resp *data);
271void
272ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
273 u64 *prev_stat, u64 *cur_stat);
274void
275ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
276 u64 *prev_stat, u64 *cur_stat);
277bool ice_is_e810t(struct ice_hw *hw);
278bool ice_is_e822(struct ice_hw *hw);
279bool ice_is_e823(struct ice_hw *hw);
280bool ice_is_e825c(struct ice_hw *hw);
281int
282ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
283 struct ice_aqc_txsched_elem_data *buf);
284int
285ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
286 struct ice_sq_cd *cd);
287int
288ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
289 bool *value, struct ice_sq_cd *cd);
290bool ice_is_100m_speed_supported(struct ice_hw *hw);
291u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
292int
293ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
294 struct ice_sq_cd *cd);
295bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
296int
297ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
298int ice_lldp_execute_pending_mib(struct ice_hw *hw);
299int
300ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
301 u16 bus_addr, __le16 addr, u8 params, u8 *data,
302 struct ice_sq_cd *cd);
303int
304ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
305 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
306 struct ice_sq_cd *cd);
307bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
308#endif /* _ICE_COMMON_H_ */