tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Read Direct Memory Access
8
9maintainers:
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14 MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
15 It contains one line buffer to store the sufficient pixel data, and
16 must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19 for details.
20
21properties:
22 compatible:
23 oneOf:
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
28 - mediatek,mt8195-vdo1-rdma
29 - items:
30 - const: mediatek,mt8188-vdo1-rdma
31 - const: mediatek,mt8195-vdo1-rdma
32
33 reg:
34 maxItems: 1
35
36 mediatek,gce-client-reg:
37 $ref: /schemas/types.yaml#/definitions/phandle-array
38 items:
39 items:
40 - description: phandle of GCE
41 - description: GCE subsys id
42 - description: register offset
43 - description: register size
44 description: The register of client driver can be configured by gce with
45 4 arguments defined in this property. Each GCE subsys id is mapping to
46 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
47
48 mediatek,gce-events:
49 description:
50 The event id which is mapping to the specific hardware event signal
51 to gce. The event id is defined in the gce header
52 include/dt-bindings/gce/<chip>-gce.h of each chips.
53 $ref: /schemas/types.yaml#/definitions/uint32-array
54
55 mediatek,scp:
56 $ref: /schemas/types.yaml#/definitions/phandle
57 description:
58 Phandle to the System Control Processor (SCP) used for initializing
59 and stopping the MDP3, for sending frame data locations to the MDP3's
60 VPU and to install Inter-Processor Interrupt handlers to control
61 processing states.
62
63 power-domains:
64 maxItems: 1
65
66 clocks:
67 items:
68 - description: RDMA clock
69 - description: RSZ clock
70 minItems: 1
71
72 iommus:
73 maxItems: 1
74
75 mboxes:
76 items:
77 - description: used for 1st data pipe from RDMA
78 - description: used for 2nd data pipe from RDMA
79 - description: used for 3rd data pipe from RDMA
80 - description: used for 4th data pipe from RDMA
81 - description: used for the data pipe from SPLIT
82 minItems: 1
83
84 interrupts:
85 maxItems: 1
86
87 '#dma-cells':
88 const: 1
89
90required:
91 - compatible
92 - reg
93 - mediatek,gce-client-reg
94 - power-domains
95 - clocks
96 - iommus
97 - '#dma-cells'
98
99allOf:
100 - if:
101 properties:
102 compatible:
103 contains:
104 const: mediatek,mt8183-mdp3-rdma
105
106 then:
107 properties:
108 clocks:
109 minItems: 2
110
111 mboxes:
112 minItems: 2
113
114 required:
115 - mboxes
116 - mediatek,gce-events
117
118 - if:
119 properties:
120 compatible:
121 contains:
122 const: mediatek,mt8195-mdp3-rdma
123
124 then:
125 properties:
126 clocks:
127 maxItems: 1
128
129 mboxes:
130 minItems: 5
131
132 required:
133 - mediatek,gce-events
134
135 - if:
136 properties:
137 compatible:
138 contains:
139 const: mediatek,mt8195-vdo1-rdma
140
141 then:
142 properties:
143 clocks:
144 maxItems: 1
145
146additionalProperties: false
147
148examples:
149 - |
150 #include <dt-bindings/clock/mt8183-clk.h>
151 #include <dt-bindings/gce/mt8183-gce.h>
152 #include <dt-bindings/power/mt8183-power.h>
153 #include <dt-bindings/memory/mt8183-larb-port.h>
154
155 dma-controller@14001000 {
156 compatible = "mediatek,mt8183-mdp3-rdma";
157 reg = <0x14001000 0x1000>;
158 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
159 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
160 <CMDQ_EVENT_MDP_RDMA0_EOF>;
161 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
162 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
163 <&mmsys CLK_MM_MDP_RSZ1>;
164 iommus = <&iommu>;
165 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
166 <&gce 21 CMDQ_THR_PRIO_LOWEST>;
167 #dma-cells = <1>;
168 };