tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27#include <linux/firmware.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/debugfs.h>
31#include <drm/drm_drv.h>
32
33#include "amdgpu.h"
34#include "amdgpu_pm.h"
35#include "amdgpu_vcn.h"
36#include "soc15d.h"
37
38/* Firmware Names */
39#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
40#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
41#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
42#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
43#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
44#define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
45#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
46#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
47#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
48#define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
49#define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
50#define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
51#define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
52#define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
53#define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
54#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
55#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
56#define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
57#define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
58#define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
59
60MODULE_FIRMWARE(FIRMWARE_RAVEN);
61MODULE_FIRMWARE(FIRMWARE_PICASSO);
62MODULE_FIRMWARE(FIRMWARE_RAVEN2);
63MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
64MODULE_FIRMWARE(FIRMWARE_RENOIR);
65MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
66MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
67MODULE_FIRMWARE(FIRMWARE_NAVI10);
68MODULE_FIRMWARE(FIRMWARE_NAVI14);
69MODULE_FIRMWARE(FIRMWARE_NAVI12);
70MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
71MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
72MODULE_FIRMWARE(FIRMWARE_VANGOGH);
73MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
74MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
75MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
76MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
77MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
78MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
79MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
80
81static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
82
83int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
84{
85 unsigned long bo_size;
86 const char *fw_name;
87 const struct common_firmware_header *hdr;
88 unsigned char fw_check;
89 unsigned int fw_shared_size, log_offset;
90 int i, r;
91
92 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
93 mutex_init(&adev->vcn.vcn_pg_lock);
94 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
95 atomic_set(&adev->vcn.total_submission_cnt, 0);
96 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
97 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
98
99 switch (adev->ip_versions[UVD_HWIP][0]) {
100 case IP_VERSION(1, 0, 0):
101 case IP_VERSION(1, 0, 1):
102 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
103 fw_name = FIRMWARE_RAVEN2;
104 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
105 fw_name = FIRMWARE_PICASSO;
106 else
107 fw_name = FIRMWARE_RAVEN;
108 break;
109 case IP_VERSION(2, 5, 0):
110 fw_name = FIRMWARE_ARCTURUS;
111 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
112 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
113 adev->vcn.indirect_sram = true;
114 break;
115 case IP_VERSION(2, 2, 0):
116 if (adev->apu_flags & AMD_APU_IS_RENOIR)
117 fw_name = FIRMWARE_RENOIR;
118 else
119 fw_name = FIRMWARE_GREEN_SARDINE;
120
121 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
122 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
123 adev->vcn.indirect_sram = true;
124 break;
125 case IP_VERSION(2, 6, 0):
126 fw_name = FIRMWARE_ALDEBARAN;
127 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
128 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
129 adev->vcn.indirect_sram = true;
130 break;
131 case IP_VERSION(2, 0, 0):
132 fw_name = FIRMWARE_NAVI10;
133 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
134 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
135 adev->vcn.indirect_sram = true;
136 break;
137 case IP_VERSION(2, 0, 2):
138 if (adev->asic_type == CHIP_NAVI12)
139 fw_name = FIRMWARE_NAVI12;
140 else
141 fw_name = FIRMWARE_NAVI14;
142 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
143 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
144 adev->vcn.indirect_sram = true;
145 break;
146 case IP_VERSION(3, 0, 0):
147 case IP_VERSION(3, 0, 64):
148 case IP_VERSION(3, 0, 192):
149 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
150 fw_name = FIRMWARE_SIENNA_CICHLID;
151 else
152 fw_name = FIRMWARE_NAVY_FLOUNDER;
153 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
154 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
155 adev->vcn.indirect_sram = true;
156 break;
157 case IP_VERSION(3, 0, 2):
158 fw_name = FIRMWARE_VANGOGH;
159 break;
160 case IP_VERSION(3, 0, 16):
161 fw_name = FIRMWARE_DIMGREY_CAVEFISH;
162 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
163 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
164 adev->vcn.indirect_sram = true;
165 break;
166 case IP_VERSION(3, 0, 33):
167 fw_name = FIRMWARE_BEIGE_GOBY;
168 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
169 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
170 adev->vcn.indirect_sram = true;
171 break;
172 case IP_VERSION(3, 1, 1):
173 fw_name = FIRMWARE_YELLOW_CARP;
174 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
175 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
176 adev->vcn.indirect_sram = true;
177 break;
178 case IP_VERSION(3, 1, 2):
179 fw_name = FIRMWARE_VCN_3_1_2;
180 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
181 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
182 adev->vcn.indirect_sram = true;
183 break;
184 case IP_VERSION(4, 0, 0):
185 fw_name = FIRMWARE_VCN4_0_0;
186 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
187 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
188 adev->vcn.indirect_sram = true;
189 break;
190 case IP_VERSION(4, 0, 2):
191 fw_name = FIRMWARE_VCN4_0_2;
192 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
193 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
194 adev->vcn.indirect_sram = true;
195 break;
196 case IP_VERSION(4, 0, 4):
197 fw_name = FIRMWARE_VCN4_0_4;
198 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
199 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
200 adev->vcn.indirect_sram = true;
201 break;
202 default:
203 return -EINVAL;
204 }
205
206 r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
207 if (r) {
208 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
209 fw_name);
210 return r;
211 }
212
213 r = amdgpu_ucode_validate(adev->vcn.fw);
214 if (r) {
215 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
216 fw_name);
217 release_firmware(adev->vcn.fw);
218 adev->vcn.fw = NULL;
219 return r;
220 }
221
222 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
223 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
224
225 /* Bit 20-23, it is encode major and non-zero for new naming convention.
226 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
227 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
228 * is zero in old naming convention, this field is always zero so far.
229 * These four bits are used to tell which naming convention is present.
230 */
231 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
232 if (fw_check) {
233 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
234
235 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
236 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
237 enc_major = fw_check;
238 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
239 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
240 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
241 enc_major, enc_minor, dec_ver, vep, fw_rev);
242 } else {
243 unsigned int version_major, version_minor, family_id;
244
245 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
246 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
247 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
248 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
249 version_major, version_minor, family_id);
250 }
251
252 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
253 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
254 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
255
256 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){
257 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
258 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
259 } else {
260 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
261 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
262 }
263
264 bo_size += fw_shared_size;
265
266 if (amdgpu_vcnfw_log)
267 bo_size += AMDGPU_VCNFW_LOG_SIZE;
268
269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
270 if (adev->vcn.harvest_config & (1 << i))
271 continue;
272
273 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
274 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
275 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
276 if (r) {
277 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
278 return r;
279 }
280
281 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
282 bo_size - fw_shared_size;
283 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
284 bo_size - fw_shared_size;
285
286 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
287
288 if (amdgpu_vcnfw_log) {
289 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
290 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
291 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
292 }
293
294 if (adev->vcn.indirect_sram) {
295 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
296 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
297 &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
298 if (r) {
299 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
300 return r;
301 }
302 }
303 }
304
305 return 0;
306}
307
308int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
309{
310 int i, j;
311
312 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
313 if (adev->vcn.harvest_config & (1 << j))
314 continue;
315
316 if (adev->vcn.indirect_sram) {
317 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
318 &adev->vcn.inst[j].dpg_sram_gpu_addr,
319 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
320 }
321 kvfree(adev->vcn.inst[j].saved_bo);
322
323 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
324 &adev->vcn.inst[j].gpu_addr,
325 (void **)&adev->vcn.inst[j].cpu_addr);
326
327 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
328
329 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
330 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
331 }
332
333 release_firmware(adev->vcn.fw);
334 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
335 mutex_destroy(&adev->vcn.vcn_pg_lock);
336
337 return 0;
338}
339
340/* from vcn4 and above, only unified queue is used */
341static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
342{
343 struct amdgpu_device *adev = ring->adev;
344 bool ret = false;
345
346 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
347 ret = true;
348
349 return ret;
350}
351
352bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
353{
354 bool ret = false;
355 int vcn_config = adev->vcn.vcn_config[vcn_instance];
356
357 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
358 ret = true;
359 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) {
360 ret = true;
361 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
362 ret = true;
363 }
364
365 return ret;
366}
367
368int amdgpu_vcn_suspend(struct amdgpu_device *adev)
369{
370 unsigned size;
371 void *ptr;
372 int i, idx;
373
374 cancel_delayed_work_sync(&adev->vcn.idle_work);
375
376 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
377 if (adev->vcn.harvest_config & (1 << i))
378 continue;
379 if (adev->vcn.inst[i].vcpu_bo == NULL)
380 return 0;
381
382 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
383 ptr = adev->vcn.inst[i].cpu_addr;
384
385 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
386 if (!adev->vcn.inst[i].saved_bo)
387 return -ENOMEM;
388
389 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
390 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
391 drm_dev_exit(idx);
392 }
393 }
394 return 0;
395}
396
397int amdgpu_vcn_resume(struct amdgpu_device *adev)
398{
399 unsigned size;
400 void *ptr;
401 int i, idx;
402
403 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
404 if (adev->vcn.harvest_config & (1 << i))
405 continue;
406 if (adev->vcn.inst[i].vcpu_bo == NULL)
407 return -EINVAL;
408
409 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
410 ptr = adev->vcn.inst[i].cpu_addr;
411
412 if (adev->vcn.inst[i].saved_bo != NULL) {
413 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
414 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
415 drm_dev_exit(idx);
416 }
417 kvfree(adev->vcn.inst[i].saved_bo);
418 adev->vcn.inst[i].saved_bo = NULL;
419 } else {
420 const struct common_firmware_header *hdr;
421 unsigned offset;
422
423 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
424 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
425 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
426 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
427 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
428 le32_to_cpu(hdr->ucode_size_bytes));
429 drm_dev_exit(idx);
430 }
431 size -= le32_to_cpu(hdr->ucode_size_bytes);
432 ptr += le32_to_cpu(hdr->ucode_size_bytes);
433 }
434 memset_io(ptr, 0, size);
435 }
436 }
437 return 0;
438}
439
440static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
441{
442 struct amdgpu_device *adev =
443 container_of(work, struct amdgpu_device, vcn.idle_work.work);
444 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
445 unsigned int i, j;
446 int r = 0;
447
448 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
449 if (adev->vcn.harvest_config & (1 << j))
450 continue;
451
452 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
453 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
454 }
455
456 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
457 struct dpg_pause_state new_state;
458
459 if (fence[j] ||
460 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
461 new_state.fw_based = VCN_DPG_STATE__PAUSE;
462 else
463 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
464
465 adev->vcn.pause_dpg_mode(adev, j, &new_state);
466 }
467
468 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
469 fences += fence[j];
470 }
471
472 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
473 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
474 AMD_PG_STATE_GATE);
475 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
476 false);
477 if (r)
478 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
479 } else {
480 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
481 }
482}
483
484void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
485{
486 struct amdgpu_device *adev = ring->adev;
487 int r = 0;
488
489 atomic_inc(&adev->vcn.total_submission_cnt);
490
491 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
492 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
493 true);
494 if (r)
495 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
496 }
497
498 mutex_lock(&adev->vcn.vcn_pg_lock);
499 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
500 AMD_PG_STATE_UNGATE);
501
502 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
503 struct dpg_pause_state new_state;
504
505 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
506 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
507 new_state.fw_based = VCN_DPG_STATE__PAUSE;
508 } else {
509 unsigned int fences = 0;
510 unsigned int i;
511
512 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
513 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
514
515 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
516 new_state.fw_based = VCN_DPG_STATE__PAUSE;
517 else
518 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
519 }
520
521 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
522 }
523 mutex_unlock(&adev->vcn.vcn_pg_lock);
524}
525
526void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
527{
528 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
529 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
530 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
531
532 atomic_dec(&ring->adev->vcn.total_submission_cnt);
533
534 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
535}
536
537int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
538{
539 struct amdgpu_device *adev = ring->adev;
540 uint32_t tmp = 0;
541 unsigned i;
542 int r;
543
544 /* VCN in SRIOV does not support direct register read/write */
545 if (amdgpu_sriov_vf(adev))
546 return 0;
547
548 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
549 r = amdgpu_ring_alloc(ring, 3);
550 if (r)
551 return r;
552 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
553 amdgpu_ring_write(ring, 0xDEADBEEF);
554 amdgpu_ring_commit(ring);
555 for (i = 0; i < adev->usec_timeout; i++) {
556 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
557 if (tmp == 0xDEADBEEF)
558 break;
559 udelay(1);
560 }
561
562 if (i >= adev->usec_timeout)
563 r = -ETIMEDOUT;
564
565 return r;
566}
567
568int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
569{
570 struct amdgpu_device *adev = ring->adev;
571 uint32_t rptr;
572 unsigned int i;
573 int r;
574
575 if (amdgpu_sriov_vf(adev))
576 return 0;
577
578 r = amdgpu_ring_alloc(ring, 16);
579 if (r)
580 return r;
581
582 rptr = amdgpu_ring_get_rptr(ring);
583
584 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
585 amdgpu_ring_commit(ring);
586
587 for (i = 0; i < adev->usec_timeout; i++) {
588 if (amdgpu_ring_get_rptr(ring) != rptr)
589 break;
590 udelay(1);
591 }
592
593 if (i >= adev->usec_timeout)
594 r = -ETIMEDOUT;
595
596 return r;
597}
598
599static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
600 struct amdgpu_ib *ib_msg,
601 struct dma_fence **fence)
602{
603 struct amdgpu_device *adev = ring->adev;
604 struct dma_fence *f = NULL;
605 struct amdgpu_job *job;
606 struct amdgpu_ib *ib;
607 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
608 int i, r;
609
610 r = amdgpu_job_alloc_with_ib(adev, 64,
611 AMDGPU_IB_POOL_DIRECT, &job);
612 if (r)
613 goto err;
614
615 ib = &job->ibs[0];
616 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
617 ib->ptr[1] = addr;
618 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
619 ib->ptr[3] = addr >> 32;
620 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
621 ib->ptr[5] = 0;
622 for (i = 6; i < 16; i += 2) {
623 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
624 ib->ptr[i+1] = 0;
625 }
626 ib->length_dw = 16;
627
628 r = amdgpu_job_submit_direct(job, ring, &f);
629 if (r)
630 goto err_free;
631
632 amdgpu_ib_free(adev, ib_msg, f);
633
634 if (fence)
635 *fence = dma_fence_get(f);
636 dma_fence_put(f);
637
638 return 0;
639
640err_free:
641 amdgpu_job_free(job);
642err:
643 amdgpu_ib_free(adev, ib_msg, f);
644 return r;
645}
646
647static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
648 struct amdgpu_ib *ib)
649{
650 struct amdgpu_device *adev = ring->adev;
651 uint32_t *msg;
652 int r, i;
653
654 memset(ib, 0, sizeof(*ib));
655 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
656 AMDGPU_IB_POOL_DIRECT,
657 ib);
658 if (r)
659 return r;
660
661 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
662 msg[0] = cpu_to_le32(0x00000028);
663 msg[1] = cpu_to_le32(0x00000038);
664 msg[2] = cpu_to_le32(0x00000001);
665 msg[3] = cpu_to_le32(0x00000000);
666 msg[4] = cpu_to_le32(handle);
667 msg[5] = cpu_to_le32(0x00000000);
668 msg[6] = cpu_to_le32(0x00000001);
669 msg[7] = cpu_to_le32(0x00000028);
670 msg[8] = cpu_to_le32(0x00000010);
671 msg[9] = cpu_to_le32(0x00000000);
672 msg[10] = cpu_to_le32(0x00000007);
673 msg[11] = cpu_to_le32(0x00000000);
674 msg[12] = cpu_to_le32(0x00000780);
675 msg[13] = cpu_to_le32(0x00000440);
676 for (i = 14; i < 1024; ++i)
677 msg[i] = cpu_to_le32(0x0);
678
679 return 0;
680}
681
682static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
683 struct amdgpu_ib *ib)
684{
685 struct amdgpu_device *adev = ring->adev;
686 uint32_t *msg;
687 int r, i;
688
689 memset(ib, 0, sizeof(*ib));
690 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
691 AMDGPU_IB_POOL_DIRECT,
692 ib);
693 if (r)
694 return r;
695
696 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
697 msg[0] = cpu_to_le32(0x00000028);
698 msg[1] = cpu_to_le32(0x00000018);
699 msg[2] = cpu_to_le32(0x00000000);
700 msg[3] = cpu_to_le32(0x00000002);
701 msg[4] = cpu_to_le32(handle);
702 msg[5] = cpu_to_le32(0x00000000);
703 for (i = 6; i < 1024; ++i)
704 msg[i] = cpu_to_le32(0x0);
705
706 return 0;
707}
708
709int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
710{
711 struct dma_fence *fence = NULL;
712 struct amdgpu_ib ib;
713 long r;
714
715 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
716 if (r)
717 goto error;
718
719 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
720 if (r)
721 goto error;
722 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
723 if (r)
724 goto error;
725
726 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
727 if (r)
728 goto error;
729
730 r = dma_fence_wait_timeout(fence, false, timeout);
731 if (r == 0)
732 r = -ETIMEDOUT;
733 else if (r > 0)
734 r = 0;
735
736 dma_fence_put(fence);
737error:
738 return r;
739}
740
741static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
742 uint32_t ib_pack_in_dw, bool enc)
743{
744 uint32_t *ib_checksum;
745
746 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
747 ib->ptr[ib->length_dw++] = 0x30000002;
748 ib_checksum = &ib->ptr[ib->length_dw++];
749 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
750
751 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
752 ib->ptr[ib->length_dw++] = 0x30000001;
753 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
754 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
755
756 return ib_checksum;
757}
758
759static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
760 uint32_t ib_pack_in_dw)
761{
762 uint32_t i;
763 uint32_t checksum = 0;
764
765 for (i = 0; i < ib_pack_in_dw; i++)
766 checksum += *(*ib_checksum + 2 + i);
767
768 **ib_checksum = checksum;
769}
770
771static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
772 struct amdgpu_ib *ib_msg,
773 struct dma_fence **fence)
774{
775 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
776 unsigned int ib_size_dw = 64;
777 struct amdgpu_device *adev = ring->adev;
778 struct dma_fence *f = NULL;
779 struct amdgpu_job *job;
780 struct amdgpu_ib *ib;
781 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
782 bool sq = amdgpu_vcn_using_unified_queue(ring);
783 uint32_t *ib_checksum;
784 uint32_t ib_pack_in_dw;
785 int i, r;
786
787 if (sq)
788 ib_size_dw += 8;
789
790 r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
791 AMDGPU_IB_POOL_DIRECT, &job);
792 if (r)
793 goto err;
794
795 ib = &job->ibs[0];
796 ib->length_dw = 0;
797
798 /* single queue headers */
799 if (sq) {
800 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
801 + 4 + 2; /* engine info + decoding ib in dw */
802 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
803 }
804
805 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
806 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
807 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
808 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
809 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
810
811 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
812 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
813 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
814
815 for (i = ib->length_dw; i < ib_size_dw; ++i)
816 ib->ptr[i] = 0x0;
817
818 if (sq)
819 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
820
821 r = amdgpu_job_submit_direct(job, ring, &f);
822 if (r)
823 goto err_free;
824
825 amdgpu_ib_free(adev, ib_msg, f);
826
827 if (fence)
828 *fence = dma_fence_get(f);
829 dma_fence_put(f);
830
831 return 0;
832
833err_free:
834 amdgpu_job_free(job);
835err:
836 amdgpu_ib_free(adev, ib_msg, f);
837 return r;
838}
839
840int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
841{
842 struct dma_fence *fence = NULL;
843 struct amdgpu_ib ib;
844 long r;
845
846 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
847 if (r)
848 goto error;
849
850 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
851 if (r)
852 goto error;
853 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
854 if (r)
855 goto error;
856
857 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
858 if (r)
859 goto error;
860
861 r = dma_fence_wait_timeout(fence, false, timeout);
862 if (r == 0)
863 r = -ETIMEDOUT;
864 else if (r > 0)
865 r = 0;
866
867 dma_fence_put(fence);
868error:
869 return r;
870}
871
872int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
873{
874 struct amdgpu_device *adev = ring->adev;
875 uint32_t rptr;
876 unsigned i;
877 int r;
878
879 if (amdgpu_sriov_vf(adev))
880 return 0;
881
882 r = amdgpu_ring_alloc(ring, 16);
883 if (r)
884 return r;
885
886 rptr = amdgpu_ring_get_rptr(ring);
887
888 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
889 amdgpu_ring_commit(ring);
890
891 for (i = 0; i < adev->usec_timeout; i++) {
892 if (amdgpu_ring_get_rptr(ring) != rptr)
893 break;
894 udelay(1);
895 }
896
897 if (i >= adev->usec_timeout)
898 r = -ETIMEDOUT;
899
900 return r;
901}
902
903static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
904 struct amdgpu_ib *ib_msg,
905 struct dma_fence **fence)
906{
907 unsigned int ib_size_dw = 16;
908 struct amdgpu_job *job;
909 struct amdgpu_ib *ib;
910 struct dma_fence *f = NULL;
911 uint32_t *ib_checksum = NULL;
912 uint64_t addr;
913 bool sq = amdgpu_vcn_using_unified_queue(ring);
914 int i, r;
915
916 if (sq)
917 ib_size_dw += 8;
918
919 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
920 AMDGPU_IB_POOL_DIRECT, &job);
921 if (r)
922 return r;
923
924 ib = &job->ibs[0];
925 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
926
927 ib->length_dw = 0;
928
929 if (sq)
930 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
931
932 ib->ptr[ib->length_dw++] = 0x00000018;
933 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
934 ib->ptr[ib->length_dw++] = handle;
935 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
936 ib->ptr[ib->length_dw++] = addr;
937 ib->ptr[ib->length_dw++] = 0x0000000b;
938
939 ib->ptr[ib->length_dw++] = 0x00000014;
940 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
941 ib->ptr[ib->length_dw++] = 0x0000001c;
942 ib->ptr[ib->length_dw++] = 0x00000000;
943 ib->ptr[ib->length_dw++] = 0x00000000;
944
945 ib->ptr[ib->length_dw++] = 0x00000008;
946 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
947
948 for (i = ib->length_dw; i < ib_size_dw; ++i)
949 ib->ptr[i] = 0x0;
950
951 if (sq)
952 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
953
954 r = amdgpu_job_submit_direct(job, ring, &f);
955 if (r)
956 goto err;
957
958 if (fence)
959 *fence = dma_fence_get(f);
960 dma_fence_put(f);
961
962 return 0;
963
964err:
965 amdgpu_job_free(job);
966 return r;
967}
968
969static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
970 struct amdgpu_ib *ib_msg,
971 struct dma_fence **fence)
972{
973 unsigned int ib_size_dw = 16;
974 struct amdgpu_job *job;
975 struct amdgpu_ib *ib;
976 struct dma_fence *f = NULL;
977 uint32_t *ib_checksum = NULL;
978 uint64_t addr;
979 bool sq = amdgpu_vcn_using_unified_queue(ring);
980 int i, r;
981
982 if (sq)
983 ib_size_dw += 8;
984
985 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
986 AMDGPU_IB_POOL_DIRECT, &job);
987 if (r)
988 return r;
989
990 ib = &job->ibs[0];
991 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
992
993 ib->length_dw = 0;
994
995 if (sq)
996 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
997
998 ib->ptr[ib->length_dw++] = 0x00000018;
999 ib->ptr[ib->length_dw++] = 0x00000001;
1000 ib->ptr[ib->length_dw++] = handle;
1001 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1002 ib->ptr[ib->length_dw++] = addr;
1003 ib->ptr[ib->length_dw++] = 0x0000000b;
1004
1005 ib->ptr[ib->length_dw++] = 0x00000014;
1006 ib->ptr[ib->length_dw++] = 0x00000002;
1007 ib->ptr[ib->length_dw++] = 0x0000001c;
1008 ib->ptr[ib->length_dw++] = 0x00000000;
1009 ib->ptr[ib->length_dw++] = 0x00000000;
1010
1011 ib->ptr[ib->length_dw++] = 0x00000008;
1012 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
1013
1014 for (i = ib->length_dw; i < ib_size_dw; ++i)
1015 ib->ptr[i] = 0x0;
1016
1017 if (sq)
1018 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
1019
1020 r = amdgpu_job_submit_direct(job, ring, &f);
1021 if (r)
1022 goto err;
1023
1024 if (fence)
1025 *fence = dma_fence_get(f);
1026 dma_fence_put(f);
1027
1028 return 0;
1029
1030err:
1031 amdgpu_job_free(job);
1032 return r;
1033}
1034
1035int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1036{
1037 struct amdgpu_device *adev = ring->adev;
1038 struct dma_fence *fence = NULL;
1039 struct amdgpu_ib ib;
1040 long r;
1041
1042 memset(&ib, 0, sizeof(ib));
1043 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
1044 AMDGPU_IB_POOL_DIRECT,
1045 &ib);
1046 if (r)
1047 return r;
1048
1049 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
1050 if (r)
1051 goto error;
1052
1053 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
1054 if (r)
1055 goto error;
1056
1057 r = dma_fence_wait_timeout(fence, false, timeout);
1058 if (r == 0)
1059 r = -ETIMEDOUT;
1060 else if (r > 0)
1061 r = 0;
1062
1063error:
1064 amdgpu_ib_free(adev, &ib, fence);
1065 dma_fence_put(fence);
1066
1067 return r;
1068}
1069
1070int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1071{
1072 long r;
1073
1074 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1075 if (r)
1076 goto error;
1077
1078 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1079
1080error:
1081 return r;
1082}
1083
1084enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1085{
1086 switch(ring) {
1087 case 0:
1088 return AMDGPU_RING_PRIO_0;
1089 case 1:
1090 return AMDGPU_RING_PRIO_1;
1091 case 2:
1092 return AMDGPU_RING_PRIO_2;
1093 default:
1094 return AMDGPU_RING_PRIO_0;
1095 }
1096}
1097
1098void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1099{
1100 int i;
1101 unsigned int idx;
1102
1103 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1104 const struct common_firmware_header *hdr;
1105 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1106
1107 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1108 if (adev->vcn.harvest_config & (1 << i))
1109 continue;
1110 /* currently only support 2 FW instances */
1111 if (i >= 2) {
1112 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1113 break;
1114 }
1115 idx = AMDGPU_UCODE_ID_VCN + i;
1116 adev->firmware.ucode[idx].ucode_id = idx;
1117 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1118 adev->firmware.fw_size +=
1119 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1120 }
1121 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1122 }
1123}
1124
1125/*
1126 * debugfs for mapping vcn firmware log buffer.
1127 */
1128#if defined(CONFIG_DEBUG_FS)
1129static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1130 size_t size, loff_t *pos)
1131{
1132 struct amdgpu_vcn_inst *vcn;
1133 void *log_buf;
1134 volatile struct amdgpu_vcn_fwlog *plog;
1135 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1136 unsigned int read_num[2] = {0};
1137
1138 vcn = file_inode(f)->i_private;
1139 if (!vcn)
1140 return -ENODEV;
1141
1142 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1143 return -EFAULT;
1144
1145 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1146
1147 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1148 read_pos = plog->rptr;
1149 write_pos = plog->wptr;
1150
1151 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1152 return -EFAULT;
1153
1154 if (!size || (read_pos == write_pos))
1155 return 0;
1156
1157 if (write_pos > read_pos) {
1158 available = write_pos - read_pos;
1159 read_num[0] = min(size, (size_t)available);
1160 } else {
1161 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1162 available = read_num[0] + write_pos - plog->header_size;
1163 if (size > available)
1164 read_num[1] = write_pos - plog->header_size;
1165 else if (size > read_num[0])
1166 read_num[1] = size - read_num[0];
1167 else
1168 read_num[0] = size;
1169 }
1170
1171 for (i = 0; i < 2; i++) {
1172 if (read_num[i]) {
1173 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1174 read_pos = plog->header_size;
1175 if (read_num[i] == copy_to_user((buf + read_bytes),
1176 (log_buf + read_pos), read_num[i]))
1177 return -EFAULT;
1178
1179 read_bytes += read_num[i];
1180 read_pos += read_num[i];
1181 }
1182 }
1183
1184 plog->rptr = read_pos;
1185 *pos += read_bytes;
1186 return read_bytes;
1187}
1188
1189static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1190 .owner = THIS_MODULE,
1191 .read = amdgpu_debugfs_vcn_fwlog_read,
1192 .llseek = default_llseek
1193};
1194#endif
1195
1196void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1197 struct amdgpu_vcn_inst *vcn)
1198{
1199#if defined(CONFIG_DEBUG_FS)
1200 struct drm_minor *minor = adev_to_drm(adev)->primary;
1201 struct dentry *root = minor->debugfs_root;
1202 char name[32];
1203
1204 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1205 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn,
1206 &amdgpu_debugfs_vcnfwlog_fops,
1207 AMDGPU_VCNFW_LOG_SIZE);
1208#endif
1209}
1210
1211void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1212{
1213#if defined(CONFIG_DEBUG_FS)
1214 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1215 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1216 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1217 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1218 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1219 + vcn->fw_shared.log_offset;
1220 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1221 fw_log->is_enabled = 1;
1222 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1223 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1224 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1225
1226 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1227 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1228 log_buf->rptr = log_buf->header_size;
1229 log_buf->wptr = log_buf->header_size;
1230 log_buf->wrapped = 0;
1231#endif
1232}
1233
1234int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1235 struct amdgpu_irq_src *source,
1236 struct amdgpu_iv_entry *entry)
1237{
1238 struct ras_common_if *ras_if = adev->vcn.ras_if;
1239 struct ras_dispatch_if ih_data = {
1240 .entry = entry,
1241 };
1242
1243 if (!ras_if)
1244 return 0;
1245
1246 ih_data.head = *ras_if;
1247 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1248
1249 return 0;
1250}