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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2021 Linaro Ltd.
5 */
6#ifndef _GSI_REG_H_
7#define _GSI_REG_H_
8
9/* === Only "gsi.c" should include this file === */
10
11#include <linux/bits.h>
12
13/**
14 * DOC: GSI Registers
15 *
16 * GSI registers are located within the "gsi" address space defined by Device
17 * Tree. The offset of each register within that space is specified by
18 * symbols defined below. The GSI address space is mapped to virtual memory
19 * space in gsi_init(). All GSI registers are 32 bits wide.
20 *
21 * Each register type is duplicated for a number of instances of something.
22 * For example, each GSI channel has its own set of registers defining its
23 * configuration. The offset to a channel's set of registers is computed
24 * based on a "base" offset plus an additional "stride" amount computed
25 * from the channel's ID. For such registers, the offset is computed by a
26 * function-like macro that takes a parameter used in the computation.
27 *
28 * The offset of a register dependent on execution environment is computed
29 * by a macro that is supplied a parameter "ee". The "ee" value is a member
30 * of the gsi_ee_id enumerated type.
31 *
32 * The offset of a channel register is computed by a macro that is supplied a
33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30
34 * (though the actual limit is hardware-dependent).
35 *
36 * The offset of an event register is computed by a macro that is supplied a
37 * parameter "ev". The "ev" value is an event id whose maximum value is 15
38 * (though the actual limit is hardware-dependent).
39 */
40
41/* GSI EE registers as a group are shifted downward by a fixed constant amount
42 * for IPA versions 4.5 and beyond. This applies to all GSI registers we use
43 * *except* the ones that disable inter-EE interrupts for channels and event
44 * channels.
45 *
46 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to
47 * the mapped range is held in gsi->virt_raw. The inter-EE interrupt
48 * registers are accessed using that pointer.
49 *
50 * Most registers are accessed using gsi->virt, which is a copy of the "raw"
51 * pointer, adjusted downward by the fixed amount.
52 */
53#define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */
54
55/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
56
57#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \
58 GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
59#define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \
60 (0x0000c020 + 0x1000 * (ee))
61
62#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \
63 GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
64#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
65 (0x0000c024 + 0x1000 * (ee))
66
67/* All other register offsets are relative to gsi->virt */
68
69/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
70enum gsi_channel_type {
71 GSI_CHANNEL_TYPE_MHI = 0x0,
72 GSI_CHANNEL_TYPE_XHCI = 0x1,
73 GSI_CHANNEL_TYPE_GPI = 0x2,
74 GSI_CHANNEL_TYPE_XDCI = 0x3,
75 GSI_CHANNEL_TYPE_WDI2 = 0x4,
76 GSI_CHANNEL_TYPE_GCI = 0x5,
77 GSI_CHANNEL_TYPE_WDI3 = 0x6,
78 GSI_CHANNEL_TYPE_MHIP = 0x7,
79 GSI_CHANNEL_TYPE_AQC = 0x8,
80 GSI_CHANNEL_TYPE_11AD = 0x9,
81};
82
83#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
84 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
85#define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
86 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
87#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
88#define CHTYPE_DIR_FMASK GENMASK(3, 3)
89#define EE_FMASK GENMASK(7, 4)
90#define CHID_FMASK GENMASK(12, 8)
91/* The next field is present for IPA v4.5 and above */
92#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
93#define ERINDEX_FMASK GENMASK(18, 14)
94#define CHSTATE_FMASK GENMASK(23, 20)
95#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
96
97/* Encoded value for CH_C_CNTXT_0 register channel protocol fields */
98static inline u32
99chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type)
100{
101 u32 val;
102
103 val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK);
104 if (version < IPA_VERSION_4_5)
105 return val;
106
107 /* Encode upper bit(s) as well */
108 type >>= hweight32(CHTYPE_PROTOCOL_FMASK);
109 val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK);
110
111 return val;
112}
113
114#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
115 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
116#define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
117 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
118
119/* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */
120static inline u32 r_length_encoded(enum ipa_version version, u32 length)
121{
122 if (version < IPA_VERSION_4_9)
123 return u32_encode_bits(length, GENMASK(15, 0));
124 return u32_encode_bits(length, GENMASK(19, 0));
125}
126
127#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
128 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
129#define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
130 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
131
132#define GSI_CH_C_CNTXT_3_OFFSET(ch) \
133 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
134#define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
135 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
136
137#define GSI_CH_C_QOS_OFFSET(ch) \
138 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
139#define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
140 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
141#define WRR_WEIGHT_FMASK GENMASK(3, 0)
142#define MAX_PREFETCH_FMASK GENMASK(8, 8)
143#define USE_DB_ENG_FMASK GENMASK(9, 9)
144/* The next field is only present for IPA v4.0, v4.1, and v4.2 */
145#define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10)
146/* The next two fields are present for IPA v4.5 and above */
147#define PREFETCH_MODE_FMASK GENMASK(13, 10)
148#define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16)
149/* The next field is present for IPA v4.9 and above */
150#define DB_IN_BYTES GENMASK(24, 24)
151
152/** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */
153enum gsi_prefetch_mode {
154 GSI_USE_PREFETCH_BUFS = 0x0,
155 GSI_ESCAPE_BUF_ONLY = 0x1,
156 GSI_SMART_PREFETCH = 0x2,
157 GSI_FREE_PREFETCH = 0x3,
158};
159
160#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
161 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
162#define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
163 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
164
165#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
166 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
167#define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
168 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
169
170#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
171 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
172#define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
173 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
174
175#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
176 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
177#define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
178 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
179
180#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
181 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
182#define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
183 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
184/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
185#define EV_CHTYPE_FMASK GENMASK(3, 0)
186#define EV_EE_FMASK GENMASK(7, 4)
187#define EV_EVCHID_FMASK GENMASK(15, 8)
188#define EV_INTYPE_FMASK GENMASK(16, 16)
189#define EV_CHSTATE_FMASK GENMASK(23, 20)
190#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24)
191
192#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
193 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
194#define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
195 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
196/* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */
197static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length)
198{
199 if (version < IPA_VERSION_4_9)
200 return u32_encode_bits(length, GENMASK(15, 0));
201 return u32_encode_bits(length, GENMASK(19, 0));
202}
203
204#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
205 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
206#define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
207 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
208
209#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
210 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
211#define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
212 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
213
214#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
215 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
216#define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
217 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
218
219#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
220 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
221#define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
222 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
223#define MODT_FMASK GENMASK(15, 0)
224#define MODC_FMASK GENMASK(23, 16)
225#define MOD_CNT_FMASK GENMASK(31, 24)
226
227#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
228 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
229#define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
230 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
231
232#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
233 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
234#define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
235 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
236
237#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
238 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
239#define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
240 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
241
242#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
243 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
244#define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
245 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
246
247#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
248 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
249#define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
250 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
251
252#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
253 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
254#define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
255 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
256
257#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
258 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
259#define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
260 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
261
262#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
263 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
264#define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
265 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
266
267#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
268 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
269#define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
270 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
271
272#define GSI_GSI_STATUS_OFFSET \
273 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
274#define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
275 (0x0001f000 + 0x4000 * (ee))
276#define ENABLED_FMASK GENMASK(0, 0)
277
278#define GSI_CH_CMD_OFFSET \
279 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
280#define GSI_EE_N_CH_CMD_OFFSET(ee) \
281 (0x0001f008 + 0x4000 * (ee))
282#define CH_CHID_FMASK GENMASK(7, 0)
283#define CH_OPCODE_FMASK GENMASK(31, 24)
284
285/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
286enum gsi_ch_cmd_opcode {
287 GSI_CH_ALLOCATE = 0x0,
288 GSI_CH_START = 0x1,
289 GSI_CH_STOP = 0x2,
290 GSI_CH_RESET = 0x9,
291 GSI_CH_DE_ALLOC = 0xa,
292 GSI_CH_DB_STOP = 0xb,
293};
294
295#define GSI_EV_CH_CMD_OFFSET \
296 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
297#define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
298 (0x0001f010 + 0x4000 * (ee))
299#define EV_CHID_FMASK GENMASK(7, 0)
300#define EV_OPCODE_FMASK GENMASK(31, 24)
301
302/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
303enum gsi_evt_cmd_opcode {
304 GSI_EVT_ALLOCATE = 0x0,
305 GSI_EVT_RESET = 0x9,
306 GSI_EVT_DE_ALLOC = 0xa,
307};
308
309#define GSI_GENERIC_CMD_OFFSET \
310 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
311#define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
312 (0x0001f018 + 0x4000 * (ee))
313#define GENERIC_OPCODE_FMASK GENMASK(4, 0)
314#define GENERIC_CHID_FMASK GENMASK(9, 5)
315#define GENERIC_EE_FMASK GENMASK(13, 10)
316#define GENERIC_PARAMS_FMASK GENMASK(31, 24) /* IPA v4.11+ */
317
318/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
319enum gsi_generic_cmd_opcode {
320 GSI_GENERIC_HALT_CHANNEL = 0x1,
321 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
322 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */
323 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */
324 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */
325};
326
327/* The next register is present for IPA v3.5.1 and above */
328#define GSI_GSI_HW_PARAM_2_OFFSET \
329 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
330#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
331 (0x0001f040 + 0x4000 * (ee))
332#define IRAM_SIZE_FMASK GENMASK(2, 0)
333#define NUM_CH_PER_EE_FMASK GENMASK(7, 3)
334#define NUM_EV_PER_EE_FMASK GENMASK(12, 8)
335#define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13)
336#define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14)
337/* Fields below are present for IPA v4.0 and above */
338#define GSI_USE_SDMA_FMASK GENMASK(15, 15)
339#define GSI_SDMA_N_INT_FMASK GENMASK(18, 16)
340#define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19)
341#define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27)
342/* Fields below are present for IPA v4.2 and above */
343#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30)
344#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31)
345
346/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
347enum gsi_iram_size {
348 IRAM_SIZE_ONE_KB = 0x0,
349 IRAM_SIZE_TWO_KB = 0x1,
350 /* The next two values are available for IPA v4.0 and above */
351 IRAM_SIZE_TWO_N_HALF_KB = 0x2,
352 IRAM_SIZE_THREE_KB = 0x3,
353 /* The next two values are available for IPA v4.5 and above */
354 IRAM_SIZE_THREE_N_HALF_KB = 0x4,
355 IRAM_SIZE_FOUR_KB = 0x5,
356};
357
358/* IRQ condition for each type is cleared by writing type-specific register */
359#define GSI_CNTXT_TYPE_IRQ_OFFSET \
360 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
361#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
362 (0x0001f080 + 0x4000 * (ee))
363#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
364 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
365#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
366 (0x0001f088 + 0x4000 * (ee))
367
368/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
369enum gsi_irq_type_id {
370 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */
371 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */
372 GSI_GLOB_EE = 0x2, /* global/general event */
373 GSI_IEOB = 0x3, /* TRE completion */
374 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */
375 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */
376 GSI_GENERAL = 0x6, /* general-purpose event */
377};
378
379#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
380 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
381#define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
382 (0x0001f090 + 0x4000 * (ee))
383
384#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
385 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
386#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
387 (0x0001f094 + 0x4000 * (ee))
388
389#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
390 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
391#define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
392 (0x0001f098 + 0x4000 * (ee))
393
394#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
395 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
396#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
397 (0x0001f09c + 0x4000 * (ee))
398
399#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
400 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
401#define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
402 (0x0001f0a0 + 0x4000 * (ee))
403
404#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
405 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
406#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
407 (0x0001f0a4 + 0x4000 * (ee))
408
409#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
410 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
411#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
412 (0x0001f0b0 + 0x4000 * (ee))
413
414#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
415 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
416#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
417 (0x0001f0b8 + 0x4000 * (ee))
418
419#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
420 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
421#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
422 (0x0001f0c0 + 0x4000 * (ee))
423
424#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
425 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
426#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
427 (0x0001f100 + 0x4000 * (ee))
428#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
429 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
430#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
431 (0x0001f108 + 0x4000 * (ee))
432#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
433 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
434#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
435 (0x0001f110 + 0x4000 * (ee))
436/* Values here are bit positions in the GLOB_IRQ_* registers */
437enum gsi_global_irq_id {
438 ERROR_INT = 0x0,
439 GP_INT1 = 0x1,
440 GP_INT2 = 0x2,
441 GP_INT3 = 0x3,
442};
443
444#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
445 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
446#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
447 (0x0001f118 + 0x4000 * (ee))
448#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
449 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
450#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
451 (0x0001f120 + 0x4000 * (ee))
452#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
453 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
454#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
455 (0x0001f128 + 0x4000 * (ee))
456/* Values here are bit positions in the (general) GSI_IRQ_* registers */
457enum gsi_general_id {
458 BREAK_POINT = 0x0,
459 BUS_ERROR = 0x1,
460 CMD_FIFO_OVRFLOW = 0x2,
461 MCS_STACK_OVRFLOW = 0x3,
462};
463
464#define GSI_CNTXT_INTSET_OFFSET \
465 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
466#define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
467 (0x0001f180 + 0x4000 * (ee))
468#define INTYPE_FMASK GENMASK(0, 0)
469
470#define GSI_ERROR_LOG_OFFSET \
471 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
472#define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
473 (0x0001f200 + 0x4000 * (ee))
474
475/* Fields below are present for IPA v3.5.1 and above */
476#define ERR_ARG3_FMASK GENMASK(3, 0)
477#define ERR_ARG2_FMASK GENMASK(7, 4)
478#define ERR_ARG1_FMASK GENMASK(11, 8)
479#define ERR_CODE_FMASK GENMASK(15, 12)
480#define ERR_VIRT_IDX_FMASK GENMASK(23, 19)
481#define ERR_TYPE_FMASK GENMASK(27, 24)
482#define ERR_EE_FMASK GENMASK(31, 28)
483
484/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
485enum gsi_err_code {
486 GSI_INVALID_TRE = 0x1,
487 GSI_OUT_OF_BUFFERS = 0x2,
488 GSI_OUT_OF_RESOURCES = 0x3,
489 GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
490 GSI_EVT_RING_EMPTY = 0x5,
491 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
492 /* 7 is not assigned */
493 GSI_HWO_1 = 0x8,
494};
495
496/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
497enum gsi_err_type {
498 GSI_ERR_TYPE_GLOB = 0x1,
499 GSI_ERR_TYPE_CHAN = 0x2,
500 GSI_ERR_TYPE_EVT = 0x3,
501};
502
503#define GSI_ERROR_LOG_CLR_OFFSET \
504 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
505#define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
506 (0x0001f210 + 0x4000 * (ee))
507
508#define GSI_CNTXT_SCRATCH_0_OFFSET \
509 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
510#define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
511 (0x0001f400 + 0x4000 * (ee))
512#define INTER_EE_RESULT_FMASK GENMASK(2, 0)
513#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5)
514
515/** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */
516enum gsi_generic_ee_result {
517 GENERIC_EE_SUCCESS = 0x1,
518 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2,
519 GENERIC_EE_INCORRECT_DIRECTION = 0x3,
520 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
521 GENERIC_EE_INCORRECT_CHANNEL = 0x5,
522 GENERIC_EE_RETRY = 0x6,
523 GENERIC_EE_NO_RESOURCES = 0x7,
524};
525
526#endif /* _GSI_REG_H_ */