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1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type {
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185};
186
187enum atom_dp_vs_preemph_def{
188 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
189 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
190 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
191 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
192 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
193 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
194 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
195 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
196 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
197 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
198};
199
200#define BIOS_ATOM_PREFIX "ATOMBIOS"
201#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
202#define BIOS_STRING_LENGTH 43
203
204/*
205enum atom_string_def{
206asic_bus_type_pcie_string = "PCI_EXPRESS",
207atom_fire_gl_string = "FGL",
208atom_bios_string = "ATOM"
209};
210*/
211
212#pragma pack(1) /* BIOS data must use byte aligment*/
213
214enum atombios_image_offset{
215 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048,
216 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002,
217 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94,
218 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/
219 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f,
220 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e,
221 OFFSET_TO_VBIOS_PART_NUMBER = 0x80,
222 OFFSET_TO_VBIOS_DATE = 0x50,
223};
224
225/****************************************************************************
226* Common header for all tables (Data table, Command function).
227* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
228* And the pointer actually points to this header.
229****************************************************************************/
230
231struct atom_common_table_header
232{
233 uint16_t structuresize;
234 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
235 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
236};
237
238/****************************************************************************
239* Structure stores the ROM header.
240****************************************************************************/
241struct atom_rom_header_v2_2
242{
243 struct atom_common_table_header table_header;
244 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
245 uint16_t bios_segment_address;
246 uint16_t protectedmodeoffset;
247 uint16_t configfilenameoffset;
248 uint16_t crc_block_offset;
249 uint16_t vbios_bootupmessageoffset;
250 uint16_t int10_offset;
251 uint16_t pcibusdevinitcode;
252 uint16_t iobaseaddress;
253 uint16_t subsystem_vendor_id;
254 uint16_t subsystem_id;
255 uint16_t pci_info_offset;
256 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
257 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
258 uint16_t reserved;
259 uint32_t pspdirtableoffset;
260};
261
262/*==============================hw function portion======================================================================*/
263
264
265/****************************************************************************
266* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
267* The real functionality of each function is associated with the parameter structure version when defined
268* For all internal cmd function definitions, please reference to atomstruct.h
269****************************************************************************/
270struct atom_master_list_of_command_functions_v2_1{
271 uint16_t asic_init; //Function
272 uint16_t cmd_function1; //used as an internal one
273 uint16_t cmd_function2; //used as an internal one
274 uint16_t cmd_function3; //used as an internal one
275 uint16_t digxencodercontrol; //Function
276 uint16_t cmd_function5; //used as an internal one
277 uint16_t cmd_function6; //used as an internal one
278 uint16_t cmd_function7; //used as an internal one
279 uint16_t cmd_function8; //used as an internal one
280 uint16_t cmd_function9; //used as an internal one
281 uint16_t setengineclock; //Function
282 uint16_t setmemoryclock; //Function
283 uint16_t setpixelclock; //Function
284 uint16_t enabledisppowergating; //Function
285 uint16_t cmd_function14; //used as an internal one
286 uint16_t cmd_function15; //used as an internal one
287 uint16_t cmd_function16; //used as an internal one
288 uint16_t cmd_function17; //used as an internal one
289 uint16_t cmd_function18; //used as an internal one
290 uint16_t cmd_function19; //used as an internal one
291 uint16_t cmd_function20; //used as an internal one
292 uint16_t cmd_function21; //used as an internal one
293 uint16_t cmd_function22; //used as an internal one
294 uint16_t cmd_function23; //used as an internal one
295 uint16_t cmd_function24; //used as an internal one
296 uint16_t cmd_function25; //used as an internal one
297 uint16_t cmd_function26; //used as an internal one
298 uint16_t cmd_function27; //used as an internal one
299 uint16_t cmd_function28; //used as an internal one
300 uint16_t cmd_function29; //used as an internal one
301 uint16_t cmd_function30; //used as an internal one
302 uint16_t cmd_function31; //used as an internal one
303 uint16_t cmd_function32; //used as an internal one
304 uint16_t cmd_function33; //used as an internal one
305 uint16_t blankcrtc; //Function
306 uint16_t enablecrtc; //Function
307 uint16_t cmd_function36; //used as an internal one
308 uint16_t cmd_function37; //used as an internal one
309 uint16_t cmd_function38; //used as an internal one
310 uint16_t cmd_function39; //used as an internal one
311 uint16_t cmd_function40; //used as an internal one
312 uint16_t getsmuclockinfo; //Function
313 uint16_t selectcrtc_source; //Function
314 uint16_t cmd_function43; //used as an internal one
315 uint16_t cmd_function44; //used as an internal one
316 uint16_t cmd_function45; //used as an internal one
317 uint16_t setdceclock; //Function
318 uint16_t getmemoryclock; //Function
319 uint16_t getengineclock; //Function
320 uint16_t setcrtc_usingdtdtiming; //Function
321 uint16_t externalencodercontrol; //Function
322 uint16_t cmd_function51; //used as an internal one
323 uint16_t cmd_function52; //used as an internal one
324 uint16_t cmd_function53; //used as an internal one
325 uint16_t processi2cchanneltransaction;//Function
326 uint16_t cmd_function55; //used as an internal one
327 uint16_t cmd_function56; //used as an internal one
328 uint16_t cmd_function57; //used as an internal one
329 uint16_t cmd_function58; //used as an internal one
330 uint16_t cmd_function59; //used as an internal one
331 uint16_t computegpuclockparam; //Function
332 uint16_t cmd_function61; //used as an internal one
333 uint16_t cmd_function62; //used as an internal one
334 uint16_t dynamicmemorysettings; //Function function
335 uint16_t memorytraining; //Function function
336 uint16_t cmd_function65; //used as an internal one
337 uint16_t cmd_function66; //used as an internal one
338 uint16_t setvoltage; //Function
339 uint16_t cmd_function68; //used as an internal one
340 uint16_t readefusevalue; //Function
341 uint16_t cmd_function70; //used as an internal one
342 uint16_t cmd_function71; //used as an internal one
343 uint16_t cmd_function72; //used as an internal one
344 uint16_t cmd_function73; //used as an internal one
345 uint16_t cmd_function74; //used as an internal one
346 uint16_t cmd_function75; //used as an internal one
347 uint16_t dig1transmittercontrol; //Function
348 uint16_t cmd_function77; //used as an internal one
349 uint16_t processauxchanneltransaction;//Function
350 uint16_t cmd_function79; //used as an internal one
351 uint16_t getvoltageinfo; //Function
352};
353
354struct atom_master_command_function_v2_1
355{
356 struct atom_common_table_header table_header;
357 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
358};
359
360/****************************************************************************
361* Structures used in every command function
362****************************************************************************/
363struct atom_function_attribute
364{
365 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
366 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
367 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
368};
369
370
371/****************************************************************************
372* Common header for all hw functions.
373* Every function pointed by _master_list_of_hw_function has this common header.
374* And the pointer actually points to this header.
375****************************************************************************/
376struct atom_rom_hw_function_header
377{
378 struct atom_common_table_header func_header;
379 struct atom_function_attribute func_attrib;
380};
381
382
383/*==============================sw data table portion======================================================================*/
384/****************************************************************************
385* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
386* The real name of each table is given when its data structure version is defined
387****************************************************************************/
388struct atom_master_list_of_data_tables_v2_1{
389 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
390 uint16_t multimedia_info;
391 uint16_t smc_dpm_info;
392 uint16_t sw_datatable3;
393 uint16_t firmwareinfo; /* Shared by various SW components */
394 uint16_t sw_datatable5;
395 uint16_t lcd_info; /* Shared by various SW components */
396 uint16_t sw_datatable7;
397 uint16_t smu_info;
398 uint16_t sw_datatable9;
399 uint16_t sw_datatable10;
400 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
401 uint16_t gpio_pin_lut; /* Shared by various SW components */
402 uint16_t sw_datatable13;
403 uint16_t gfx_info;
404 uint16_t powerplayinfo; /* Shared by various SW components */
405 uint16_t sw_datatable16;
406 uint16_t sw_datatable17;
407 uint16_t sw_datatable18;
408 uint16_t sw_datatable19;
409 uint16_t sw_datatable20;
410 uint16_t sw_datatable21;
411 uint16_t displayobjectinfo; /* Shared by various SW components */
412 uint16_t indirectioaccess; /* used as an internal one */
413 uint16_t umc_info; /* Shared by various SW components */
414 uint16_t sw_datatable25;
415 uint16_t sw_datatable26;
416 uint16_t dce_info; /* Shared by various SW components */
417 uint16_t vram_info; /* Shared by various SW components */
418 uint16_t sw_datatable29;
419 uint16_t integratedsysteminfo; /* Shared by various SW components */
420 uint16_t asic_profiling_info; /* Shared by various SW components */
421 uint16_t voltageobject_info; /* shared by various SW components */
422 uint16_t sw_datatable33;
423 uint16_t sw_datatable34;
424};
425
426
427struct atom_master_data_table_v2_1
428{
429 struct atom_common_table_header table_header;
430 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
431};
432
433
434struct atom_dtd_format
435{
436 uint16_t pixclk;
437 uint16_t h_active;
438 uint16_t h_blanking_time;
439 uint16_t v_active;
440 uint16_t v_blanking_time;
441 uint16_t h_sync_offset;
442 uint16_t h_sync_width;
443 uint16_t v_sync_offset;
444 uint16_t v_syncwidth;
445 uint16_t reserved;
446 uint16_t reserved0;
447 uint8_t h_border;
448 uint8_t v_border;
449 uint16_t miscinfo;
450 uint8_t atom_mode_id;
451 uint8_t refreshrate;
452};
453
454/* atom_dtd_format.modemiscinfo defintion */
455enum atom_dtd_format_modemiscinfo{
456 ATOM_HSYNC_POLARITY = 0x0002,
457 ATOM_VSYNC_POLARITY = 0x0004,
458 ATOM_H_REPLICATIONBY2 = 0x0010,
459 ATOM_V_REPLICATIONBY2 = 0x0020,
460 ATOM_INTERLACE = 0x0080,
461 ATOM_COMPOSITESYNC = 0x0040,
462};
463
464
465/* utilitypipeline
466 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
467 * the location of it can't change
468*/
469
470
471/*
472 ***************************************************************************
473 Data Table firmwareinfo structure
474 ***************************************************************************
475*/
476
477struct atom_firmware_info_v3_1
478{
479 struct atom_common_table_header table_header;
480 uint32_t firmware_revision;
481 uint32_t bootup_sclk_in10khz;
482 uint32_t bootup_mclk_in10khz;
483 uint32_t firmware_capability; // enum atombios_firmware_capability
484 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
485 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
486 uint16_t bootup_vddc_mv;
487 uint16_t bootup_vddci_mv;
488 uint16_t bootup_mvddc_mv;
489 uint16_t bootup_vddgfx_mv;
490 uint8_t mem_module_id;
491 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
492 uint8_t reserved1[2];
493 uint32_t mc_baseaddr_high;
494 uint32_t mc_baseaddr_low;
495 uint32_t reserved2[6];
496};
497
498/* Total 32bit cap indication */
499enum atombios_firmware_capability
500{
501 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
502 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
503 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
504 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
505 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
506 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
507 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
508 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
509 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
510};
511
512enum atom_cooling_solution_id{
513 AIR_COOLING = 0x00,
514 LIQUID_COOLING = 0x01
515};
516
517struct atom_firmware_info_v3_2 {
518 struct atom_common_table_header table_header;
519 uint32_t firmware_revision;
520 uint32_t bootup_sclk_in10khz;
521 uint32_t bootup_mclk_in10khz;
522 uint32_t firmware_capability; // enum atombios_firmware_capability
523 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
524 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
525 uint16_t bootup_vddc_mv;
526 uint16_t bootup_vddci_mv;
527 uint16_t bootup_mvddc_mv;
528 uint16_t bootup_vddgfx_mv;
529 uint8_t mem_module_id;
530 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
531 uint8_t reserved1[2];
532 uint32_t mc_baseaddr_high;
533 uint32_t mc_baseaddr_low;
534 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
535 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
536 uint8_t board_i2c_feature_slave_addr;
537 uint8_t reserved3;
538 uint16_t bootup_mvddq_mv;
539 uint16_t bootup_mvpp_mv;
540 uint32_t zfbstartaddrin16mb;
541 uint32_t reserved2[3];
542};
543
544struct atom_firmware_info_v3_3
545{
546 struct atom_common_table_header table_header;
547 uint32_t firmware_revision;
548 uint32_t bootup_sclk_in10khz;
549 uint32_t bootup_mclk_in10khz;
550 uint32_t firmware_capability; // enum atombios_firmware_capability
551 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
552 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
553 uint16_t bootup_vddc_mv;
554 uint16_t bootup_vddci_mv;
555 uint16_t bootup_mvddc_mv;
556 uint16_t bootup_vddgfx_mv;
557 uint8_t mem_module_id;
558 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
559 uint8_t reserved1[2];
560 uint32_t mc_baseaddr_high;
561 uint32_t mc_baseaddr_low;
562 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
563 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
564 uint8_t board_i2c_feature_slave_addr;
565 uint8_t reserved3;
566 uint16_t bootup_mvddq_mv;
567 uint16_t bootup_mvpp_mv;
568 uint32_t zfbstartaddrin16mb;
569 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
570 uint32_t reserved2[2];
571};
572
573struct atom_firmware_info_v3_4 {
574 struct atom_common_table_header table_header;
575 uint32_t firmware_revision;
576 uint32_t bootup_sclk_in10khz;
577 uint32_t bootup_mclk_in10khz;
578 uint32_t firmware_capability; // enum atombios_firmware_capability
579 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
580 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
581 uint16_t bootup_vddc_mv;
582 uint16_t bootup_vddci_mv;
583 uint16_t bootup_mvddc_mv;
584 uint16_t bootup_vddgfx_mv;
585 uint8_t mem_module_id;
586 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
587 uint8_t reserved1[2];
588 uint32_t mc_baseaddr_high;
589 uint32_t mc_baseaddr_low;
590 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
591 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
592 uint8_t board_i2c_feature_slave_addr;
593 uint8_t ras_rom_i2c_slave_addr;
594 uint16_t bootup_mvddq_mv;
595 uint16_t bootup_mvpp_mv;
596 uint32_t zfbstartaddrin16mb;
597 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
598 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
599 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap
600 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap
601 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap
602 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap
603 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
604 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
605 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
606 uint32_t pspbl_init_done_reg_addr;
607 uint32_t pspbl_init_done_value;
608 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done
609 uint32_t reserved[2];
610};
611
612/*
613 ***************************************************************************
614 Data Table lcd_info structure
615 ***************************************************************************
616*/
617
618struct lcd_info_v2_1
619{
620 struct atom_common_table_header table_header;
621 struct atom_dtd_format lcd_timing;
622 uint16_t backlight_pwm;
623 uint16_t special_handle_cap;
624 uint16_t panel_misc;
625 uint16_t lvds_max_slink_pclk;
626 uint16_t lvds_ss_percentage;
627 uint16_t lvds_ss_rate_10hz;
628 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
629 uint8_t pwr_on_de_to_vary_bl;
630 uint8_t pwr_down_vary_bloff_to_de;
631 uint8_t pwr_down_de_to_digoff;
632 uint8_t pwr_off_delay;
633 uint8_t pwr_on_vary_bl_to_blon;
634 uint8_t pwr_down_bloff_to_vary_bloff;
635 uint8_t panel_bpc;
636 uint8_t dpcd_edp_config_cap;
637 uint8_t dpcd_max_link_rate;
638 uint8_t dpcd_max_lane_count;
639 uint8_t dpcd_max_downspread;
640 uint8_t min_allowed_bl_level;
641 uint8_t max_allowed_bl_level;
642 uint8_t bootup_bl_level;
643 uint8_t dplvdsrxid;
644 uint32_t reserved1[8];
645};
646
647/* lcd_info_v2_1.panel_misc defintion */
648enum atom_lcd_info_panel_misc{
649 ATOM_PANEL_MISC_FPDI =0x0002,
650};
651
652//uceDPToLVDSRxId
653enum atom_lcd_info_dptolvds_rx_id
654{
655 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
656 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
657 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
658};
659
660
661/*
662 ***************************************************************************
663 Data Table gpio_pin_lut structure
664 ***************************************************************************
665*/
666
667struct atom_gpio_pin_assignment
668{
669 uint32_t data_a_reg_index;
670 uint8_t gpio_bitshift;
671 uint8_t gpio_mask_bitshift;
672 uint8_t gpio_id;
673 uint8_t reserved;
674};
675
676/* atom_gpio_pin_assignment.gpio_id definition */
677enum atom_gpio_pin_assignment_gpio_id {
678 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
679 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
680 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
681
682 /* gpio_id pre-define id for multiple usage */
683 /* GPIO use to control PCIE_VDDC in certain SLT board */
684 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
685 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
686 PP_AC_DC_SWITCH_GPIO_PINID = 60,
687 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
688 VDDC_VRHOT_GPIO_PINID = 61,
689 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
690 VDDC_PCC_GPIO_PINID = 62,
691 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
692 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
693 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
694 DRAM_SELF_REFRESH_GPIO_PINID = 64,
695 /* Thermal interrupt output->system thermal chip GPIO pin */
696 THERMAL_INT_OUTPUT_GPIO_PINID =65,
697};
698
699
700struct atom_gpio_pin_lut_v2_1
701{
702 struct atom_common_table_header table_header;
703 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
704 struct atom_gpio_pin_assignment gpio_pin[8];
705};
706
707
708/*
709 ***************************************************************************
710 Data Table vram_usagebyfirmware structure
711 ***************************************************************************
712*/
713
714struct vram_usagebyfirmware_v2_1
715{
716 struct atom_common_table_header table_header;
717 uint32_t start_address_in_kb;
718 uint16_t used_by_firmware_in_kb;
719 uint16_t used_by_driver_in_kb;
720};
721
722
723/*
724 ***************************************************************************
725 Data Table displayobjectinfo structure
726 ***************************************************************************
727*/
728
729enum atom_object_record_type_id
730{
731 ATOM_I2C_RECORD_TYPE =1,
732 ATOM_HPD_INT_RECORD_TYPE =2,
733 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
734 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
735 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
736 ATOM_ENCODER_CAP_RECORD_TYPE=20,
737 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
738 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
739 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23,
740 ATOM_RECORD_END_TYPE =0xFF,
741};
742
743struct atom_common_record_header
744{
745 uint8_t record_type; //An emun to indicate the record type
746 uint8_t record_size; //The size of the whole record in byte
747};
748
749struct atom_i2c_record
750{
751 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
752 uint8_t i2c_id;
753 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
754};
755
756struct atom_hpd_int_record
757{
758 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
759 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
760 uint8_t plugin_pin_state;
761};
762
763// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
764enum atom_encoder_caps_def
765{
766 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
767 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
768 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
769 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
770 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
771 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
772 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board
773 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board
774 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board
775 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
776};
777
778struct atom_encoder_caps_record
779{
780 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
781 uint32_t encodercaps;
782};
783
784enum atom_connector_caps_def
785{
786 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
787 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
788};
789
790struct atom_disp_connector_caps_record
791{
792 struct atom_common_record_header record_header;
793 uint32_t connectcaps;
794};
795
796//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
797struct atom_gpio_pin_control_pair
798{
799 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
800 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
801};
802
803struct atom_object_gpio_cntl_record
804{
805 struct atom_common_record_header record_header;
806 uint8_t flag; // Future expnadibility
807 uint8_t number_of_pins; // Number of GPIO pins used to control the object
808 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
809};
810
811//Definitions for GPIO pin state
812enum atom_gpio_pin_control_pinstate_def
813{
814 GPIO_PIN_TYPE_INPUT = 0x00,
815 GPIO_PIN_TYPE_OUTPUT = 0x10,
816 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
817
818//For GPIO_PIN_TYPE_OUTPUT the following is defined
819 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
820 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
821 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
822 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
823};
824
825// Indexes to GPIO array in GLSync record
826// GLSync record is for Frame Lock/Gen Lock feature.
827enum atom_glsync_record_gpio_index_def
828{
829 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
830 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
831 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
832 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
833 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
834 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
835 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
836 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
837 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
838 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
839};
840
841
842struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
843{
844 struct atom_common_record_header record_header;
845 uint8_t hpd_pin_map[8];
846};
847
848struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
849{
850 struct atom_common_record_header record_header;
851 uint8_t aux_ddc_map[8];
852};
853
854struct atom_connector_forced_tmds_cap_record
855{
856 struct atom_common_record_header record_header;
857 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
858 uint8_t maxtmdsclkrate_in2_5mhz;
859 uint8_t reserved;
860};
861
862struct atom_connector_layout_info
863{
864 uint16_t connectorobjid;
865 uint8_t connector_type;
866 uint8_t position;
867};
868
869// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
870enum atom_connector_layout_info_connector_type_def
871{
872 CONNECTOR_TYPE_DVI_D = 1,
873
874 CONNECTOR_TYPE_HDMI = 4,
875 CONNECTOR_TYPE_DISPLAY_PORT = 5,
876 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
877};
878
879struct atom_bracket_layout_record
880{
881 struct atom_common_record_header record_header;
882 uint8_t bracketlen;
883 uint8_t bracketwidth;
884 uint8_t conn_num;
885 uint8_t reserved;
886 struct atom_connector_layout_info conn_info[1];
887};
888
889enum atom_display_device_tag_def{
890 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
891 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability
892 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
893 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
894 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
895 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
896 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
897 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
898 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
899};
900
901struct atom_display_object_path_v2
902{
903 uint16_t display_objid; //Connector Object ID or Misc Object ID
904 uint16_t disp_recordoffset;
905 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
906 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
907 uint16_t encoder_recordoffset;
908 uint16_t extencoder_recordoffset;
909 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
910 uint8_t priority_id;
911 uint8_t reserved;
912};
913
914struct display_object_info_table_v1_4
915{
916 struct atom_common_table_header table_header;
917 uint16_t supporteddevices;
918 uint8_t number_of_path;
919 uint8_t reserved;
920 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
921};
922
923
924/*
925 ***************************************************************************
926 Data Table dce_info structure
927 ***************************************************************************
928*/
929struct atom_display_controller_info_v4_1
930{
931 struct atom_common_table_header table_header;
932 uint32_t display_caps;
933 uint32_t bootup_dispclk_10khz;
934 uint16_t dce_refclk_10khz;
935 uint16_t i2c_engine_refclk_10khz;
936 uint16_t dvi_ss_percentage; // in unit of 0.001%
937 uint16_t dvi_ss_rate_10hz;
938 uint16_t hdmi_ss_percentage; // in unit of 0.001%
939 uint16_t hdmi_ss_rate_10hz;
940 uint16_t dp_ss_percentage; // in unit of 0.001%
941 uint16_t dp_ss_rate_10hz;
942 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
943 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
944 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
945 uint8_t ss_reserved;
946 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
947 uint8_t reserved1[3];
948 uint16_t dpphy_refclk_10khz;
949 uint16_t reserved2;
950 uint8_t dceip_min_ver;
951 uint8_t dceip_max_ver;
952 uint8_t max_disp_pipe_num;
953 uint8_t max_vbios_active_disp_pipe_num;
954 uint8_t max_ppll_num;
955 uint8_t max_disp_phy_num;
956 uint8_t max_aux_pairs;
957 uint8_t remotedisplayconfig;
958 uint8_t reserved3[8];
959};
960
961struct atom_display_controller_info_v4_2
962{
963 struct atom_common_table_header table_header;
964 uint32_t display_caps;
965 uint32_t bootup_dispclk_10khz;
966 uint16_t dce_refclk_10khz;
967 uint16_t i2c_engine_refclk_10khz;
968 uint16_t dvi_ss_percentage; // in unit of 0.001%
969 uint16_t dvi_ss_rate_10hz;
970 uint16_t hdmi_ss_percentage; // in unit of 0.001%
971 uint16_t hdmi_ss_rate_10hz;
972 uint16_t dp_ss_percentage; // in unit of 0.001%
973 uint16_t dp_ss_rate_10hz;
974 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
975 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
976 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
977 uint8_t ss_reserved;
978 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
979 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
980 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
981 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
982 uint16_t dpphy_refclk_10khz;
983 uint16_t reserved2;
984 uint8_t dcnip_min_ver;
985 uint8_t dcnip_max_ver;
986 uint8_t max_disp_pipe_num;
987 uint8_t max_vbios_active_disp_pipe_num;
988 uint8_t max_ppll_num;
989 uint8_t max_disp_phy_num;
990 uint8_t max_aux_pairs;
991 uint8_t remotedisplayconfig;
992 uint8_t reserved3[8];
993};
994
995struct atom_display_controller_info_v4_3
996{
997 struct atom_common_table_header table_header;
998 uint32_t display_caps;
999 uint32_t bootup_dispclk_10khz;
1000 uint16_t dce_refclk_10khz;
1001 uint16_t i2c_engine_refclk_10khz;
1002 uint16_t dvi_ss_percentage; // in unit of 0.001%
1003 uint16_t dvi_ss_rate_10hz;
1004 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1005 uint16_t hdmi_ss_rate_10hz;
1006 uint16_t dp_ss_percentage; // in unit of 0.001%
1007 uint16_t dp_ss_rate_10hz;
1008 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1009 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1010 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1011 uint8_t ss_reserved;
1012 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1013 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1014 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1015 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1016 uint16_t dpphy_refclk_10khz;
1017 uint16_t reserved2;
1018 uint8_t dcnip_min_ver;
1019 uint8_t dcnip_max_ver;
1020 uint8_t max_disp_pipe_num;
1021 uint8_t max_vbios_active_disp_pipe_num;
1022 uint8_t max_ppll_num;
1023 uint8_t max_disp_phy_num;
1024 uint8_t max_aux_pairs;
1025 uint8_t remotedisplayconfig;
1026 uint8_t reserved3[8];
1027};
1028
1029struct atom_display_controller_info_v4_4 {
1030 struct atom_common_table_header table_header;
1031 uint32_t display_caps;
1032 uint32_t bootup_dispclk_10khz;
1033 uint16_t dce_refclk_10khz;
1034 uint16_t i2c_engine_refclk_10khz;
1035 uint16_t dvi_ss_percentage; // in unit of 0.001%
1036 uint16_t dvi_ss_rate_10hz;
1037 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1038 uint16_t hdmi_ss_rate_10hz;
1039 uint16_t dp_ss_percentage; // in unit of 0.001%
1040 uint16_t dp_ss_rate_10hz;
1041 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1042 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1043 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1044 uint8_t ss_reserved;
1045 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1046 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1047 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1048 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1049 uint16_t dpphy_refclk_10khz;
1050 uint16_t hw_chip_id;
1051 uint8_t dcnip_min_ver;
1052 uint8_t dcnip_max_ver;
1053 uint8_t max_disp_pipe_num;
1054 uint8_t max_vbios_active_disp_pipum;
1055 uint8_t max_ppll_num;
1056 uint8_t max_disp_phy_num;
1057 uint8_t max_aux_pairs;
1058 uint8_t remotedisplayconfig;
1059 uint32_t dispclk_pll_vco_freq;
1060 uint32_t dp_ref_clk_freq;
1061 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1062 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1063 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1064 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1065 uint16_t dc_golden_table_ver;
1066 uint32_t reserved3[3];
1067};
1068
1069struct atom_dc_golden_table_v1
1070{
1071 uint32_t aux_dphy_rx_control0_val;
1072 uint32_t aux_dphy_tx_control_val;
1073 uint32_t aux_dphy_rx_control1_val;
1074 uint32_t dc_gpio_aux_ctrl_0_val;
1075 uint32_t dc_gpio_aux_ctrl_1_val;
1076 uint32_t dc_gpio_aux_ctrl_2_val;
1077 uint32_t dc_gpio_aux_ctrl_3_val;
1078 uint32_t dc_gpio_aux_ctrl_4_val;
1079 uint32_t dc_gpio_aux_ctrl_5_val;
1080 uint32_t reserved[23];
1081};
1082
1083enum dce_info_caps_def
1084{
1085 // only for VBIOS
1086 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
1087 // only for VBIOS
1088 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
1089 // only for VBIOS
1090 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
1091 // only for VBIOS
1092 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20,
1093 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1094};
1095
1096/*
1097 ***************************************************************************
1098 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
1099 ***************************************************************************
1100*/
1101struct atom_ext_display_path
1102{
1103 uint16_t device_tag; //A bit vector to show what devices are supported
1104 uint16_t device_acpi_enum; //16bit device ACPI id.
1105 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
1106 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1107 uint8_t hpdlut_index; //An index into external HPD pin LUT
1108 uint16_t ext_encoder_objid; //external encoder object id
1109 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
1110 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1111 uint16_t caps;
1112 uint16_t reserved;
1113};
1114
1115//usCaps
1116enum ext_display_path_cap_def {
1117 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001,
1118 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002,
1119 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C,
1120 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip
1121 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1122 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1123};
1124
1125struct atom_external_display_connection_info
1126{
1127 struct atom_common_table_header table_header;
1128 uint8_t guid[16]; // a GUID is a 16 byte long string
1129 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
1130 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1131 uint8_t stereopinid; // use for eDP panel
1132 uint8_t remotedisplayconfig;
1133 uint8_t edptolvdsrxid;
1134 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1135 uint8_t reserved[3]; // for potential expansion
1136};
1137
1138/*
1139 ***************************************************************************
1140 Data Table integratedsysteminfo structure
1141 ***************************************************************************
1142*/
1143
1144struct atom_camera_dphy_timing_param
1145{
1146 uint8_t profile_id; // SENSOR_PROFILES
1147 uint32_t param;
1148};
1149
1150struct atom_camera_dphy_elec_param
1151{
1152 uint16_t param[3];
1153};
1154
1155struct atom_camera_module_info
1156{
1157 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1158 uint8_t module_name[8];
1159 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1160};
1161
1162struct atom_camera_flashlight_info
1163{
1164 uint8_t flashlight_id; // 0: Rear, 1: Front
1165 uint8_t name[8];
1166};
1167
1168struct atom_camera_data
1169{
1170 uint32_t versionCode;
1171 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1172 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1173 struct atom_camera_dphy_elec_param dphy_param;
1174 uint32_t crc_val; // CRC
1175};
1176
1177
1178struct atom_14nm_dpphy_dvihdmi_tuningset
1179{
1180 uint32_t max_symclk_in10khz;
1181 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1182 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1183 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1184 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1185 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1186 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1187 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1188};
1189
1190struct atom_14nm_dpphy_dp_setting{
1191 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1192 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1193 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1194 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1195};
1196
1197struct atom_14nm_dpphy_dp_tuningset{
1198 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1199 uint8_t version;
1200 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1201 uint16_t reserved;
1202 struct atom_14nm_dpphy_dp_setting dptuning[10];
1203};
1204
1205struct atom_14nm_dig_transmitter_info_header_v4_0{
1206 struct atom_common_table_header table_header;
1207 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1208 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1209 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1210};
1211
1212struct atom_14nm_combphy_tmds_vs_set
1213{
1214 uint8_t sym_clk;
1215 uint8_t dig_mode;
1216 uint8_t phy_sel;
1217 uint16_t common_mar_deemph_nom__margin_deemph_val;
1218 uint8_t common_seldeemph60__deemph_6db_4_val;
1219 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1220 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1221 uint8_t margin_deemph_lane0__deemph_sel_val;
1222};
1223
1224struct atom_DCN_dpphy_dvihdmi_tuningset
1225{
1226 uint32_t max_symclk_in10khz;
1227 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1228 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1229 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1230 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1231 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1232 uint8_t reserved1;
1233 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1234 uint8_t reserved2;
1235};
1236
1237struct atom_DCN_dpphy_dp_setting{
1238 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1239 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1240 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1241 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1242 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1243};
1244
1245struct atom_DCN_dpphy_dp_tuningset{
1246 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1247 uint8_t version;
1248 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting
1249 uint16_t reserved;
1250 struct atom_DCN_dpphy_dp_setting dptunings[10];
1251};
1252
1253struct atom_i2c_reg_info {
1254 uint8_t ucI2cRegIndex;
1255 uint8_t ucI2cRegVal;
1256};
1257
1258struct atom_hdmi_retimer_redriver_set {
1259 uint8_t HdmiSlvAddr;
1260 uint8_t HdmiRegNum;
1261 uint8_t Hdmi6GRegNum;
1262 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1263 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1264};
1265
1266struct atom_integrated_system_info_v1_11
1267{
1268 struct atom_common_table_header table_header;
1269 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1270 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1271 uint32_t system_config;
1272 uint32_t cpucapinfo;
1273 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1274 uint16_t gpuclk_ss_type;
1275 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1276 uint16_t lvds_ss_rate_10hz;
1277 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1278 uint16_t hdmi_ss_rate_10hz;
1279 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1280 uint16_t dvi_ss_rate_10hz;
1281 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1282 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1283 uint16_t backlight_pwm_hz; // pwm frequency in hz
1284 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1285 uint8_t umachannelnumber; // number of memory channels
1286 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1287 uint8_t pwr_on_de_to_vary_bl;
1288 uint8_t pwr_down_vary_bloff_to_de;
1289 uint8_t pwr_down_de_to_digoff;
1290 uint8_t pwr_off_delay;
1291 uint8_t pwr_on_vary_bl_to_blon;
1292 uint8_t pwr_down_bloff_to_vary_bloff;
1293 uint8_t min_allowed_bl_level;
1294 uint8_t htc_hyst_limit;
1295 uint8_t htc_tmp_limit;
1296 uint8_t reserved1;
1297 uint8_t reserved2;
1298 struct atom_external_display_connection_info extdispconninfo;
1299 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1300 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1301 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1302 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1303 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1304 struct atom_camera_data camera_info;
1305 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1306 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1307 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1308 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1309 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1310 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1311 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1312 uint32_t reserved[66];
1313};
1314
1315struct atom_integrated_system_info_v1_12
1316{
1317 struct atom_common_table_header table_header;
1318 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1319 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1320 uint32_t system_config;
1321 uint32_t cpucapinfo;
1322 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1323 uint16_t gpuclk_ss_type;
1324 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1325 uint16_t lvds_ss_rate_10hz;
1326 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1327 uint16_t hdmi_ss_rate_10hz;
1328 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1329 uint16_t dvi_ss_rate_10hz;
1330 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1331 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1332 uint16_t backlight_pwm_hz; // pwm frequency in hz
1333 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1334 uint8_t umachannelnumber; // number of memory channels
1335 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1336 uint8_t pwr_on_de_to_vary_bl;
1337 uint8_t pwr_down_vary_bloff_to_de;
1338 uint8_t pwr_down_de_to_digoff;
1339 uint8_t pwr_off_delay;
1340 uint8_t pwr_on_vary_bl_to_blon;
1341 uint8_t pwr_down_bloff_to_vary_bloff;
1342 uint8_t min_allowed_bl_level;
1343 uint8_t htc_hyst_limit;
1344 uint8_t htc_tmp_limit;
1345 uint8_t reserved1;
1346 uint8_t reserved2;
1347 struct atom_external_display_connection_info extdispconninfo;
1348 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
1349 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset;
1350 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
1351 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
1352 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
1353 struct atom_camera_data camera_info;
1354 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1355 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1356 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1357 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1358 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
1359 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
1360 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
1361 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
1362 uint32_t reserved[63];
1363};
1364
1365struct edp_info_table
1366{
1367 uint16_t edp_backlight_pwm_hz;
1368 uint16_t edp_ss_percentage;
1369 uint16_t edp_ss_rate_10hz;
1370 uint16_t reserved1;
1371 uint32_t reserved2;
1372 uint8_t edp_pwr_on_off_delay;
1373 uint8_t edp_pwr_on_vary_bl_to_blon;
1374 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1375 uint8_t edp_panel_bpc;
1376 uint8_t edp_bootup_bl_level;
1377 uint8_t reserved3[3];
1378 uint32_t reserved4[3];
1379};
1380
1381struct atom_integrated_system_info_v2_1
1382{
1383 struct atom_common_table_header table_header;
1384 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1385 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1386 uint32_t system_config;
1387 uint32_t cpucapinfo;
1388 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1389 uint16_t gpuclk_ss_type;
1390 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1391 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1392 uint8_t umachannelnumber; // number of memory channels
1393 uint8_t htc_hyst_limit;
1394 uint8_t htc_tmp_limit;
1395 uint8_t reserved1;
1396 uint8_t reserved2;
1397 struct edp_info_table edp1_info;
1398 struct edp_info_table edp2_info;
1399 uint32_t reserved3[8];
1400 struct atom_external_display_connection_info extdispconninfo;
1401 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
1402 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6
1403 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
1404 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
1405 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1406 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
1407 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
1408 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
1409 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
1410 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
1411 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1412 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1413 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1414 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1415 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1416 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1417 uint32_t reserved7[32];
1418
1419};
1420
1421struct atom_n6_display_phy_tuning_set {
1422 uint8_t display_signal_type;
1423 uint8_t phy_sel;
1424 uint8_t preset_level;
1425 uint8_t reserved1;
1426 uint32_t reserved2;
1427 uint32_t speed_upto;
1428 uint8_t tx_vboost_level;
1429 uint8_t tx_vreg_v2i;
1430 uint8_t tx_vregdrv_byp;
1431 uint8_t tx_term_cntl;
1432 uint8_t tx_peak_level;
1433 uint8_t tx_slew_en;
1434 uint8_t tx_eq_pre;
1435 uint8_t tx_eq_main;
1436 uint8_t tx_eq_post;
1437 uint8_t tx_en_inv_pre;
1438 uint8_t tx_en_inv_post;
1439 uint8_t reserved3;
1440 uint32_t reserved4;
1441 uint32_t reserved5;
1442 uint32_t reserved6;
1443};
1444
1445struct atom_display_phy_tuning_info {
1446 struct atom_common_table_header table_header;
1447 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
1448};
1449
1450struct atom_integrated_system_info_v2_2
1451{
1452 struct atom_common_table_header table_header;
1453 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1454 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1455 uint32_t system_config;
1456 uint32_t cpucapinfo;
1457 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1458 uint16_t gpuclk_ss_type;
1459 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1460 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1461 uint8_t umachannelnumber; // number of memory channels
1462 uint8_t htc_hyst_limit;
1463 uint8_t htc_tmp_limit;
1464 uint8_t reserved1;
1465 uint8_t reserved2;
1466 struct edp_info_table edp1_info;
1467 struct edp_info_table edp2_info;
1468 uint32_t reserved3[8];
1469 struct atom_external_display_connection_info extdispconninfo;
1470
1471 uint32_t reserved4[189];
1472};
1473
1474// system_config
1475enum atom_system_vbiosmisc_def{
1476 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1477};
1478
1479
1480// gpucapinfo
1481enum atom_system_gpucapinf_def{
1482 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1483};
1484
1485//dpphy_override
1486enum atom_sysinfo_dpphy_override_def{
1487 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1488 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1489 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1490 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1491 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1492};
1493
1494//lvds_misc
1495enum atom_sys_info_lvds_misc_def
1496{
1497 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1498 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1499 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1500};
1501
1502
1503//memorytype DMI Type 17 offset 12h - Memory Type
1504enum atom_dmi_t17_mem_type_def{
1505 OtherMemType = 0x01, ///< Assign 01 to Other
1506 UnknownMemType, ///< Assign 02 to Unknown
1507 DramMemType, ///< Assign 03 to DRAM
1508 EdramMemType, ///< Assign 04 to EDRAM
1509 VramMemType, ///< Assign 05 to VRAM
1510 SramMemType, ///< Assign 06 to SRAM
1511 RamMemType, ///< Assign 07 to RAM
1512 RomMemType, ///< Assign 08 to ROM
1513 FlashMemType, ///< Assign 09 to Flash
1514 EepromMemType, ///< Assign 10 to EEPROM
1515 FepromMemType, ///< Assign 11 to FEPROM
1516 EpromMemType, ///< Assign 12 to EPROM
1517 CdramMemType, ///< Assign 13 to CDRAM
1518 ThreeDramMemType, ///< Assign 14 to 3DRAM
1519 SdramMemType, ///< Assign 15 to SDRAM
1520 SgramMemType, ///< Assign 16 to SGRAM
1521 RdramMemType, ///< Assign 17 to RDRAM
1522 DdrMemType, ///< Assign 18 to DDR
1523 Ddr2MemType, ///< Assign 19 to DDR2
1524 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1525 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1526 Fbd2MemType, ///< Assign 25 to FBD2
1527 Ddr4MemType, ///< Assign 26 to DDR4
1528 LpDdrMemType, ///< Assign 27 to LPDDR
1529 LpDdr2MemType, ///< Assign 28 to LPDDR2
1530 LpDdr3MemType, ///< Assign 29 to LPDDR3
1531 LpDdr4MemType, ///< Assign 30 to LPDDR4
1532 GDdr6MemType, ///< Assign 31 to GDDR6
1533 HbmMemType, ///< Assign 32 to HBM
1534 Hbm2MemType, ///< Assign 33 to HBM2
1535 Ddr5MemType, ///< Assign 34 to DDR5
1536 LpDdr5MemType, ///< Assign 35 to LPDDR5
1537};
1538
1539
1540// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1541struct atom_fusion_system_info_v4
1542{
1543 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1544 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1545};
1546
1547
1548/*
1549 ***************************************************************************
1550 Data Table gfx_info structure
1551 ***************************************************************************
1552*/
1553
1554struct atom_gfx_info_v2_2
1555{
1556 struct atom_common_table_header table_header;
1557 uint8_t gfxip_min_ver;
1558 uint8_t gfxip_max_ver;
1559 uint8_t max_shader_engines;
1560 uint8_t max_tile_pipes;
1561 uint8_t max_cu_per_sh;
1562 uint8_t max_sh_per_se;
1563 uint8_t max_backends_per_se;
1564 uint8_t max_texture_channel_caches;
1565 uint32_t regaddr_cp_dma_src_addr;
1566 uint32_t regaddr_cp_dma_src_addr_hi;
1567 uint32_t regaddr_cp_dma_dst_addr;
1568 uint32_t regaddr_cp_dma_dst_addr_hi;
1569 uint32_t regaddr_cp_dma_command;
1570 uint32_t regaddr_cp_status;
1571 uint32_t regaddr_rlc_gpu_clock_32;
1572 uint32_t rlc_gpu_timer_refclk;
1573};
1574
1575struct atom_gfx_info_v2_3 {
1576 struct atom_common_table_header table_header;
1577 uint8_t gfxip_min_ver;
1578 uint8_t gfxip_max_ver;
1579 uint8_t max_shader_engines;
1580 uint8_t max_tile_pipes;
1581 uint8_t max_cu_per_sh;
1582 uint8_t max_sh_per_se;
1583 uint8_t max_backends_per_se;
1584 uint8_t max_texture_channel_caches;
1585 uint32_t regaddr_cp_dma_src_addr;
1586 uint32_t regaddr_cp_dma_src_addr_hi;
1587 uint32_t regaddr_cp_dma_dst_addr;
1588 uint32_t regaddr_cp_dma_dst_addr_hi;
1589 uint32_t regaddr_cp_dma_command;
1590 uint32_t regaddr_cp_status;
1591 uint32_t regaddr_rlc_gpu_clock_32;
1592 uint32_t rlc_gpu_timer_refclk;
1593 uint8_t active_cu_per_sh;
1594 uint8_t active_rb_per_se;
1595 uint16_t gcgoldenoffset;
1596 uint32_t rm21_sram_vmin_value;
1597};
1598
1599struct atom_gfx_info_v2_4
1600{
1601 struct atom_common_table_header table_header;
1602 uint8_t gfxip_min_ver;
1603 uint8_t gfxip_max_ver;
1604 uint8_t max_shader_engines;
1605 uint8_t reserved;
1606 uint8_t max_cu_per_sh;
1607 uint8_t max_sh_per_se;
1608 uint8_t max_backends_per_se;
1609 uint8_t max_texture_channel_caches;
1610 uint32_t regaddr_cp_dma_src_addr;
1611 uint32_t regaddr_cp_dma_src_addr_hi;
1612 uint32_t regaddr_cp_dma_dst_addr;
1613 uint32_t regaddr_cp_dma_dst_addr_hi;
1614 uint32_t regaddr_cp_dma_command;
1615 uint32_t regaddr_cp_status;
1616 uint32_t regaddr_rlc_gpu_clock_32;
1617 uint32_t rlc_gpu_timer_refclk;
1618 uint8_t active_cu_per_sh;
1619 uint8_t active_rb_per_se;
1620 uint16_t gcgoldenoffset;
1621 uint16_t gc_num_gprs;
1622 uint16_t gc_gsprim_buff_depth;
1623 uint16_t gc_parameter_cache_depth;
1624 uint16_t gc_wave_size;
1625 uint16_t gc_max_waves_per_simd;
1626 uint16_t gc_lds_size;
1627 uint8_t gc_num_max_gs_thds;
1628 uint8_t gc_gs_table_depth;
1629 uint8_t gc_double_offchip_lds_buffer;
1630 uint8_t gc_max_scratch_slots_per_cu;
1631 uint32_t sram_rm_fuses_val;
1632 uint32_t sram_custom_rm_fuses_val;
1633};
1634
1635struct atom_gfx_info_v2_7 {
1636 struct atom_common_table_header table_header;
1637 uint8_t gfxip_min_ver;
1638 uint8_t gfxip_max_ver;
1639 uint8_t max_shader_engines;
1640 uint8_t reserved;
1641 uint8_t max_cu_per_sh;
1642 uint8_t max_sh_per_se;
1643 uint8_t max_backends_per_se;
1644 uint8_t max_texture_channel_caches;
1645 uint32_t regaddr_cp_dma_src_addr;
1646 uint32_t regaddr_cp_dma_src_addr_hi;
1647 uint32_t regaddr_cp_dma_dst_addr;
1648 uint32_t regaddr_cp_dma_dst_addr_hi;
1649 uint32_t regaddr_cp_dma_command;
1650 uint32_t regaddr_cp_status;
1651 uint32_t regaddr_rlc_gpu_clock_32;
1652 uint32_t rlc_gpu_timer_refclk;
1653 uint8_t active_cu_per_sh;
1654 uint8_t active_rb_per_se;
1655 uint16_t gcgoldenoffset;
1656 uint16_t gc_num_gprs;
1657 uint16_t gc_gsprim_buff_depth;
1658 uint16_t gc_parameter_cache_depth;
1659 uint16_t gc_wave_size;
1660 uint16_t gc_max_waves_per_simd;
1661 uint16_t gc_lds_size;
1662 uint8_t gc_num_max_gs_thds;
1663 uint8_t gc_gs_table_depth;
1664 uint8_t gc_double_offchip_lds_buffer;
1665 uint8_t gc_max_scratch_slots_per_cu;
1666 uint32_t sram_rm_fuses_val;
1667 uint32_t sram_custom_rm_fuses_val;
1668 uint8_t cut_cu;
1669 uint8_t active_cu_total;
1670 uint8_t cu_reserved[2];
1671 uint32_t gc_config;
1672 uint8_t inactive_cu_per_se[8];
1673 uint32_t reserved2[6];
1674};
1675
1676/*
1677 ***************************************************************************
1678 Data Table smu_info structure
1679 ***************************************************************************
1680*/
1681struct atom_smu_info_v3_1
1682{
1683 struct atom_common_table_header table_header;
1684 uint8_t smuip_min_ver;
1685 uint8_t smuip_max_ver;
1686 uint8_t smu_rsd1;
1687 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1688 uint16_t sclk_ss_percentage;
1689 uint16_t sclk_ss_rate_10hz;
1690 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1691 uint16_t gpuclk_ss_rate_10hz;
1692 uint32_t core_refclk_10khz;
1693 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1694 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1695 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1696 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1697 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1698 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1699 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1700 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1701};
1702
1703struct atom_smu_info_v3_2 {
1704 struct atom_common_table_header table_header;
1705 uint8_t smuip_min_ver;
1706 uint8_t smuip_max_ver;
1707 uint8_t smu_rsd1;
1708 uint8_t gpuclk_ss_mode;
1709 uint16_t sclk_ss_percentage;
1710 uint16_t sclk_ss_rate_10hz;
1711 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1712 uint16_t gpuclk_ss_rate_10hz;
1713 uint32_t core_refclk_10khz;
1714 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1715 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1716 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1717 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1718 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1719 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1720 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1721 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1722 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1723 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1724 uint16_t smugoldenoffset;
1725 uint32_t gpupll_vco_freq_10khz;
1726 uint32_t bootup_smnclk_10khz;
1727 uint32_t bootup_socclk_10khz;
1728 uint32_t bootup_mp0clk_10khz;
1729 uint32_t bootup_mp1clk_10khz;
1730 uint32_t bootup_lclk_10khz;
1731 uint32_t bootup_dcefclk_10khz;
1732 uint32_t ctf_threshold_override_value;
1733 uint32_t reserved[5];
1734};
1735
1736struct atom_smu_info_v3_3 {
1737 struct atom_common_table_header table_header;
1738 uint8_t smuip_min_ver;
1739 uint8_t smuip_max_ver;
1740 uint8_t waflclk_ss_mode;
1741 uint8_t gpuclk_ss_mode;
1742 uint16_t sclk_ss_percentage;
1743 uint16_t sclk_ss_rate_10hz;
1744 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1745 uint16_t gpuclk_ss_rate_10hz;
1746 uint32_t core_refclk_10khz;
1747 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1748 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1749 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1750 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1751 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1752 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1753 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1754 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1755 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1756 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1757 uint16_t smugoldenoffset;
1758 uint32_t gpupll_vco_freq_10khz;
1759 uint32_t bootup_smnclk_10khz;
1760 uint32_t bootup_socclk_10khz;
1761 uint32_t bootup_mp0clk_10khz;
1762 uint32_t bootup_mp1clk_10khz;
1763 uint32_t bootup_lclk_10khz;
1764 uint32_t bootup_dcefclk_10khz;
1765 uint32_t ctf_threshold_override_value;
1766 uint32_t syspll3_0_vco_freq_10khz;
1767 uint32_t syspll3_1_vco_freq_10khz;
1768 uint32_t bootup_fclk_10khz;
1769 uint32_t bootup_waflclk_10khz;
1770 uint32_t smu_info_caps;
1771 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1772 uint16_t smuinitoffset;
1773 uint32_t reserved;
1774};
1775
1776/*
1777 ***************************************************************************
1778 Data Table smc_dpm_info structure
1779 ***************************************************************************
1780 */
1781struct atom_smc_dpm_info_v4_1
1782{
1783 struct atom_common_table_header table_header;
1784 uint8_t liquid1_i2c_address;
1785 uint8_t liquid2_i2c_address;
1786 uint8_t vr_i2c_address;
1787 uint8_t plx_i2c_address;
1788
1789 uint8_t liquid_i2c_linescl;
1790 uint8_t liquid_i2c_linesda;
1791 uint8_t vr_i2c_linescl;
1792 uint8_t vr_i2c_linesda;
1793
1794 uint8_t plx_i2c_linescl;
1795 uint8_t plx_i2c_linesda;
1796 uint8_t vrsensorpresent;
1797 uint8_t liquidsensorpresent;
1798
1799 uint16_t maxvoltagestepgfx;
1800 uint16_t maxvoltagestepsoc;
1801
1802 uint8_t vddgfxvrmapping;
1803 uint8_t vddsocvrmapping;
1804 uint8_t vddmem0vrmapping;
1805 uint8_t vddmem1vrmapping;
1806
1807 uint8_t gfxulvphasesheddingmask;
1808 uint8_t soculvphasesheddingmask;
1809 uint8_t padding8_v[2];
1810
1811 uint16_t gfxmaxcurrent;
1812 uint8_t gfxoffset;
1813 uint8_t padding_telemetrygfx;
1814
1815 uint16_t socmaxcurrent;
1816 uint8_t socoffset;
1817 uint8_t padding_telemetrysoc;
1818
1819 uint16_t mem0maxcurrent;
1820 uint8_t mem0offset;
1821 uint8_t padding_telemetrymem0;
1822
1823 uint16_t mem1maxcurrent;
1824 uint8_t mem1offset;
1825 uint8_t padding_telemetrymem1;
1826
1827 uint8_t acdcgpio;
1828 uint8_t acdcpolarity;
1829 uint8_t vr0hotgpio;
1830 uint8_t vr0hotpolarity;
1831
1832 uint8_t vr1hotgpio;
1833 uint8_t vr1hotpolarity;
1834 uint8_t padding1;
1835 uint8_t padding2;
1836
1837 uint8_t ledpin0;
1838 uint8_t ledpin1;
1839 uint8_t ledpin2;
1840 uint8_t padding8_4;
1841
1842 uint8_t pllgfxclkspreadenabled;
1843 uint8_t pllgfxclkspreadpercent;
1844 uint16_t pllgfxclkspreadfreq;
1845
1846 uint8_t uclkspreadenabled;
1847 uint8_t uclkspreadpercent;
1848 uint16_t uclkspreadfreq;
1849
1850 uint8_t socclkspreadenabled;
1851 uint8_t socclkspreadpercent;
1852 uint16_t socclkspreadfreq;
1853
1854 uint8_t acggfxclkspreadenabled;
1855 uint8_t acggfxclkspreadpercent;
1856 uint16_t acggfxclkspreadfreq;
1857
1858 uint8_t Vr2_I2C_address;
1859 uint8_t padding_vr2[3];
1860
1861 uint32_t boardreserved[9];
1862};
1863
1864/*
1865 ***************************************************************************
1866 Data Table smc_dpm_info structure
1867 ***************************************************************************
1868 */
1869struct atom_smc_dpm_info_v4_3
1870{
1871 struct atom_common_table_header table_header;
1872 uint8_t liquid1_i2c_address;
1873 uint8_t liquid2_i2c_address;
1874 uint8_t vr_i2c_address;
1875 uint8_t plx_i2c_address;
1876
1877 uint8_t liquid_i2c_linescl;
1878 uint8_t liquid_i2c_linesda;
1879 uint8_t vr_i2c_linescl;
1880 uint8_t vr_i2c_linesda;
1881
1882 uint8_t plx_i2c_linescl;
1883 uint8_t plx_i2c_linesda;
1884 uint8_t vrsensorpresent;
1885 uint8_t liquidsensorpresent;
1886
1887 uint16_t maxvoltagestepgfx;
1888 uint16_t maxvoltagestepsoc;
1889
1890 uint8_t vddgfxvrmapping;
1891 uint8_t vddsocvrmapping;
1892 uint8_t vddmem0vrmapping;
1893 uint8_t vddmem1vrmapping;
1894
1895 uint8_t gfxulvphasesheddingmask;
1896 uint8_t soculvphasesheddingmask;
1897 uint8_t externalsensorpresent;
1898 uint8_t padding8_v;
1899
1900 uint16_t gfxmaxcurrent;
1901 uint8_t gfxoffset;
1902 uint8_t padding_telemetrygfx;
1903
1904 uint16_t socmaxcurrent;
1905 uint8_t socoffset;
1906 uint8_t padding_telemetrysoc;
1907
1908 uint16_t mem0maxcurrent;
1909 uint8_t mem0offset;
1910 uint8_t padding_telemetrymem0;
1911
1912 uint16_t mem1maxcurrent;
1913 uint8_t mem1offset;
1914 uint8_t padding_telemetrymem1;
1915
1916 uint8_t acdcgpio;
1917 uint8_t acdcpolarity;
1918 uint8_t vr0hotgpio;
1919 uint8_t vr0hotpolarity;
1920
1921 uint8_t vr1hotgpio;
1922 uint8_t vr1hotpolarity;
1923 uint8_t padding1;
1924 uint8_t padding2;
1925
1926 uint8_t ledpin0;
1927 uint8_t ledpin1;
1928 uint8_t ledpin2;
1929 uint8_t padding8_4;
1930
1931 uint8_t pllgfxclkspreadenabled;
1932 uint8_t pllgfxclkspreadpercent;
1933 uint16_t pllgfxclkspreadfreq;
1934
1935 uint8_t uclkspreadenabled;
1936 uint8_t uclkspreadpercent;
1937 uint16_t uclkspreadfreq;
1938
1939 uint8_t fclkspreadenabled;
1940 uint8_t fclkspreadpercent;
1941 uint16_t fclkspreadfreq;
1942
1943 uint8_t fllgfxclkspreadenabled;
1944 uint8_t fllgfxclkspreadpercent;
1945 uint16_t fllgfxclkspreadfreq;
1946
1947 uint32_t boardreserved[10];
1948};
1949
1950struct smudpm_i2ccontrollerconfig_t {
1951 uint32_t enabled;
1952 uint32_t slaveaddress;
1953 uint32_t controllerport;
1954 uint32_t controllername;
1955 uint32_t thermalthrottler;
1956 uint32_t i2cprotocol;
1957 uint32_t i2cspeed;
1958};
1959
1960struct atom_smc_dpm_info_v4_4
1961{
1962 struct atom_common_table_header table_header;
1963 uint32_t i2c_padding[3];
1964
1965 uint16_t maxvoltagestepgfx;
1966 uint16_t maxvoltagestepsoc;
1967
1968 uint8_t vddgfxvrmapping;
1969 uint8_t vddsocvrmapping;
1970 uint8_t vddmem0vrmapping;
1971 uint8_t vddmem1vrmapping;
1972
1973 uint8_t gfxulvphasesheddingmask;
1974 uint8_t soculvphasesheddingmask;
1975 uint8_t externalsensorpresent;
1976 uint8_t padding8_v;
1977
1978 uint16_t gfxmaxcurrent;
1979 uint8_t gfxoffset;
1980 uint8_t padding_telemetrygfx;
1981
1982 uint16_t socmaxcurrent;
1983 uint8_t socoffset;
1984 uint8_t padding_telemetrysoc;
1985
1986 uint16_t mem0maxcurrent;
1987 uint8_t mem0offset;
1988 uint8_t padding_telemetrymem0;
1989
1990 uint16_t mem1maxcurrent;
1991 uint8_t mem1offset;
1992 uint8_t padding_telemetrymem1;
1993
1994
1995 uint8_t acdcgpio;
1996 uint8_t acdcpolarity;
1997 uint8_t vr0hotgpio;
1998 uint8_t vr0hotpolarity;
1999
2000 uint8_t vr1hotgpio;
2001 uint8_t vr1hotpolarity;
2002 uint8_t padding1;
2003 uint8_t padding2;
2004
2005
2006 uint8_t ledpin0;
2007 uint8_t ledpin1;
2008 uint8_t ledpin2;
2009 uint8_t padding8_4;
2010
2011
2012 uint8_t pllgfxclkspreadenabled;
2013 uint8_t pllgfxclkspreadpercent;
2014 uint16_t pllgfxclkspreadfreq;
2015
2016
2017 uint8_t uclkspreadenabled;
2018 uint8_t uclkspreadpercent;
2019 uint16_t uclkspreadfreq;
2020
2021
2022 uint8_t fclkspreadenabled;
2023 uint8_t fclkspreadpercent;
2024 uint16_t fclkspreadfreq;
2025
2026
2027 uint8_t fllgfxclkspreadenabled;
2028 uint8_t fllgfxclkspreadpercent;
2029 uint16_t fllgfxclkspreadfreq;
2030
2031
2032 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
2033
2034
2035 uint32_t boardreserved[10];
2036};
2037
2038enum smudpm_v4_5_i2ccontrollername_e{
2039 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2040 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
2041 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
2042 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
2043 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
2044 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
2045 SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
2046 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
2047 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
2048};
2049
2050enum smudpm_v4_5_i2ccontrollerthrottler_e{
2051 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2052 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
2053 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
2054 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
2055 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
2056 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
2057 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
2058 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
2059 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
2060};
2061
2062enum smudpm_v4_5_i2ccontrollerprotocol_e{
2063 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
2064 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
2065 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
2066 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
2067 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
2068 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
2069 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
2070};
2071
2072struct smudpm_i2c_controller_config_v2
2073{
2074 uint8_t Enabled;
2075 uint8_t Speed;
2076 uint8_t Padding[2];
2077 uint32_t SlaveAddress;
2078 uint8_t ControllerPort;
2079 uint8_t ControllerName;
2080 uint8_t ThermalThrotter;
2081 uint8_t I2cProtocol;
2082};
2083
2084struct atom_smc_dpm_info_v4_5
2085{
2086 struct atom_common_table_header table_header;
2087 // SECTION: BOARD PARAMETERS
2088 // I2C Control
2089 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
2090
2091 // SVI2 Board Parameters
2092 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2093 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2094
2095 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2096 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2097 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2098 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2099
2100 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2101 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2102 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2103 uint8_t Padding8_V;
2104
2105 // Telemetry Settings
2106 uint16_t GfxMaxCurrent; // in Amps
2107 uint8_t GfxOffset; // in Amps
2108 uint8_t Padding_TelemetryGfx;
2109 uint16_t SocMaxCurrent; // in Amps
2110 uint8_t SocOffset; // in Amps
2111 uint8_t Padding_TelemetrySoc;
2112
2113 uint16_t Mem0MaxCurrent; // in Amps
2114 uint8_t Mem0Offset; // in Amps
2115 uint8_t Padding_TelemetryMem0;
2116
2117 uint16_t Mem1MaxCurrent; // in Amps
2118 uint8_t Mem1Offset; // in Amps
2119 uint8_t Padding_TelemetryMem1;
2120
2121 // GPIO Settings
2122 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2123 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2124 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2125 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2126
2127 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2128 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2129 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2130 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2131
2132 // LED Display Settings
2133 uint8_t LedPin0; // GPIO number for LedPin[0]
2134 uint8_t LedPin1; // GPIO number for LedPin[1]
2135 uint8_t LedPin2; // GPIO number for LedPin[2]
2136 uint8_t padding8_4;
2137
2138 // GFXCLK PLL Spread Spectrum
2139 uint8_t PllGfxclkSpreadEnabled; // on or off
2140 uint8_t PllGfxclkSpreadPercent; // Q4.4
2141 uint16_t PllGfxclkSpreadFreq; // kHz
2142
2143 // GFXCLK DFLL Spread Spectrum
2144 uint8_t DfllGfxclkSpreadEnabled; // on or off
2145 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2146 uint16_t DfllGfxclkSpreadFreq; // kHz
2147
2148 // UCLK Spread Spectrum
2149 uint8_t UclkSpreadEnabled; // on or off
2150 uint8_t UclkSpreadPercent; // Q4.4
2151 uint16_t UclkSpreadFreq; // kHz
2152
2153 // SOCCLK Spread Spectrum
2154 uint8_t SoclkSpreadEnabled; // on or off
2155 uint8_t SocclkSpreadPercent; // Q4.4
2156 uint16_t SocclkSpreadFreq; // kHz
2157
2158 // Total board power
2159 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2160 uint16_t BoardPadding;
2161
2162 // Mvdd Svi2 Div Ratio Setting
2163 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2164
2165 uint32_t BoardReserved[9];
2166
2167};
2168
2169struct atom_smc_dpm_info_v4_6
2170{
2171 struct atom_common_table_header table_header;
2172 // section: board parameters
2173 uint32_t i2c_padding[3]; // old i2c control are moved to new area
2174
2175 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2176 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2177
2178 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2179 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2180 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2181 uint8_t boardvrmapping; // use vr_mapping* bitfields
2182
2183 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2184 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2185 uint8_t padding8_v[2];
2186
2187 // telemetry settings
2188 uint16_t gfxmaxcurrent; // in amps
2189 uint8_t gfxoffset; // in amps
2190 uint8_t padding_telemetrygfx;
2191
2192 uint16_t socmaxcurrent; // in amps
2193 uint8_t socoffset; // in amps
2194 uint8_t padding_telemetrysoc;
2195
2196 uint16_t memmaxcurrent; // in amps
2197 uint8_t memoffset; // in amps
2198 uint8_t padding_telemetrymem;
2199
2200 uint16_t boardmaxcurrent; // in amps
2201 uint8_t boardoffset; // in amps
2202 uint8_t padding_telemetryboardinput;
2203
2204 // gpio settings
2205 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2206 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2207 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2208 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2209
2210 // gfxclk pll spread spectrum
2211 uint8_t pllgfxclkspreadenabled; // on or off
2212 uint8_t pllgfxclkspreadpercent; // q4.4
2213 uint16_t pllgfxclkspreadfreq; // khz
2214
2215 // uclk spread spectrum
2216 uint8_t uclkspreadenabled; // on or off
2217 uint8_t uclkspreadpercent; // q4.4
2218 uint16_t uclkspreadfreq; // khz
2219
2220 // fclk spread spectrum
2221 uint8_t fclkspreadenabled; // on or off
2222 uint8_t fclkspreadpercent; // q4.4
2223 uint16_t fclkspreadfreq; // khz
2224
2225
2226 // gfxclk fll spread spectrum
2227 uint8_t fllgfxclkspreadenabled; // on or off
2228 uint8_t fllgfxclkspreadpercent; // q4.4
2229 uint16_t fllgfxclkspreadfreq; // khz
2230
2231 // i2c controller structure
2232 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2233
2234 // memory section
2235 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2236
2237 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2238 uint8_t paddingmem[3];
2239
2240 // total board power
2241 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power
2242 uint16_t boardpadding;
2243
2244 // section: xgmi training
2245 uint8_t xgmilinkspeed[4];
2246 uint8_t xgmilinkwidth[4];
2247
2248 uint16_t xgmifclkfreq[4];
2249 uint16_t xgmisocvoltage[4];
2250
2251 // reserved
2252 uint32_t boardreserved[10];
2253};
2254
2255struct atom_smc_dpm_info_v4_7
2256{
2257 struct atom_common_table_header table_header;
2258 // SECTION: BOARD PARAMETERS
2259 // I2C Control
2260 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
2261
2262 // SVI2 Board Parameters
2263 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2264 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2265
2266 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2267 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2268 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2269 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2270
2271 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2272 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2273 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2274 uint8_t Padding8_V;
2275
2276 // Telemetry Settings
2277 uint16_t GfxMaxCurrent; // in Amps
2278 uint8_t GfxOffset; // in Amps
2279 uint8_t Padding_TelemetryGfx;
2280 uint16_t SocMaxCurrent; // in Amps
2281 uint8_t SocOffset; // in Amps
2282 uint8_t Padding_TelemetrySoc;
2283
2284 uint16_t Mem0MaxCurrent; // in Amps
2285 uint8_t Mem0Offset; // in Amps
2286 uint8_t Padding_TelemetryMem0;
2287
2288 uint16_t Mem1MaxCurrent; // in Amps
2289 uint8_t Mem1Offset; // in Amps
2290 uint8_t Padding_TelemetryMem1;
2291
2292 // GPIO Settings
2293 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2294 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2295 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2296 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2297
2298 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2299 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2300 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2301 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2302
2303 // LED Display Settings
2304 uint8_t LedPin0; // GPIO number for LedPin[0]
2305 uint8_t LedPin1; // GPIO number for LedPin[1]
2306 uint8_t LedPin2; // GPIO number for LedPin[2]
2307 uint8_t padding8_4;
2308
2309 // GFXCLK PLL Spread Spectrum
2310 uint8_t PllGfxclkSpreadEnabled; // on or off
2311 uint8_t PllGfxclkSpreadPercent; // Q4.4
2312 uint16_t PllGfxclkSpreadFreq; // kHz
2313
2314 // GFXCLK DFLL Spread Spectrum
2315 uint8_t DfllGfxclkSpreadEnabled; // on or off
2316 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2317 uint16_t DfllGfxclkSpreadFreq; // kHz
2318
2319 // UCLK Spread Spectrum
2320 uint8_t UclkSpreadEnabled; // on or off
2321 uint8_t UclkSpreadPercent; // Q4.4
2322 uint16_t UclkSpreadFreq; // kHz
2323
2324 // SOCCLK Spread Spectrum
2325 uint8_t SoclkSpreadEnabled; // on or off
2326 uint8_t SocclkSpreadPercent; // Q4.4
2327 uint16_t SocclkSpreadFreq; // kHz
2328
2329 // Total board power
2330 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2331 uint16_t BoardPadding;
2332
2333 // Mvdd Svi2 Div Ratio Setting
2334 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2335
2336 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2337 uint8_t GpioI2cScl; // Serial Clock
2338 uint8_t GpioI2cSda; // Serial Data
2339 uint16_t GpioPadding;
2340
2341 // Additional LED Display Settings
2342 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2343 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2344 uint16_t LedEnableMask;
2345
2346 // Power Limit Scalars
2347 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2348
2349 uint8_t MvddUlvPhaseSheddingMask;
2350 uint8_t VddciUlvPhaseSheddingMask;
2351 uint8_t Padding8_Psi1;
2352 uint8_t Padding8_Psi2;
2353
2354 uint32_t BoardReserved[5];
2355};
2356
2357struct smudpm_i2c_controller_config_v3
2358{
2359 uint8_t Enabled;
2360 uint8_t Speed;
2361 uint8_t SlaveAddress;
2362 uint8_t ControllerPort;
2363 uint8_t ControllerName;
2364 uint8_t ThermalThrotter;
2365 uint8_t I2cProtocol;
2366 uint8_t PaddingConfig;
2367};
2368
2369struct atom_smc_dpm_info_v4_9
2370{
2371 struct atom_common_table_header table_header;
2372
2373 //SECTION: Gaming Clocks
2374 //uint32_t GamingClk[6];
2375
2376 // SECTION: I2C Control
2377 struct smudpm_i2c_controller_config_v3 I2cControllers[16];
2378
2379 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2380 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2381 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2382 uint8_t I2cSpare;
2383
2384 // SECTION: SVI2 Board Parameters
2385 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2386 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2387 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2388 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2389
2390 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2391 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2392 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2393 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2394
2395 // SECTION: Telemetry Settings
2396 uint16_t GfxMaxCurrent; // in Amps
2397 uint8_t GfxOffset; // in Amps
2398 uint8_t Padding_TelemetryGfx;
2399
2400 uint16_t SocMaxCurrent; // in Amps
2401 uint8_t SocOffset; // in Amps
2402 uint8_t Padding_TelemetrySoc;
2403
2404 uint16_t Mem0MaxCurrent; // in Amps
2405 uint8_t Mem0Offset; // in Amps
2406 uint8_t Padding_TelemetryMem0;
2407
2408 uint16_t Mem1MaxCurrent; // in Amps
2409 uint8_t Mem1Offset; // in Amps
2410 uint8_t Padding_TelemetryMem1;
2411
2412 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2413
2414 // SECTION: GPIO Settings
2415 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2416 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2417 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2418 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2419
2420 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2421 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2422 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2423 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2424
2425 // LED Display Settings
2426 uint8_t LedPin0; // GPIO number for LedPin[0]
2427 uint8_t LedPin1; // GPIO number for LedPin[1]
2428 uint8_t LedPin2; // GPIO number for LedPin[2]
2429 uint8_t LedEnableMask;
2430
2431 uint8_t LedPcie; // GPIO number for PCIE results
2432 uint8_t LedError; // GPIO number for Error Cases
2433 uint8_t LedSpare1[2];
2434
2435 // SECTION: Clock Spread Spectrum
2436
2437 // GFXCLK PLL Spread Spectrum
2438 uint8_t PllGfxclkSpreadEnabled; // on or off
2439 uint8_t PllGfxclkSpreadPercent; // Q4.4
2440 uint16_t PllGfxclkSpreadFreq; // kHz
2441
2442 // GFXCLK DFLL Spread Spectrum
2443 uint8_t DfllGfxclkSpreadEnabled; // on or off
2444 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2445 uint16_t DfllGfxclkSpreadFreq; // kHz
2446
2447 // UCLK Spread Spectrum
2448 uint8_t UclkSpreadEnabled; // on or off
2449 uint8_t UclkSpreadPercent; // Q4.4
2450 uint16_t UclkSpreadFreq; // kHz
2451
2452 // FCLK Spread Spectrum
2453 uint8_t FclkSpreadEnabled; // on or off
2454 uint8_t FclkSpreadPercent; // Q4.4
2455 uint16_t FclkSpreadFreq; // kHz
2456
2457 // Section: Memory Config
2458 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2459
2460 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2461 uint8_t PaddingMem1[3];
2462
2463 // Section: Total Board Power
2464 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2465 uint16_t BoardPowerPadding;
2466
2467 // SECTION: XGMI Training
2468 uint8_t XgmiLinkSpeed [4];
2469 uint8_t XgmiLinkWidth [4];
2470
2471 uint16_t XgmiFclkFreq [4];
2472 uint16_t XgmiSocVoltage [4];
2473
2474 // SECTION: Board Reserved
2475
2476 uint32_t BoardReserved[16];
2477
2478};
2479
2480struct atom_smc_dpm_info_v4_10
2481{
2482 struct atom_common_table_header table_header;
2483
2484 // SECTION: BOARD PARAMETERS
2485 // Telemetry Settings
2486 uint16_t GfxMaxCurrent; // in Amps
2487 uint8_t GfxOffset; // in Amps
2488 uint8_t Padding_TelemetryGfx;
2489
2490 uint16_t SocMaxCurrent; // in Amps
2491 uint8_t SocOffset; // in Amps
2492 uint8_t Padding_TelemetrySoc;
2493
2494 uint16_t MemMaxCurrent; // in Amps
2495 uint8_t MemOffset; // in Amps
2496 uint8_t Padding_TelemetryMem;
2497
2498 uint16_t BoardMaxCurrent; // in Amps
2499 uint8_t BoardOffset; // in Amps
2500 uint8_t Padding_TelemetryBoardInput;
2501
2502 // Platform input telemetry voltage coefficient
2503 uint32_t BoardVoltageCoeffA; // decode by /1000
2504 uint32_t BoardVoltageCoeffB; // decode by /1000
2505
2506 // GPIO Settings
2507 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2508 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2509 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2510 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2511
2512 // UCLK Spread Spectrum
2513 uint8_t UclkSpreadEnabled; // on or off
2514 uint8_t UclkSpreadPercent; // Q4.4
2515 uint16_t UclkSpreadFreq; // kHz
2516
2517 // FCLK Spread Spectrum
2518 uint8_t FclkSpreadEnabled; // on or off
2519 uint8_t FclkSpreadPercent; // Q4.4
2520 uint16_t FclkSpreadFreq; // kHz
2521
2522 // I2C Controller Structure
2523 struct smudpm_i2c_controller_config_v3 I2cControllers[8];
2524
2525 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2526 uint8_t GpioI2cScl; // Serial Clock
2527 uint8_t GpioI2cSda; // Serial Data
2528 uint16_t spare5;
2529
2530 uint32_t reserved[16];
2531};
2532
2533/*
2534 ***************************************************************************
2535 Data Table asic_profiling_info structure
2536 ***************************************************************************
2537*/
2538struct atom_asic_profiling_info_v4_1
2539{
2540 struct atom_common_table_header table_header;
2541 uint32_t maxvddc;
2542 uint32_t minvddc;
2543 uint32_t avfs_meannsigma_acontant0;
2544 uint32_t avfs_meannsigma_acontant1;
2545 uint32_t avfs_meannsigma_acontant2;
2546 uint16_t avfs_meannsigma_dc_tol_sigma;
2547 uint16_t avfs_meannsigma_platform_mean;
2548 uint16_t avfs_meannsigma_platform_sigma;
2549 uint32_t gb_vdroop_table_cksoff_a0;
2550 uint32_t gb_vdroop_table_cksoff_a1;
2551 uint32_t gb_vdroop_table_cksoff_a2;
2552 uint32_t gb_vdroop_table_ckson_a0;
2553 uint32_t gb_vdroop_table_ckson_a1;
2554 uint32_t gb_vdroop_table_ckson_a2;
2555 uint32_t avfsgb_fuse_table_cksoff_m1;
2556 uint32_t avfsgb_fuse_table_cksoff_m2;
2557 uint32_t avfsgb_fuse_table_cksoff_b;
2558 uint32_t avfsgb_fuse_table_ckson_m1;
2559 uint32_t avfsgb_fuse_table_ckson_m2;
2560 uint32_t avfsgb_fuse_table_ckson_b;
2561 uint16_t max_voltage_0_25mv;
2562 uint8_t enable_gb_vdroop_table_cksoff;
2563 uint8_t enable_gb_vdroop_table_ckson;
2564 uint8_t enable_gb_fuse_table_cksoff;
2565 uint8_t enable_gb_fuse_table_ckson;
2566 uint16_t psm_age_comfactor;
2567 uint8_t enable_apply_avfs_cksoff_voltage;
2568 uint8_t reserved;
2569 uint32_t dispclk2gfxclk_a;
2570 uint32_t dispclk2gfxclk_b;
2571 uint32_t dispclk2gfxclk_c;
2572 uint32_t pixclk2gfxclk_a;
2573 uint32_t pixclk2gfxclk_b;
2574 uint32_t pixclk2gfxclk_c;
2575 uint32_t dcefclk2gfxclk_a;
2576 uint32_t dcefclk2gfxclk_b;
2577 uint32_t dcefclk2gfxclk_c;
2578 uint32_t phyclk2gfxclk_a;
2579 uint32_t phyclk2gfxclk_b;
2580 uint32_t phyclk2gfxclk_c;
2581};
2582
2583struct atom_asic_profiling_info_v4_2 {
2584 struct atom_common_table_header table_header;
2585 uint32_t maxvddc;
2586 uint32_t minvddc;
2587 uint32_t avfs_meannsigma_acontant0;
2588 uint32_t avfs_meannsigma_acontant1;
2589 uint32_t avfs_meannsigma_acontant2;
2590 uint16_t avfs_meannsigma_dc_tol_sigma;
2591 uint16_t avfs_meannsigma_platform_mean;
2592 uint16_t avfs_meannsigma_platform_sigma;
2593 uint32_t gb_vdroop_table_cksoff_a0;
2594 uint32_t gb_vdroop_table_cksoff_a1;
2595 uint32_t gb_vdroop_table_cksoff_a2;
2596 uint32_t gb_vdroop_table_ckson_a0;
2597 uint32_t gb_vdroop_table_ckson_a1;
2598 uint32_t gb_vdroop_table_ckson_a2;
2599 uint32_t avfsgb_fuse_table_cksoff_m1;
2600 uint32_t avfsgb_fuse_table_cksoff_m2;
2601 uint32_t avfsgb_fuse_table_cksoff_b;
2602 uint32_t avfsgb_fuse_table_ckson_m1;
2603 uint32_t avfsgb_fuse_table_ckson_m2;
2604 uint32_t avfsgb_fuse_table_ckson_b;
2605 uint16_t max_voltage_0_25mv;
2606 uint8_t enable_gb_vdroop_table_cksoff;
2607 uint8_t enable_gb_vdroop_table_ckson;
2608 uint8_t enable_gb_fuse_table_cksoff;
2609 uint8_t enable_gb_fuse_table_ckson;
2610 uint16_t psm_age_comfactor;
2611 uint8_t enable_apply_avfs_cksoff_voltage;
2612 uint8_t reserved;
2613 uint32_t dispclk2gfxclk_a;
2614 uint32_t dispclk2gfxclk_b;
2615 uint32_t dispclk2gfxclk_c;
2616 uint32_t pixclk2gfxclk_a;
2617 uint32_t pixclk2gfxclk_b;
2618 uint32_t pixclk2gfxclk_c;
2619 uint32_t dcefclk2gfxclk_a;
2620 uint32_t dcefclk2gfxclk_b;
2621 uint32_t dcefclk2gfxclk_c;
2622 uint32_t phyclk2gfxclk_a;
2623 uint32_t phyclk2gfxclk_b;
2624 uint32_t phyclk2gfxclk_c;
2625 uint32_t acg_gb_vdroop_table_a0;
2626 uint32_t acg_gb_vdroop_table_a1;
2627 uint32_t acg_gb_vdroop_table_a2;
2628 uint32_t acg_avfsgb_fuse_table_m1;
2629 uint32_t acg_avfsgb_fuse_table_m2;
2630 uint32_t acg_avfsgb_fuse_table_b;
2631 uint8_t enable_acg_gb_vdroop_table;
2632 uint8_t enable_acg_gb_fuse_table;
2633 uint32_t acg_dispclk2gfxclk_a;
2634 uint32_t acg_dispclk2gfxclk_b;
2635 uint32_t acg_dispclk2gfxclk_c;
2636 uint32_t acg_pixclk2gfxclk_a;
2637 uint32_t acg_pixclk2gfxclk_b;
2638 uint32_t acg_pixclk2gfxclk_c;
2639 uint32_t acg_dcefclk2gfxclk_a;
2640 uint32_t acg_dcefclk2gfxclk_b;
2641 uint32_t acg_dcefclk2gfxclk_c;
2642 uint32_t acg_phyclk2gfxclk_a;
2643 uint32_t acg_phyclk2gfxclk_b;
2644 uint32_t acg_phyclk2gfxclk_c;
2645};
2646
2647/*
2648 ***************************************************************************
2649 Data Table multimedia_info structure
2650 ***************************************************************************
2651*/
2652struct atom_multimedia_info_v2_1
2653{
2654 struct atom_common_table_header table_header;
2655 uint8_t uvdip_min_ver;
2656 uint8_t uvdip_max_ver;
2657 uint8_t vceip_min_ver;
2658 uint8_t vceip_max_ver;
2659 uint16_t uvd_enc_max_input_width_pixels;
2660 uint16_t uvd_enc_max_input_height_pixels;
2661 uint16_t vce_enc_max_input_width_pixels;
2662 uint16_t vce_enc_max_input_height_pixels;
2663 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2664 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2665};
2666
2667
2668/*
2669 ***************************************************************************
2670 Data Table umc_info structure
2671 ***************************************************************************
2672*/
2673struct atom_umc_info_v3_1
2674{
2675 struct atom_common_table_header table_header;
2676 uint32_t ucode_version;
2677 uint32_t ucode_rom_startaddr;
2678 uint32_t ucode_length;
2679 uint16_t umc_reg_init_offset;
2680 uint16_t customer_ucode_name_offset;
2681 uint16_t mclk_ss_percentage;
2682 uint16_t mclk_ss_rate_10hz;
2683 uint8_t umcip_min_ver;
2684 uint8_t umcip_max_ver;
2685 uint8_t vram_type; //enum of atom_dgpu_vram_type
2686 uint8_t umc_config;
2687 uint32_t mem_refclk_10khz;
2688};
2689
2690// umc_info.umc_config
2691enum atom_umc_config_def {
2692 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
2693 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
2694 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
2695 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
2696 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
2697 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
2698};
2699
2700struct atom_umc_info_v3_2
2701{
2702 struct atom_common_table_header table_header;
2703 uint32_t ucode_version;
2704 uint32_t ucode_rom_startaddr;
2705 uint32_t ucode_length;
2706 uint16_t umc_reg_init_offset;
2707 uint16_t customer_ucode_name_offset;
2708 uint16_t mclk_ss_percentage;
2709 uint16_t mclk_ss_rate_10hz;
2710 uint8_t umcip_min_ver;
2711 uint8_t umcip_max_ver;
2712 uint8_t vram_type; //enum of atom_dgpu_vram_type
2713 uint8_t umc_config;
2714 uint32_t mem_refclk_10khz;
2715 uint32_t pstate_uclk_10khz[4];
2716 uint16_t umcgoldenoffset;
2717 uint16_t densitygoldenoffset;
2718};
2719
2720struct atom_umc_info_v3_3
2721{
2722 struct atom_common_table_header table_header;
2723 uint32_t ucode_reserved;
2724 uint32_t ucode_rom_startaddr;
2725 uint32_t ucode_length;
2726 uint16_t umc_reg_init_offset;
2727 uint16_t customer_ucode_name_offset;
2728 uint16_t mclk_ss_percentage;
2729 uint16_t mclk_ss_rate_10hz;
2730 uint8_t umcip_min_ver;
2731 uint8_t umcip_max_ver;
2732 uint8_t vram_type; //enum of atom_dgpu_vram_type
2733 uint8_t umc_config;
2734 uint32_t mem_refclk_10khz;
2735 uint32_t pstate_uclk_10khz[4];
2736 uint16_t umcgoldenoffset;
2737 uint16_t densitygoldenoffset;
2738 uint32_t umc_config1;
2739 uint32_t bist_data_startaddr;
2740 uint32_t reserved[2];
2741};
2742
2743enum atom_umc_config1_def {
2744 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
2745 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
2746 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
2747 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
2748 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
2749 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
2750};
2751
2752/*
2753 ***************************************************************************
2754 Data Table vram_info structure
2755 ***************************************************************************
2756*/
2757struct atom_vram_module_v9 {
2758 // Design Specific Values
2759 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2760 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2761 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2762 uint16_t reserved[3];
2763 uint16_t mem_voltage; // mem_voltage
2764 uint16_t vram_module_size; // Size of atom_vram_module_v9
2765 uint8_t ext_memory_id; // Current memory module ID
2766 uint8_t memory_type; // enum of atom_dgpu_vram_type
2767 uint8_t channel_num; // Number of mem. channels supported in this module
2768 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2769 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2770 uint8_t tunningset_id; // MC phy registers set per.
2771 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2772 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2773 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2774 uint8_t vram_rsd2; // reserved
2775 char dram_pnstring[20]; // part number end with '0'.
2776};
2777
2778struct atom_vram_info_header_v2_3 {
2779 struct atom_common_table_header table_header;
2780 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2781 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2782 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2783 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2784 uint16_t dram_data_remap_tbloffset; // reserved for now
2785 uint16_t tmrs_seq_offset; // offset of HBM tmrs
2786 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2787 uint16_t vram_rsd2;
2788 uint8_t vram_module_num; // indicate number of VRAM module
2789 uint8_t umcip_min_ver;
2790 uint8_t umcip_max_ver;
2791 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2792 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2793};
2794
2795struct atom_umc_register_addr_info{
2796 uint32_t umc_register_addr:24;
2797 uint32_t umc_reg_type_ind:1;
2798 uint32_t umc_reg_rsvd:7;
2799};
2800
2801//atom_umc_register_addr_info.
2802enum atom_umc_register_addr_info_flag{
2803 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
2804};
2805
2806union atom_umc_register_addr_info_access
2807{
2808 struct atom_umc_register_addr_info umc_reg_addr;
2809 uint32_t u32umc_reg_addr;
2810};
2811
2812struct atom_umc_reg_setting_id_config{
2813 uint32_t memclockrange:24;
2814 uint32_t mem_blk_id:8;
2815};
2816
2817union atom_umc_reg_setting_id_config_access
2818{
2819 struct atom_umc_reg_setting_id_config umc_id_access;
2820 uint32_t u32umc_id_access;
2821};
2822
2823struct atom_umc_reg_setting_data_block{
2824 union atom_umc_reg_setting_id_config_access block_id;
2825 uint32_t u32umc_reg_data[1];
2826};
2827
2828struct atom_umc_init_reg_block{
2829 uint16_t umc_reg_num;
2830 uint16_t reserved;
2831 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
2832 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
2833};
2834
2835struct atom_vram_module_v10 {
2836 // Design Specific Values
2837 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2838 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2839 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2840 uint16_t reserved[3];
2841 uint16_t mem_voltage; // mem_voltage
2842 uint16_t vram_module_size; // Size of atom_vram_module_v9
2843 uint8_t ext_memory_id; // Current memory module ID
2844 uint8_t memory_type; // enum of atom_dgpu_vram_type
2845 uint8_t channel_num; // Number of mem. channels supported in this module
2846 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2847 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2848 uint8_t tunningset_id; // MC phy registers set per
2849 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2850 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2851 uint8_t vram_flags; // bit0= bankgroup enable
2852 uint8_t vram_rsd2; // reserved
2853 uint16_t gddr6_mr10; // gddr6 mode register10 value
2854 uint16_t gddr6_mr1; // gddr6 mode register1 value
2855 uint16_t gddr6_mr2; // gddr6 mode register2 value
2856 uint16_t gddr6_mr7; // gddr6 mode register7 value
2857 char dram_pnstring[20]; // part number end with '0'
2858};
2859
2860struct atom_vram_info_header_v2_4 {
2861 struct atom_common_table_header table_header;
2862 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2863 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2864 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2865 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2866 uint16_t dram_data_remap_tbloffset; // reserved for now
2867 uint16_t reserved; // offset of reserved
2868 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2869 uint16_t vram_rsd2;
2870 uint8_t vram_module_num; // indicate number of VRAM module
2871 uint8_t umcip_min_ver;
2872 uint8_t umcip_max_ver;
2873 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2874 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2875};
2876
2877struct atom_vram_module_v11 {
2878 // Design Specific Values
2879 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2880 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2881 uint16_t mem_voltage; // mem_voltage
2882 uint16_t vram_module_size; // Size of atom_vram_module_v9
2883 uint8_t ext_memory_id; // Current memory module ID
2884 uint8_t memory_type; // enum of atom_dgpu_vram_type
2885 uint8_t channel_num; // Number of mem. channels supported in this module
2886 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2887 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2888 uint8_t tunningset_id; // MC phy registers set per.
2889 uint16_t reserved[4]; // reserved
2890 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2891 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2892 uint8_t vram_flags; // bit0= bankgroup enable
2893 uint8_t vram_rsd2; // reserved
2894 uint16_t gddr6_mr10; // gddr6 mode register10 value
2895 uint16_t gddr6_mr0; // gddr6 mode register0 value
2896 uint16_t gddr6_mr1; // gddr6 mode register1 value
2897 uint16_t gddr6_mr2; // gddr6 mode register2 value
2898 uint16_t gddr6_mr4; // gddr6 mode register4 value
2899 uint16_t gddr6_mr7; // gddr6 mode register7 value
2900 uint16_t gddr6_mr8; // gddr6 mode register8 value
2901 char dram_pnstring[40]; // part number end with '0'.
2902};
2903
2904struct atom_gddr6_ac_timing_v2_5 {
2905 uint32_t u32umc_id_access;
2906 uint8_t RL;
2907 uint8_t WL;
2908 uint8_t tRAS;
2909 uint8_t tRC;
2910
2911 uint16_t tREFI;
2912 uint8_t tRFC;
2913 uint8_t tRFCpb;
2914
2915 uint8_t tRREFD;
2916 uint8_t tRCDRD;
2917 uint8_t tRCDWR;
2918 uint8_t tRP;
2919
2920 uint8_t tRRDS;
2921 uint8_t tRRDL;
2922 uint8_t tWR;
2923 uint8_t tWTRS;
2924
2925 uint8_t tWTRL;
2926 uint8_t tFAW;
2927 uint8_t tCCDS;
2928 uint8_t tCCDL;
2929
2930 uint8_t tCRCRL;
2931 uint8_t tCRCWL;
2932 uint8_t tCKE;
2933 uint8_t tCKSRE;
2934
2935 uint8_t tCKSRX;
2936 uint8_t tRTPS;
2937 uint8_t tRTPL;
2938 uint8_t tMRD;
2939
2940 uint8_t tMOD;
2941 uint8_t tXS;
2942 uint8_t tXHP;
2943 uint8_t tXSMRS;
2944
2945 uint32_t tXSH;
2946
2947 uint8_t tPD;
2948 uint8_t tXP;
2949 uint8_t tCPDED;
2950 uint8_t tACTPDE;
2951
2952 uint8_t tPREPDE;
2953 uint8_t tREFPDE;
2954 uint8_t tMRSPDEN;
2955 uint8_t tRDSRE;
2956
2957 uint8_t tWRSRE;
2958 uint8_t tPPD;
2959 uint8_t tCCDMW;
2960 uint8_t tWTRTR;
2961
2962 uint8_t tLTLTR;
2963 uint8_t tREFTR;
2964 uint8_t VNDR;
2965 uint8_t reserved[9];
2966};
2967
2968struct atom_gddr6_bit_byte_remap {
2969 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap
2970 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0
2971 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1
2972 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2
2973 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0
2974 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1
2975 uint32_t phy_dram; //mmUMC_PHY_DRAM
2976};
2977
2978struct atom_gddr6_dram_data_remap {
2979 uint32_t table_size;
2980 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
2981 struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
2982};
2983
2984struct atom_vram_info_header_v2_5 {
2985 struct atom_common_table_header table_header;
2986 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
2987 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
2988 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2989 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2990 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
2991 uint16_t reserved; // offset of reserved
2992 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2993 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
2994 uint8_t vram_module_num; // indicate number of VRAM module
2995 uint8_t umcip_min_ver;
2996 uint8_t umcip_max_ver;
2997 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2998 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2999};
3000
3001struct atom_vram_info_header_v2_6 {
3002 struct atom_common_table_header table_header;
3003 uint16_t mem_adjust_tbloffset;
3004 uint16_t mem_clk_patch_tbloffset;
3005 uint16_t mc_adjust_pertile_tbloffset;
3006 uint16_t mc_phyinit_tbloffset;
3007 uint16_t dram_data_remap_tbloffset;
3008 uint16_t tmrs_seq_offset;
3009 uint16_t post_ucode_init_offset;
3010 uint16_t vram_rsd2;
3011 uint8_t vram_module_num;
3012 uint8_t umcip_min_ver;
3013 uint8_t umcip_max_ver;
3014 uint8_t mc_phy_tile_num;
3015 struct atom_vram_module_v9 vram_module[16];
3016};
3017/*
3018 ***************************************************************************
3019 Data Table voltageobject_info structure
3020 ***************************************************************************
3021*/
3022struct atom_i2c_data_entry
3023{
3024 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
3025 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
3026};
3027
3028struct atom_voltage_object_header_v4{
3029 uint8_t voltage_type; //enum atom_voltage_type
3030 uint8_t voltage_mode; //enum atom_voltage_object_mode
3031 uint16_t object_size; //Size of Object
3032};
3033
3034// atom_voltage_object_header_v4.voltage_mode
3035enum atom_voltage_object_mode
3036{
3037 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
3038 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
3039 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
3040 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
3041 VOLTAGE_OBJ_EVV = 8,
3042 VOLTAGE_OBJ_MERGED_POWER = 9,
3043};
3044
3045struct atom_i2c_voltage_object_v4
3046{
3047 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
3048 uint8_t regulator_id; //Indicate Voltage Regulator Id
3049 uint8_t i2c_id;
3050 uint8_t i2c_slave_addr;
3051 uint8_t i2c_control_offset;
3052 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3053 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
3054 uint8_t reserved[2];
3055 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
3056};
3057
3058// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
3059enum atom_i2c_voltage_control_flag
3060{
3061 VOLTAGE_DATA_ONE_BYTE = 0,
3062 VOLTAGE_DATA_TWO_BYTE = 1,
3063};
3064
3065
3066struct atom_voltage_gpio_map_lut
3067{
3068 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
3069 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
3070};
3071
3072struct atom_gpio_voltage_object_v4
3073{
3074 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
3075 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
3076 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
3077 uint8_t phase_delay_us; // phase delay in unit of micro second
3078 uint8_t reserved;
3079 uint32_t gpio_mask_val; // GPIO Mask value
3080 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
3081};
3082
3083struct atom_svid2_voltage_object_v4
3084{
3085 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
3086 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3087 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3088 uint8_t psi0_enable; //
3089 uint8_t maxvstep;
3090 uint8_t telemetry_offset;
3091 uint8_t telemetry_gain;
3092 uint16_t reserved1;
3093};
3094
3095struct atom_merged_voltage_object_v4
3096{
3097 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
3098 uint8_t merged_powerrail_type; //enum atom_voltage_type
3099 uint8_t reserved[3];
3100};
3101
3102union atom_voltage_object_v4{
3103 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
3104 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
3105 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
3106 struct atom_merged_voltage_object_v4 merged_voltage_obj;
3107};
3108
3109struct atom_voltage_objects_info_v4_1
3110{
3111 struct atom_common_table_header table_header;
3112 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
3113};
3114
3115
3116/*
3117 ***************************************************************************
3118 All Command Function structure definition
3119 ***************************************************************************
3120*/
3121
3122/*
3123 ***************************************************************************
3124 Structures used by asic_init
3125 ***************************************************************************
3126*/
3127
3128struct asic_init_engine_parameters
3129{
3130 uint32_t sclkfreqin10khz:24;
3131 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
3132};
3133
3134struct asic_init_mem_parameters
3135{
3136 uint32_t mclkfreqin10khz:24;
3137 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
3138};
3139
3140struct asic_init_parameters_v2_1
3141{
3142 struct asic_init_engine_parameters engineparam;
3143 struct asic_init_mem_parameters memparam;
3144};
3145
3146struct asic_init_ps_allocation_v2_1
3147{
3148 struct asic_init_parameters_v2_1 param;
3149 uint32_t reserved[16];
3150};
3151
3152
3153enum atom_asic_init_engine_flag
3154{
3155 b3NORMAL_ENGINE_INIT = 0,
3156 b3SRIOV_SKIP_ASIC_INIT = 0x02,
3157 b3SRIOV_LOAD_UCODE = 0x40,
3158};
3159
3160enum atom_asic_init_mem_flag
3161{
3162 b3NORMAL_MEM_INIT = 0,
3163 b3DRAM_SELF_REFRESH_EXIT =0x20,
3164};
3165
3166/*
3167 ***************************************************************************
3168 Structures used by setengineclock
3169 ***************************************************************************
3170*/
3171
3172struct set_engine_clock_parameters_v2_1
3173{
3174 uint32_t sclkfreqin10khz:24;
3175 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3176 uint32_t reserved[10];
3177};
3178
3179struct set_engine_clock_ps_allocation_v2_1
3180{
3181 struct set_engine_clock_parameters_v2_1 clockinfo;
3182 uint32_t reserved[10];
3183};
3184
3185
3186enum atom_set_engine_mem_clock_flag
3187{
3188 b3NORMAL_CHANGE_CLOCK = 0,
3189 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3190 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
3191};
3192
3193/*
3194 ***************************************************************************
3195 Structures used by getengineclock
3196 ***************************************************************************
3197*/
3198struct get_engine_clock_parameter
3199{
3200 uint32_t sclk_10khz; // current engine speed in 10KHz unit
3201 uint32_t reserved;
3202};
3203
3204/*
3205 ***************************************************************************
3206 Structures used by setmemoryclock
3207 ***************************************************************************
3208*/
3209struct set_memory_clock_parameters_v2_1
3210{
3211 uint32_t mclkfreqin10khz:24;
3212 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3213 uint32_t reserved[10];
3214};
3215
3216struct set_memory_clock_ps_allocation_v2_1
3217{
3218 struct set_memory_clock_parameters_v2_1 clockinfo;
3219 uint32_t reserved[10];
3220};
3221
3222
3223/*
3224 ***************************************************************************
3225 Structures used by getmemoryclock
3226 ***************************************************************************
3227*/
3228struct get_memory_clock_parameter
3229{
3230 uint32_t mclk_10khz; // current engine speed in 10KHz unit
3231 uint32_t reserved;
3232};
3233
3234
3235
3236/*
3237 ***************************************************************************
3238 Structures used by setvoltage
3239 ***************************************************************************
3240*/
3241
3242struct set_voltage_parameters_v1_4
3243{
3244 uint8_t voltagetype; /* enum atom_voltage_type */
3245 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3246 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
3247};
3248
3249//set_voltage_parameters_v2_1.voltagemode
3250enum atom_set_voltage_command{
3251 ATOM_SET_VOLTAGE = 0,
3252 ATOM_INIT_VOLTAGE_REGULATOR = 3,
3253 ATOM_SET_VOLTAGE_PHASE = 4,
3254 ATOM_GET_LEAKAGE_ID = 8,
3255};
3256
3257struct set_voltage_ps_allocation_v1_4
3258{
3259 struct set_voltage_parameters_v1_4 setvoltageparam;
3260 uint32_t reserved[10];
3261};
3262
3263
3264/*
3265 ***************************************************************************
3266 Structures used by computegpuclockparam
3267 ***************************************************************************
3268*/
3269
3270//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
3271enum atom_gpu_clock_type
3272{
3273 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3274 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3275 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3276};
3277
3278struct compute_gpu_clock_input_parameter_v1_8
3279{
3280 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3281 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
3282 uint32_t reserved[5];
3283};
3284
3285
3286struct compute_gpu_clock_output_parameter_v1_8
3287{
3288 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3289 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
3290 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3291 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3292 uint16_t pll_ss_slew_frac;
3293 uint8_t pll_ss_enable;
3294 uint8_t reserved;
3295 uint32_t reserved1[2];
3296};
3297
3298
3299
3300/*
3301 ***************************************************************************
3302 Structures used by ReadEfuseValue
3303 ***************************************************************************
3304*/
3305
3306struct read_efuse_input_parameters_v3_1
3307{
3308 uint16_t efuse_start_index;
3309 uint8_t reserved;
3310 uint8_t bitslen;
3311};
3312
3313// ReadEfuseValue input/output parameter
3314union read_efuse_value_parameters_v3_1
3315{
3316 struct read_efuse_input_parameters_v3_1 efuse_info;
3317 uint32_t efusevalue;
3318};
3319
3320
3321/*
3322 ***************************************************************************
3323 Structures used by getsmuclockinfo
3324 ***************************************************************************
3325*/
3326struct atom_get_smu_clock_info_parameters_v3_1
3327{
3328 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3329 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3330 uint8_t command; // enum of atom_get_smu_clock_info_command
3331 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3332};
3333
3334enum atom_get_smu_clock_info_command
3335{
3336 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
3337 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
3338 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
3339};
3340
3341enum atom_smu9_syspll0_clock_id
3342{
3343 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
3344 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
3345 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3346 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
3347 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
3348 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
3349 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
3350 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
3351 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
3352 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
3353 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
3354};
3355
3356enum atom_smu11_syspll_id {
3357 SMU11_SYSPLL0_ID = 0,
3358 SMU11_SYSPLL1_0_ID = 1,
3359 SMU11_SYSPLL1_1_ID = 2,
3360 SMU11_SYSPLL1_2_ID = 3,
3361 SMU11_SYSPLL2_ID = 4,
3362 SMU11_SYSPLL3_0_ID = 5,
3363 SMU11_SYSPLL3_1_ID = 6,
3364};
3365
3366enum atom_smu11_syspll0_clock_id {
3367 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
3368 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
3369 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3370 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
3371 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
3372 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
3373};
3374
3375enum atom_smu11_syspll1_0_clock_id {
3376 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
3377};
3378
3379enum atom_smu11_syspll1_1_clock_id {
3380 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
3381};
3382
3383enum atom_smu11_syspll1_2_clock_id {
3384 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
3385};
3386
3387enum atom_smu11_syspll2_clock_id {
3388 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
3389};
3390
3391enum atom_smu11_syspll3_0_clock_id {
3392 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
3393 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
3394 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
3395};
3396
3397enum atom_smu11_syspll3_1_clock_id {
3398 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
3399 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
3400 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
3401};
3402
3403enum atom_smu12_syspll_id {
3404 SMU12_SYSPLL0_ID = 0,
3405 SMU12_SYSPLL1_ID = 1,
3406 SMU12_SYSPLL2_ID = 2,
3407 SMU12_SYSPLL3_0_ID = 3,
3408 SMU12_SYSPLL3_1_ID = 4,
3409};
3410
3411enum atom_smu12_syspll0_clock_id {
3412 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK
3413 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
3414 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3415 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
3416 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK
3417 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK
3418 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK
3419 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK
3420 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK
3421 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK
3422 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK
3423};
3424
3425enum atom_smu12_syspll1_clock_id {
3426 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK
3427 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK
3428 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK
3429 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK
3430};
3431
3432enum atom_smu12_syspll2_clock_id {
3433 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK
3434};
3435
3436enum atom_smu12_syspll3_0_clock_id {
3437 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK
3438};
3439
3440enum atom_smu12_syspll3_1_clock_id {
3441 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK
3442};
3443
3444struct atom_get_smu_clock_info_output_parameters_v3_1
3445{
3446 union {
3447 uint32_t smu_clock_freq_hz;
3448 uint32_t syspllvcofreq_10khz;
3449 uint32_t sysspllrefclk_10khz;
3450 }atom_smu_outputclkfreq;
3451};
3452
3453
3454
3455/*
3456 ***************************************************************************
3457 Structures used by dynamicmemorysettings
3458 ***************************************************************************
3459*/
3460
3461enum atom_dynamic_memory_setting_command
3462{
3463 COMPUTE_MEMORY_PLL_PARAM = 1,
3464 COMPUTE_ENGINE_PLL_PARAM = 2,
3465 ADJUST_MC_SETTING_PARAM = 3,
3466};
3467
3468/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3469struct dynamic_mclk_settings_parameters_v2_1
3470{
3471 uint32_t mclk_10khz:24; //Input= target mclk
3472 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3473 uint32_t reserved;
3474};
3475
3476/* when command = COMPUTE_ENGINE_PLL_PARAM */
3477struct dynamic_sclk_settings_parameters_v2_1
3478{
3479 uint32_t sclk_10khz:24; //Input= target mclk
3480 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3481 uint32_t mclk_10khz;
3482 uint32_t reserved;
3483};
3484
3485union dynamic_memory_settings_parameters_v2_1
3486{
3487 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3488 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3489};
3490
3491
3492
3493/*
3494 ***************************************************************************
3495 Structures used by memorytraining
3496 ***************************************************************************
3497*/
3498
3499enum atom_umc6_0_ucode_function_call_enum_id
3500{
3501 UMC60_UCODE_FUNC_ID_REINIT = 0,
3502 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
3503 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
3504};
3505
3506
3507struct memory_training_parameters_v2_1
3508{
3509 uint8_t ucode_func_id;
3510 uint8_t ucode_reserved[3];
3511 uint32_t reserved[5];
3512};
3513
3514
3515/*
3516 ***************************************************************************
3517 Structures used by setpixelclock
3518 ***************************************************************************
3519*/
3520
3521struct set_pixel_clock_parameter_v1_7
3522{
3523 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
3524
3525 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3526 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
3527 // indicate which graphic encoder will be used.
3528 uint8_t encoder_mode; // Encoder mode:
3529 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
3530 uint8_t crtc_id; // enum of atom_crtc_def
3531 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3532 uint8_t reserved1[2];
3533 uint32_t reserved2;
3534};
3535
3536//ucMiscInfo
3537enum atom_set_pixel_clock_v1_7_misc_info
3538{
3539 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
3540 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
3541 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
3542 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
3543 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
3544 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
3545 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
3546 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
3547 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
3548 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
3549 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
3550};
3551
3552/* deep_color_ratio */
3553enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3554{
3555 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3556 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3557 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3558 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3559};
3560
3561/*
3562 ***************************************************************************
3563 Structures used by setdceclock
3564 ***************************************************************************
3565*/
3566
3567// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
3568struct set_dce_clock_parameters_v2_1
3569{
3570 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
3571 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
3572 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
3573 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
3574 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
3575};
3576
3577//ucDCEClkType
3578enum atom_set_dce_clock_clock_type
3579{
3580 DCE_CLOCK_TYPE_DISPCLK = 0,
3581 DCE_CLOCK_TYPE_DPREFCLK = 1,
3582 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
3583};
3584
3585//ucDCEClkFlag when ucDCEClkType == DPREFCLK
3586enum atom_set_dce_clock_dprefclk_flag
3587{
3588 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
3589 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
3590 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
3591 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
3592 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
3593};
3594
3595//ucDCEClkFlag when ucDCEClkType == PIXCLK
3596enum atom_set_dce_clock_pixclk_flag
3597{
3598 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
3599 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3600 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3601 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3602 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3603 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
3604};
3605
3606struct set_dce_clock_ps_allocation_v2_1
3607{
3608 struct set_dce_clock_parameters_v2_1 param;
3609 uint32_t ulReserved[2];
3610};
3611
3612
3613/****************************************************************************/
3614// Structures used by BlankCRTC
3615/****************************************************************************/
3616struct blank_crtc_parameters
3617{
3618 uint8_t crtc_id; // enum atom_crtc_def
3619 uint8_t blanking; // enum atom_blank_crtc_command
3620 uint16_t reserved;
3621 uint32_t reserved1;
3622};
3623
3624enum atom_blank_crtc_command
3625{
3626 ATOM_BLANKING = 1,
3627 ATOM_BLANKING_OFF = 0,
3628};
3629
3630/****************************************************************************/
3631// Structures used by enablecrtc
3632/****************************************************************************/
3633struct enable_crtc_parameters
3634{
3635 uint8_t crtc_id; // enum atom_crtc_def
3636 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3637 uint8_t padding[2];
3638};
3639
3640
3641/****************************************************************************/
3642// Structure used by EnableDispPowerGating
3643/****************************************************************************/
3644struct enable_disp_power_gating_parameters_v2_1
3645{
3646 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
3647 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3648 uint8_t padding[2];
3649};
3650
3651struct enable_disp_power_gating_ps_allocation
3652{
3653 struct enable_disp_power_gating_parameters_v2_1 param;
3654 uint32_t ulReserved[4];
3655};
3656
3657/****************************************************************************/
3658// Structure used in setcrtc_usingdtdtiming
3659/****************************************************************************/
3660struct set_crtc_using_dtd_timing_parameters
3661{
3662 uint16_t h_size;
3663 uint16_t h_blanking_time;
3664 uint16_t v_size;
3665 uint16_t v_blanking_time;
3666 uint16_t h_syncoffset;
3667 uint16_t h_syncwidth;
3668 uint16_t v_syncoffset;
3669 uint16_t v_syncwidth;
3670 uint16_t modemiscinfo;
3671 uint8_t h_border;
3672 uint8_t v_border;
3673 uint8_t crtc_id; // enum atom_crtc_def
3674 uint8_t encoder_mode; // atom_encode_mode_def
3675 uint8_t padding[2];
3676};
3677
3678
3679/****************************************************************************/
3680// Structures used by processi2cchanneltransaction
3681/****************************************************************************/
3682struct process_i2c_channel_transaction_parameters
3683{
3684 uint8_t i2cspeed_khz;
3685 union {
3686 uint8_t regindex;
3687 uint8_t status; /* enum atom_process_i2c_flag */
3688 } regind_status;
3689 uint16_t i2c_data_out;
3690 uint8_t flag; /* enum atom_process_i2c_status */
3691 uint8_t trans_bytes;
3692 uint8_t slave_addr;
3693 uint8_t i2c_id;
3694};
3695
3696//ucFlag
3697enum atom_process_i2c_flag
3698{
3699 HW_I2C_WRITE = 1,
3700 HW_I2C_READ = 0,
3701 I2C_2BYTE_ADDR = 0x02,
3702 HW_I2C_SMBUS_BYTE_WR = 0x04,
3703};
3704
3705//status
3706enum atom_process_i2c_status
3707{
3708 HW_ASSISTED_I2C_STATUS_FAILURE =2,
3709 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
3710};
3711
3712
3713/****************************************************************************/
3714// Structures used by processauxchanneltransaction
3715/****************************************************************************/
3716
3717struct process_aux_channel_transaction_parameters_v1_2
3718{
3719 uint16_t aux_request;
3720 uint16_t dataout;
3721 uint8_t channelid;
3722 union {
3723 uint8_t reply_status;
3724 uint8_t aux_delay;
3725 } aux_status_delay;
3726 uint8_t dataout_len;
3727 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
3728};
3729
3730
3731/****************************************************************************/
3732// Structures used by selectcrtc_source
3733/****************************************************************************/
3734
3735struct select_crtc_source_parameters_v2_3
3736{
3737 uint8_t crtc_id; // enum atom_crtc_def
3738 uint8_t encoder_id; // enum atom_dig_def
3739 uint8_t encode_mode; // enum atom_encode_mode_def
3740 uint8_t dst_bpc; // enum atom_panel_bit_per_color
3741};
3742
3743
3744/****************************************************************************/
3745// Structures used by digxencodercontrol
3746/****************************************************************************/
3747
3748// ucAction:
3749enum atom_dig_encoder_control_action
3750{
3751 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
3752 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
3753 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
3754 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
3755 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
3756 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
3757 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
3758 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
3759 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
3760 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
3761 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
3762 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
3763 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
3764 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
3765};
3766
3767//define ucPanelMode
3768enum atom_dig_encoder_control_panelmode
3769{
3770 DP_PANEL_MODE_DISABLE = 0x00,
3771 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
3772 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
3773};
3774
3775//ucDigId
3776enum atom_dig_encoder_control_v5_digid
3777{
3778 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
3779 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
3780 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
3781 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
3782 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
3783 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
3784 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
3785 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
3786};
3787
3788struct dig_encoder_stream_setup_parameters_v1_5
3789{
3790 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3791 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
3792 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3793 uint8_t lanenum; // Lane number
3794 uint32_t pclk_10khz; // Pixel Clock in 10Khz
3795 uint8_t bitpercolor;
3796 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
3797 uint8_t reserved[2];
3798};
3799
3800struct dig_encoder_link_setup_parameters_v1_5
3801{
3802 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3803 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
3804 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3805 uint8_t lanenum; // Lane number
3806 uint8_t symclk_10khz; // Symbol Clock in 10Khz
3807 uint8_t hpd_sel;
3808 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3809 uint8_t reserved[2];
3810};
3811
3812struct dp_panel_mode_set_parameters_v1_5
3813{
3814 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3815 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
3816 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
3817 uint8_t reserved1;
3818 uint32_t reserved2[2];
3819};
3820
3821struct dig_encoder_generic_cmd_parameters_v1_5
3822{
3823 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3824 uint8_t action; // = rest of generic encoder command which does not carry any parameters
3825 uint8_t reserved1[2];
3826 uint32_t reserved2[2];
3827};
3828
3829union dig_encoder_control_parameters_v1_5
3830{
3831 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
3832 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
3833 struct dig_encoder_link_setup_parameters_v1_5 link_param;
3834 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
3835};
3836
3837/*
3838 ***************************************************************************
3839 Structures used by dig1transmittercontrol
3840 ***************************************************************************
3841*/
3842struct dig_transmitter_control_parameters_v1_6
3843{
3844 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3845 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3846 union {
3847 uint8_t digmode; // enum atom_encode_mode_def
3848 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
3849 } mode_laneset;
3850 uint8_t lanenum; // Lane number 1, 2, 4, 8
3851 uint32_t symclk_10khz; // Symbol Clock in 10Khz
3852 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3853 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3854 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3855 uint8_t reserved;
3856 uint32_t reserved1;
3857};
3858
3859struct dig_transmitter_control_ps_allocation_v1_6
3860{
3861 struct dig_transmitter_control_parameters_v1_6 param;
3862 uint32_t reserved[4];
3863};
3864
3865//ucAction
3866enum atom_dig_transmitter_control_action
3867{
3868 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
3869 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
3870 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
3871 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
3872 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
3873 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
3874 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
3875 ATOM_TRANSMITTER_ACTION_INIT = 7,
3876 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
3877 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
3878 ATOM_TRANSMITTER_ACTION_SETUP = 10,
3879 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
3880 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
3881 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
3882};
3883
3884// digfe_sel
3885enum atom_dig_transmitter_control_digfe_sel
3886{
3887 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
3888 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
3889 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
3890 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
3891 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
3892 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
3893 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
3894};
3895
3896
3897//ucHPDSel
3898enum atom_dig_transmitter_control_hpd_sel
3899{
3900 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
3901 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
3902 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
3903 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
3904 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
3905 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
3906 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
3907};
3908
3909// ucDPLaneSet
3910enum atom_dig_transmitter_control_dplaneset
3911{
3912 DP_LANE_SET__0DB_0_4V = 0x00,
3913 DP_LANE_SET__0DB_0_6V = 0x01,
3914 DP_LANE_SET__0DB_0_8V = 0x02,
3915 DP_LANE_SET__0DB_1_2V = 0x03,
3916 DP_LANE_SET__3_5DB_0_4V = 0x08,
3917 DP_LANE_SET__3_5DB_0_6V = 0x09,
3918 DP_LANE_SET__3_5DB_0_8V = 0x0a,
3919 DP_LANE_SET__6DB_0_4V = 0x10,
3920 DP_LANE_SET__6DB_0_6V = 0x11,
3921 DP_LANE_SET__9_5DB_0_4V = 0x18,
3922};
3923
3924
3925
3926/****************************************************************************/
3927// Structures used by ExternalEncoderControl V2.4
3928/****************************************************************************/
3929
3930struct external_encoder_control_parameters_v2_4
3931{
3932 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
3933 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
3934 uint8_t action; //
3935 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3936 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3937 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
3938 uint8_t hpd_id;
3939};
3940
3941
3942// ucAction
3943enum external_encoder_control_action_def
3944{
3945 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
3946 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
3947 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
3948 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
3949 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
3950 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
3951 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
3952 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
3953};
3954
3955// ucConfig
3956enum external_encoder_control_v2_4_config_def
3957{
3958 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
3959 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
3960 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
3961 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
3962 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
3963 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
3964 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
3965 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
3966 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
3967};
3968
3969struct external_encoder_control_ps_allocation_v2_4
3970{
3971 struct external_encoder_control_parameters_v2_4 sExtEncoder;
3972 uint32_t reserved[2];
3973};
3974
3975
3976/*
3977 ***************************************************************************
3978 AMD ACPI Table
3979
3980 ***************************************************************************
3981*/
3982
3983struct amd_acpi_description_header{
3984 uint32_t signature;
3985 uint32_t tableLength; //Length
3986 uint8_t revision;
3987 uint8_t checksum;
3988 uint8_t oemId[6];
3989 uint8_t oemTableId[8]; //UINT64 OemTableId;
3990 uint32_t oemRevision;
3991 uint32_t creatorId;
3992 uint32_t creatorRevision;
3993};
3994
3995struct uefi_acpi_vfct{
3996 struct amd_acpi_description_header sheader;
3997 uint8_t tableUUID[16]; //0x24
3998 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
3999 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
4000 uint32_t reserved[4]; //0x3C
4001};
4002
4003struct vfct_image_header{
4004 uint32_t pcibus; //0x4C
4005 uint32_t pcidevice; //0x50
4006 uint32_t pcifunction; //0x54
4007 uint16_t vendorid; //0x58
4008 uint16_t deviceid; //0x5A
4009 uint16_t ssvid; //0x5C
4010 uint16_t ssid; //0x5E
4011 uint32_t revision; //0x60
4012 uint32_t imagelength; //0x64
4013};
4014
4015
4016struct gop_vbios_content {
4017 struct vfct_image_header vbiosheader;
4018 uint8_t vbioscontent[1];
4019};
4020
4021struct gop_lib1_content {
4022 struct vfct_image_header lib1header;
4023 uint8_t lib1content[1];
4024};
4025
4026
4027
4028/*
4029 ***************************************************************************
4030 Scratch Register definitions
4031 Each number below indicates which scratch regiser request, Active and
4032 Connect all share the same definitions as display_device_tag defines
4033 ***************************************************************************
4034*/
4035
4036enum scratch_register_def{
4037 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
4038 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
4039 ATOM_ACTIVE_INFO_DEF = 3,
4040 ATOM_LCD_INFO_DEF = 4,
4041 ATOM_DEVICE_REQ_INFO_DEF = 5,
4042 ATOM_ACC_CHANGE_INFO_DEF = 6,
4043 ATOM_PRE_OS_MODE_INFO_DEF = 7,
4044 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
4045 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
4046};
4047
4048enum scratch_device_connect_info_bit_def{
4049 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
4050 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
4051 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
4052 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
4053 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
4054 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
4055 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
4056 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
4057 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
4058};
4059
4060enum scratch_bl_bri_level_info_bit_def{
4061 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
4062#ifndef _H2INC
4063 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
4064 ATOM_DEVICE_DPMS_STATE =0x00010000,
4065#endif
4066};
4067
4068enum scratch_active_info_bits_def{
4069 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
4070 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
4071 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
4072 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
4073 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
4074 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
4075 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
4076 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
4077};
4078
4079enum scratch_device_req_info_bits_def{
4080 ATOM_DISPLAY_LCD1_REQ =0x0002,
4081 ATOM_DISPLAY_DFP1_REQ =0x0008,
4082 ATOM_DISPLAY_DFP2_REQ =0x0080,
4083 ATOM_DISPLAY_DFP3_REQ =0x0200,
4084 ATOM_DISPLAY_DFP4_REQ =0x0400,
4085 ATOM_DISPLAY_DFP5_REQ =0x0800,
4086 ATOM_DISPLAY_DFP6_REQ =0x0040,
4087 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
4088};
4089
4090enum scratch_acc_change_info_bitshift_def{
4091 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
4092 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
4093};
4094
4095enum scratch_acc_change_info_bits_def{
4096 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
4097 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
4098};
4099
4100enum scratch_pre_os_mode_info_bits_def{
4101 ATOM_PRE_OS_MODE_MASK =0x00000003,
4102 ATOM_PRE_OS_MODE_VGA =0x00000000,
4103 ATOM_PRE_OS_MODE_VESA =0x00000001,
4104 ATOM_PRE_OS_MODE_GOP =0x00000002,
4105 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
4106 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4107 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
4108 ATOM_ASIC_INIT_COMPLETE =0x00000200,
4109#ifndef _H2INC
4110 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
4111#endif
4112};
4113
4114
4115
4116/*
4117 ***************************************************************************
4118 ATOM firmware ID header file
4119 !! Please keep it at end of the atomfirmware.h !!
4120 ***************************************************************************
4121*/
4122#include "atomfirmwareid.h"
4123#pragma pack()
4124
4125#endif
4126