tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Pinctrl data for the NVIDIA Tegra20 pinmux
3 *
4 * Author: Stephen Warren <swarren@nvidia.com>
5 *
6 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Derived from code:
9 * Copyright (C) 2010 Google, Inc.
10 * Copyright (C) 2010 NVIDIA Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22#include <linux/clk-provider.h>
23#include <linux/init.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28
29#include "pinctrl-tegra.h"
30
31/*
32 * Most pins affected by the pinmux can also be GPIOs. Define these first.
33 * These must match how the GPIO driver names/numbers its pins.
34 */
35#define _GPIO(offset) (offset)
36
37#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
38#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
39#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
40#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
41#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
42#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
43#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
44#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
45#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
46#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
47#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
48#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
49#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
50#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
51#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
52#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
53#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
54#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
55#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
56#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
57#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
58#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
59#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
60#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
61#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
62#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
63#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
64#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
65#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
66#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
67#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
68#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
69#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
70#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
71#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
72#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
73#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
74#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
75#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
76#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
77#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
78#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
79#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
80#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
81#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
82#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
83#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
84#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
85#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
86#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
87#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
88#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
89#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
90#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
91#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
92#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
93#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
94#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
95#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
96#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
97#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
98#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
99#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
100#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
101#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
102#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
103#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
104#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
105#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
106#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
107#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
108#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
109#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
110#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
111#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
112#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
113#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
114#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
115#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
116#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
117#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
118#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
119#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
120#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
121#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
122#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
123#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
124#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
125#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
126#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
127#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
128#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
129#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
130#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
131#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
132#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
133#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
134#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
135#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
136#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
137#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
138#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
139#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
140#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
141#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
142#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
143#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
144#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
145#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
146#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
147#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
148#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
149#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
150#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
151#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
152#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
153#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
154#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
155#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
156#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
157#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
158#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
159#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
160#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
161#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
162#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
163#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
164#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
165#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
166#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
167#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
168#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
169#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
170#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
171#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
172#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
173#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
174#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
175#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
176#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
177#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
178#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
179#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
180#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
181#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
182#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
183#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
184#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
185#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
186#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
187#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
188#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
189#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
190#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
191#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
192#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
193#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
194#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
195#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
196#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
197#define TEGRA_PIN_PU0 _GPIO(160)
198#define TEGRA_PIN_PU1 _GPIO(161)
199#define TEGRA_PIN_PU2 _GPIO(162)
200#define TEGRA_PIN_PU3 _GPIO(163)
201#define TEGRA_PIN_PU4 _GPIO(164)
202#define TEGRA_PIN_PU5 _GPIO(165)
203#define TEGRA_PIN_PU6 _GPIO(166)
204#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
205#define TEGRA_PIN_PV0 _GPIO(168)
206#define TEGRA_PIN_PV1 _GPIO(169)
207#define TEGRA_PIN_PV2 _GPIO(170)
208#define TEGRA_PIN_PV3 _GPIO(171)
209#define TEGRA_PIN_PV4 _GPIO(172)
210#define TEGRA_PIN_PV5 _GPIO(173)
211#define TEGRA_PIN_PV6 _GPIO(174)
212#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
213#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
214#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
215#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
216#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
217#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
218#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
219#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
220#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
221#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
222#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
223#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
224#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
225#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
226#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
227#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
228#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
229#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
230#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
231#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
232#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
233#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
234#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
235#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
236#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
237#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
238#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
239#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
240#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
241#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
242#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
243#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
244#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
245#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
246#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
247#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
248#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
249#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
250#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
251#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
252#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
253#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
254#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
255#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
256#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
257#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
258#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
259#define TEGRA_PIN_PBB6 _GPIO(222)
260#define TEGRA_PIN_PBB7 _GPIO(223)
261
262/* All non-GPIO pins follow */
263#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
264#define _PIN(offset) (NUM_GPIOS + (offset))
265
266#define TEGRA_PIN_CRT_HSYNC _PIN(30)
267#define TEGRA_PIN_CRT_VSYNC _PIN(31)
268#define TEGRA_PIN_DDC_SCL _PIN(32)
269#define TEGRA_PIN_DDC_SDA _PIN(33)
270#define TEGRA_PIN_OWC _PIN(34)
271#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
272#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
273#define TEGRA_PIN_PWR_INT_N _PIN(37)
274#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
275#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
276#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
277#define TEGRA_PIN_DDR_A0 _PIN(41)
278#define TEGRA_PIN_DDR_A1 _PIN(42)
279#define TEGRA_PIN_DDR_A2 _PIN(43)
280#define TEGRA_PIN_DDR_A3 _PIN(44)
281#define TEGRA_PIN_DDR_A4 _PIN(45)
282#define TEGRA_PIN_DDR_A5 _PIN(46)
283#define TEGRA_PIN_DDR_A6 _PIN(47)
284#define TEGRA_PIN_DDR_A7 _PIN(48)
285#define TEGRA_PIN_DDR_A8 _PIN(49)
286#define TEGRA_PIN_DDR_A9 _PIN(50)
287#define TEGRA_PIN_DDR_A10 _PIN(51)
288#define TEGRA_PIN_DDR_A11 _PIN(52)
289#define TEGRA_PIN_DDR_A12 _PIN(53)
290#define TEGRA_PIN_DDR_A13 _PIN(54)
291#define TEGRA_PIN_DDR_A14 _PIN(55)
292#define TEGRA_PIN_DDR_CAS_N _PIN(56)
293#define TEGRA_PIN_DDR_BA0 _PIN(57)
294#define TEGRA_PIN_DDR_BA1 _PIN(58)
295#define TEGRA_PIN_DDR_BA2 _PIN(59)
296#define TEGRA_PIN_DDR_DQS0P _PIN(60)
297#define TEGRA_PIN_DDR_DQS0N _PIN(61)
298#define TEGRA_PIN_DDR_DQS1P _PIN(62)
299#define TEGRA_PIN_DDR_DQS1N _PIN(63)
300#define TEGRA_PIN_DDR_DQS2P _PIN(64)
301#define TEGRA_PIN_DDR_DQS2N _PIN(65)
302#define TEGRA_PIN_DDR_DQS3P _PIN(66)
303#define TEGRA_PIN_DDR_DQS3N _PIN(67)
304#define TEGRA_PIN_DDR_CKE0 _PIN(68)
305#define TEGRA_PIN_DDR_CKE1 _PIN(69)
306#define TEGRA_PIN_DDR_CLK _PIN(70)
307#define TEGRA_PIN_DDR_CLK_N _PIN(71)
308#define TEGRA_PIN_DDR_DM0 _PIN(72)
309#define TEGRA_PIN_DDR_DM1 _PIN(73)
310#define TEGRA_PIN_DDR_DM2 _PIN(74)
311#define TEGRA_PIN_DDR_DM3 _PIN(75)
312#define TEGRA_PIN_DDR_ODT _PIN(76)
313#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
314#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
315#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
316#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
317#define TEGRA_PIN_DDR_RAS_N _PIN(81)
318#define TEGRA_PIN_DDR_WE_N _PIN(82)
319#define TEGRA_PIN_DDR_DQ0 _PIN(83)
320#define TEGRA_PIN_DDR_DQ1 _PIN(84)
321#define TEGRA_PIN_DDR_DQ2 _PIN(85)
322#define TEGRA_PIN_DDR_DQ3 _PIN(86)
323#define TEGRA_PIN_DDR_DQ4 _PIN(87)
324#define TEGRA_PIN_DDR_DQ5 _PIN(88)
325#define TEGRA_PIN_DDR_DQ6 _PIN(89)
326#define TEGRA_PIN_DDR_DQ7 _PIN(90)
327#define TEGRA_PIN_DDR_DQ8 _PIN(91)
328#define TEGRA_PIN_DDR_DQ9 _PIN(92)
329#define TEGRA_PIN_DDR_DQ10 _PIN(93)
330#define TEGRA_PIN_DDR_DQ11 _PIN(94)
331#define TEGRA_PIN_DDR_DQ12 _PIN(95)
332#define TEGRA_PIN_DDR_DQ13 _PIN(96)
333#define TEGRA_PIN_DDR_DQ14 _PIN(97)
334#define TEGRA_PIN_DDR_DQ15 _PIN(98)
335#define TEGRA_PIN_DDR_DQ16 _PIN(99)
336#define TEGRA_PIN_DDR_DQ17 _PIN(100)
337#define TEGRA_PIN_DDR_DQ18 _PIN(101)
338#define TEGRA_PIN_DDR_DQ19 _PIN(102)
339#define TEGRA_PIN_DDR_DQ20 _PIN(103)
340#define TEGRA_PIN_DDR_DQ21 _PIN(104)
341#define TEGRA_PIN_DDR_DQ22 _PIN(105)
342#define TEGRA_PIN_DDR_DQ23 _PIN(106)
343#define TEGRA_PIN_DDR_DQ24 _PIN(107)
344#define TEGRA_PIN_DDR_DQ25 _PIN(108)
345#define TEGRA_PIN_DDR_DQ26 _PIN(109)
346#define TEGRA_PIN_DDR_DQ27 _PIN(110)
347#define TEGRA_PIN_DDR_DQ28 _PIN(111)
348#define TEGRA_PIN_DDR_DQ29 _PIN(112)
349#define TEGRA_PIN_DDR_DQ30 _PIN(113)
350#define TEGRA_PIN_DDR_DQ31 _PIN(114)
351#define TEGRA_PIN_DDR_CS0_N _PIN(115)
352#define TEGRA_PIN_DDR_CS1_N _PIN(116)
353#define TEGRA_PIN_SYS_RESET _PIN(117)
354#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
355#define TEGRA_PIN_JTAG_TDO _PIN(119)
356#define TEGRA_PIN_JTAG_TMS _PIN(120)
357#define TEGRA_PIN_JTAG_TCK _PIN(121)
358#define TEGRA_PIN_JTAG_TDI _PIN(122)
359#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
360
361static const struct pinctrl_pin_desc tegra20_pins[] = {
362 PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
363 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
364 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
365 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
366 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
367 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
368 PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
369 PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
370 PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
371 PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
372 PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
373 PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
374 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
375 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
376 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
377 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
378 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
379 PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
380 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
381 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
382 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
383 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
384 PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
385 PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
386 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
387 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
388 PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
389 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
390 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
391 PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
392 PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
393 PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
394 PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
395 PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
396 PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
397 PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
398 PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
399 PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
400 PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
401 PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
402 PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
403 PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
404 PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
405 PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
406 PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
407 PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
408 PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
409 PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
410 PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
411 PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
412 PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
413 PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
414 PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
415 PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
416 PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
417 PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
418 PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
419 PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
420 PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
421 PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
422 PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
423 PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
424 PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
425 PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
426 PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
427 PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
428 PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
429 PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
430 PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
431 PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
432 PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
433 PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
434 PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
435 PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
436 PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
437 PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
438 PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
439 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
440 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
441 PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
442 PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
443 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
444 PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
445 PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
446 PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
447 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
448 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
449 PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
450 PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
451 PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
452 PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
453 PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
454 PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
455 PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
456 PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
457 PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
458 PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
459 PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
460 PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
461 PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
462 PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
463 PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
464 PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
465 PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
466 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
467 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
468 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
469 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
470 PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
471 PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
472 PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
473 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
474 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
475 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
476 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
477 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
478 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
479 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
480 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
481 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
482 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
483 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
484 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
485 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
486 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
487 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
488 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
489 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
490 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
491 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
492 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
493 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
494 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
495 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
496 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
497 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
498 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
499 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
500 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
501 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
502 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
503 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
504 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
505 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
506 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
507 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
508 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
509 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
510 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
511 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
512 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
513 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
514 PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
515 PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
516 PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
517 PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
518 PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
519 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
520 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
521 PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
522 /* PU0..6: GPIO only */
523 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
524 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
525 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
526 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
527 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
528 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
529 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
530 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
531 /* PV0..1: GPIO only */
532 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
533 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
534 /* PV2..3: Balls are named after GPIO not function */
535 PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
536 PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
537 /* PV4..6: GPIO only */
538 PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
539 PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
540 PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
541 PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
542 PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
543 PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
544 PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
545 PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
546 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
547 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
548 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
549 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
550 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
551 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
552 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
553 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
554 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
555 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
556 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
557 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
558 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
559 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
560 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
561 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
562 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
563 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
564 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
565 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
566 PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
567 PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
568 PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
569 PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
570 PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
571 PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
572 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
573 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
574 PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
575 PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
576 PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
577 PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
578 PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
579 PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
580 PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
581 PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
582 PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
583 PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
584 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
585 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
586 PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
587 PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
588 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
589 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
590 PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
591 PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
592 PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
593 PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
594 PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
595 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
596 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
597 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
598 PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
599 PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
600 PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
601 PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
602 PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
603 PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
604 PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
605 PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
606 PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
607 PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
608 PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
609 PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
610 PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
611 PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
612 PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
613 PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
614 PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
615 PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
616 PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
617 PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
618 PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
619 PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
620 PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
621 PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
622 PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
623 PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
624 PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
625 PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
626 PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
627 PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
628 PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
629 PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
630 PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
631 PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
632 PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
633 PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
634 PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
635 PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
636 PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
637 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
638 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
639 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
640 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
641 PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
642 PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
643 PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
644 PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
645 PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
646 PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
647 PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
648 PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
649 PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
650 PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
651 PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
652 PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
653 PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
654 PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
655 PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
656 PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
657 PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
658 PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
659 PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
660 PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
661 PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
662 PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
663 PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
664 PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
665 PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
666 PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
667 PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
668 PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
669 PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
670 PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
671 PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
672 PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
673 PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
674 PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
675 PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
676 PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
677 PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
678 PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
679 PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
680 PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
681 PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
682 PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
683 PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
684};
685
686static const unsigned ata_pins[] = {
687 TEGRA_PIN_GMI_CS6_N_PI3,
688 TEGRA_PIN_GMI_CS7_N_PI6,
689 TEGRA_PIN_GMI_RST_N_PI4,
690};
691
692static const unsigned atb_pins[] = {
693 TEGRA_PIN_GMI_CS5_N_PI2,
694 TEGRA_PIN_GMI_DPD_PT7,
695};
696
697static const unsigned atc_pins[] = {
698 TEGRA_PIN_GMI_IORDY_PI5,
699 TEGRA_PIN_GMI_WAIT_PI7,
700 TEGRA_PIN_GMI_ADV_N_PK0,
701 TEGRA_PIN_GMI_CLK_PK1,
702 TEGRA_PIN_GMI_CS2_N_PK3,
703 TEGRA_PIN_GMI_CS3_N_PK4,
704 TEGRA_PIN_GMI_CS4_N_PK2,
705 TEGRA_PIN_GMI_AD0_PG0,
706 TEGRA_PIN_GMI_AD1_PG1,
707 TEGRA_PIN_GMI_AD2_PG2,
708 TEGRA_PIN_GMI_AD3_PG3,
709 TEGRA_PIN_GMI_AD4_PG4,
710 TEGRA_PIN_GMI_AD5_PG5,
711 TEGRA_PIN_GMI_AD6_PG6,
712 TEGRA_PIN_GMI_AD7_PG7,
713 TEGRA_PIN_GMI_HIOW_N_PI0,
714 TEGRA_PIN_GMI_HIOR_N_PI1,
715};
716
717static const unsigned atd_pins[] = {
718 TEGRA_PIN_GMI_AD8_PH0,
719 TEGRA_PIN_GMI_AD9_PH1,
720 TEGRA_PIN_GMI_AD10_PH2,
721 TEGRA_PIN_GMI_AD11_PH3,
722};
723
724static const unsigned ate_pins[] = {
725 TEGRA_PIN_GMI_AD12_PH4,
726 TEGRA_PIN_GMI_AD13_PH5,
727 TEGRA_PIN_GMI_AD14_PH6,
728 TEGRA_PIN_GMI_AD15_PH7,
729};
730
731static const unsigned cdev1_pins[] = {
732 TEGRA_PIN_DAP_MCLK1_PW4,
733};
734
735static const unsigned cdev2_pins[] = {
736 TEGRA_PIN_DAP_MCLK2_PW5,
737};
738
739static const unsigned crtp_pins[] = {
740 TEGRA_PIN_CRT_HSYNC,
741 TEGRA_PIN_CRT_VSYNC,
742};
743
744static const unsigned csus_pins[] = {
745 TEGRA_PIN_VI_MCLK_PT1,
746};
747
748static const unsigned dap1_pins[] = {
749 TEGRA_PIN_DAP1_FS_PN0,
750 TEGRA_PIN_DAP1_DIN_PN1,
751 TEGRA_PIN_DAP1_DOUT_PN2,
752 TEGRA_PIN_DAP1_SCLK_PN3,
753};
754
755static const unsigned dap2_pins[] = {
756 TEGRA_PIN_DAP2_FS_PA2,
757 TEGRA_PIN_DAP2_SCLK_PA3,
758 TEGRA_PIN_DAP2_DIN_PA4,
759 TEGRA_PIN_DAP2_DOUT_PA5,
760};
761
762static const unsigned dap3_pins[] = {
763 TEGRA_PIN_DAP3_FS_PP0,
764 TEGRA_PIN_DAP3_DIN_PP1,
765 TEGRA_PIN_DAP3_DOUT_PP2,
766 TEGRA_PIN_DAP3_SCLK_PP3,
767};
768
769static const unsigned dap4_pins[] = {
770 TEGRA_PIN_DAP4_FS_PP4,
771 TEGRA_PIN_DAP4_DIN_PP5,
772 TEGRA_PIN_DAP4_DOUT_PP6,
773 TEGRA_PIN_DAP4_SCLK_PP7,
774};
775
776static const unsigned ddc_pins[] = {
777 TEGRA_PIN_DDC_SCL,
778 TEGRA_PIN_DDC_SDA,
779};
780
781static const unsigned dta_pins[] = {
782 TEGRA_PIN_VI_D0_PT4,
783 TEGRA_PIN_VI_D1_PD5,
784};
785
786static const unsigned dtb_pins[] = {
787 TEGRA_PIN_VI_D10_PT2,
788 TEGRA_PIN_VI_D11_PT3,
789};
790
791static const unsigned dtc_pins[] = {
792 TEGRA_PIN_VI_HSYNC_PD7,
793 TEGRA_PIN_VI_VSYNC_PD6,
794};
795
796static const unsigned dtd_pins[] = {
797 TEGRA_PIN_VI_PCLK_PT0,
798 TEGRA_PIN_VI_D2_PL0,
799 TEGRA_PIN_VI_D3_PL1,
800 TEGRA_PIN_VI_D4_PL2,
801 TEGRA_PIN_VI_D5_PL3,
802 TEGRA_PIN_VI_D6_PL4,
803 TEGRA_PIN_VI_D7_PL5,
804 TEGRA_PIN_VI_D8_PL6,
805 TEGRA_PIN_VI_D9_PL7,
806};
807
808static const unsigned dte_pins[] = {
809 TEGRA_PIN_VI_GP0_PBB1,
810 TEGRA_PIN_VI_GP3_PBB4,
811 TEGRA_PIN_VI_GP4_PBB5,
812 TEGRA_PIN_VI_GP5_PD2,
813 TEGRA_PIN_VI_GP6_PA0,
814};
815
816static const unsigned dtf_pins[] = {
817 TEGRA_PIN_CAM_I2C_SCL_PBB2,
818 TEGRA_PIN_CAM_I2C_SDA_PBB3,
819};
820
821static const unsigned gma_pins[] = {
822 TEGRA_PIN_GMI_AD20_PAA0,
823 TEGRA_PIN_GMI_AD21_PAA1,
824 TEGRA_PIN_GMI_AD22_PAA2,
825 TEGRA_PIN_GMI_AD23_PAA3,
826};
827
828static const unsigned gmb_pins[] = {
829 TEGRA_PIN_GMI_WP_N_PC7,
830};
831
832static const unsigned gmc_pins[] = {
833 TEGRA_PIN_GMI_AD16_PJ7,
834 TEGRA_PIN_GMI_AD17_PB0,
835 TEGRA_PIN_GMI_AD18_PB1,
836 TEGRA_PIN_GMI_AD19_PK7,
837};
838
839static const unsigned gmd_pins[] = {
840 TEGRA_PIN_GMI_CS0_N_PJ0,
841 TEGRA_PIN_GMI_CS1_N_PJ2,
842};
843
844static const unsigned gme_pins[] = {
845 TEGRA_PIN_GMI_AD24_PAA4,
846 TEGRA_PIN_GMI_AD25_PAA5,
847 TEGRA_PIN_GMI_AD26_PAA6,
848 TEGRA_PIN_GMI_AD27_PAA7,
849};
850
851static const unsigned gpu_pins[] = {
852 TEGRA_PIN_PU0,
853 TEGRA_PIN_PU1,
854 TEGRA_PIN_PU2,
855 TEGRA_PIN_PU3,
856 TEGRA_PIN_PU4,
857 TEGRA_PIN_PU5,
858 TEGRA_PIN_PU6,
859};
860
861static const unsigned gpu7_pins[] = {
862 TEGRA_PIN_JTAG_RTCK_PU7,
863};
864
865static const unsigned gpv_pins[] = {
866 TEGRA_PIN_PV4,
867 TEGRA_PIN_PV5,
868 TEGRA_PIN_PV6,
869};
870
871static const unsigned hdint_pins[] = {
872 TEGRA_PIN_HDMI_INT_N_PN7,
873};
874
875static const unsigned i2cp_pins[] = {
876 TEGRA_PIN_PWR_I2C_SCL_PZ6,
877 TEGRA_PIN_PWR_I2C_SDA_PZ7,
878};
879
880static const unsigned irrx_pins[] = {
881 TEGRA_PIN_UART2_RTS_N_PJ6,
882};
883
884static const unsigned irtx_pins[] = {
885 TEGRA_PIN_UART2_CTS_N_PJ5,
886};
887
888static const unsigned kbca_pins[] = {
889 TEGRA_PIN_KB_ROW0_PR0,
890 TEGRA_PIN_KB_ROW1_PR1,
891 TEGRA_PIN_KB_ROW2_PR2,
892};
893
894static const unsigned kbcb_pins[] = {
895 TEGRA_PIN_KB_ROW7_PR7,
896 TEGRA_PIN_KB_ROW8_PS0,
897 TEGRA_PIN_KB_ROW9_PS1,
898 TEGRA_PIN_KB_ROW10_PS2,
899 TEGRA_PIN_KB_ROW11_PS3,
900 TEGRA_PIN_KB_ROW12_PS4,
901 TEGRA_PIN_KB_ROW13_PS5,
902 TEGRA_PIN_KB_ROW14_PS6,
903 TEGRA_PIN_KB_ROW15_PS7,
904};
905
906static const unsigned kbcc_pins[] = {
907 TEGRA_PIN_KB_COL0_PQ0,
908 TEGRA_PIN_KB_COL1_PQ1,
909};
910
911static const unsigned kbcd_pins[] = {
912 TEGRA_PIN_KB_ROW3_PR3,
913 TEGRA_PIN_KB_ROW4_PR4,
914 TEGRA_PIN_KB_ROW5_PR5,
915 TEGRA_PIN_KB_ROW6_PR6,
916};
917
918static const unsigned kbce_pins[] = {
919 TEGRA_PIN_KB_COL7_PQ7,
920};
921
922static const unsigned kbcf_pins[] = {
923 TEGRA_PIN_KB_COL2_PQ2,
924 TEGRA_PIN_KB_COL3_PQ3,
925 TEGRA_PIN_KB_COL4_PQ4,
926 TEGRA_PIN_KB_COL5_PQ5,
927 TEGRA_PIN_KB_COL6_PQ6,
928};
929
930static const unsigned lcsn_pins[] = {
931 TEGRA_PIN_LCD_CS0_N_PN4,
932};
933
934static const unsigned ld0_pins[] = {
935 TEGRA_PIN_LCD_D0_PE0,
936};
937
938static const unsigned ld1_pins[] = {
939 TEGRA_PIN_LCD_D1_PE1,
940};
941
942static const unsigned ld2_pins[] = {
943 TEGRA_PIN_LCD_D2_PE2,
944};
945
946static const unsigned ld3_pins[] = {
947 TEGRA_PIN_LCD_D3_PE3,
948};
949
950static const unsigned ld4_pins[] = {
951 TEGRA_PIN_LCD_D4_PE4,
952};
953
954static const unsigned ld5_pins[] = {
955 TEGRA_PIN_LCD_D5_PE5,
956};
957
958static const unsigned ld6_pins[] = {
959 TEGRA_PIN_LCD_D6_PE6,
960};
961
962static const unsigned ld7_pins[] = {
963 TEGRA_PIN_LCD_D7_PE7,
964};
965
966static const unsigned ld8_pins[] = {
967 TEGRA_PIN_LCD_D8_PF0,
968};
969
970static const unsigned ld9_pins[] = {
971 TEGRA_PIN_LCD_D9_PF1,
972};
973
974static const unsigned ld10_pins[] = {
975 TEGRA_PIN_LCD_D10_PF2,
976};
977
978static const unsigned ld11_pins[] = {
979 TEGRA_PIN_LCD_D11_PF3,
980};
981
982static const unsigned ld12_pins[] = {
983 TEGRA_PIN_LCD_D12_PF4,
984};
985
986static const unsigned ld13_pins[] = {
987 TEGRA_PIN_LCD_D13_PF5,
988};
989
990static const unsigned ld14_pins[] = {
991 TEGRA_PIN_LCD_D14_PF6,
992};
993
994static const unsigned ld15_pins[] = {
995 TEGRA_PIN_LCD_D15_PF7,
996};
997
998static const unsigned ld16_pins[] = {
999 TEGRA_PIN_LCD_D16_PM0,
1000};
1001
1002static const unsigned ld17_pins[] = {
1003 TEGRA_PIN_LCD_D17_PM1,
1004};
1005
1006static const unsigned ldc_pins[] = {
1007 TEGRA_PIN_LCD_DC0_PN6,
1008};
1009
1010static const unsigned ldi_pins[] = {
1011 TEGRA_PIN_LCD_D22_PM6,
1012};
1013
1014static const unsigned lhp0_pins[] = {
1015 TEGRA_PIN_LCD_D21_PM5,
1016};
1017
1018static const unsigned lhp1_pins[] = {
1019 TEGRA_PIN_LCD_D18_PM2,
1020};
1021
1022static const unsigned lhp2_pins[] = {
1023 TEGRA_PIN_LCD_D19_PM3,
1024};
1025
1026static const unsigned lhs_pins[] = {
1027 TEGRA_PIN_LCD_HSYNC_PJ3,
1028};
1029
1030static const unsigned lm0_pins[] = {
1031 TEGRA_PIN_LCD_CS1_N_PW0,
1032};
1033
1034static const unsigned lm1_pins[] = {
1035 TEGRA_PIN_LCD_M1_PW1,
1036};
1037
1038static const unsigned lpp_pins[] = {
1039 TEGRA_PIN_LCD_D23_PM7,
1040};
1041
1042static const unsigned lpw0_pins[] = {
1043 TEGRA_PIN_LCD_PWR0_PB2,
1044};
1045
1046static const unsigned lpw1_pins[] = {
1047 TEGRA_PIN_LCD_PWR1_PC1,
1048};
1049
1050static const unsigned lpw2_pins[] = {
1051 TEGRA_PIN_LCD_PWR2_PC6,
1052};
1053
1054static const unsigned lsc0_pins[] = {
1055 TEGRA_PIN_LCD_PCLK_PB3,
1056};
1057
1058static const unsigned lsc1_pins[] = {
1059 TEGRA_PIN_LCD_WR_N_PZ3,
1060};
1061
1062static const unsigned lsck_pins[] = {
1063 TEGRA_PIN_LCD_SCK_PZ4,
1064};
1065
1066static const unsigned lsda_pins[] = {
1067 TEGRA_PIN_LCD_SDOUT_PN5,
1068};
1069
1070static const unsigned lsdi_pins[] = {
1071 TEGRA_PIN_LCD_SDIN_PZ2,
1072};
1073
1074static const unsigned lspi_pins[] = {
1075 TEGRA_PIN_LCD_DE_PJ1,
1076};
1077
1078static const unsigned lvp0_pins[] = {
1079 TEGRA_PIN_LCD_DC1_PV7,
1080};
1081
1082static const unsigned lvp1_pins[] = {
1083 TEGRA_PIN_LCD_D20_PM4,
1084};
1085
1086static const unsigned lvs_pins[] = {
1087 TEGRA_PIN_LCD_VSYNC_PJ4,
1088};
1089
1090static const unsigned ls_pins[] = {
1091 TEGRA_PIN_LCD_PWR0_PB2,
1092 TEGRA_PIN_LCD_PWR1_PC1,
1093 TEGRA_PIN_LCD_PWR2_PC6,
1094 TEGRA_PIN_LCD_SDIN_PZ2,
1095 TEGRA_PIN_LCD_SDOUT_PN5,
1096 TEGRA_PIN_LCD_WR_N_PZ3,
1097 TEGRA_PIN_LCD_CS0_N_PN4,
1098 TEGRA_PIN_LCD_DC0_PN6,
1099 TEGRA_PIN_LCD_SCK_PZ4,
1100};
1101
1102static const unsigned lc_pins[] = {
1103 TEGRA_PIN_LCD_PCLK_PB3,
1104 TEGRA_PIN_LCD_DE_PJ1,
1105 TEGRA_PIN_LCD_HSYNC_PJ3,
1106 TEGRA_PIN_LCD_VSYNC_PJ4,
1107 TEGRA_PIN_LCD_CS1_N_PW0,
1108 TEGRA_PIN_LCD_M1_PW1,
1109 TEGRA_PIN_LCD_DC1_PV7,
1110 TEGRA_PIN_HDMI_INT_N_PN7,
1111};
1112
1113static const unsigned ld17_0_pins[] = {
1114 TEGRA_PIN_LCD_D0_PE0,
1115 TEGRA_PIN_LCD_D1_PE1,
1116 TEGRA_PIN_LCD_D2_PE2,
1117 TEGRA_PIN_LCD_D3_PE3,
1118 TEGRA_PIN_LCD_D4_PE4,
1119 TEGRA_PIN_LCD_D5_PE5,
1120 TEGRA_PIN_LCD_D6_PE6,
1121 TEGRA_PIN_LCD_D7_PE7,
1122 TEGRA_PIN_LCD_D8_PF0,
1123 TEGRA_PIN_LCD_D9_PF1,
1124 TEGRA_PIN_LCD_D10_PF2,
1125 TEGRA_PIN_LCD_D11_PF3,
1126 TEGRA_PIN_LCD_D12_PF4,
1127 TEGRA_PIN_LCD_D13_PF5,
1128 TEGRA_PIN_LCD_D14_PF6,
1129 TEGRA_PIN_LCD_D15_PF7,
1130 TEGRA_PIN_LCD_D16_PM0,
1131 TEGRA_PIN_LCD_D17_PM1,
1132};
1133
1134static const unsigned ld19_18_pins[] = {
1135 TEGRA_PIN_LCD_D18_PM2,
1136 TEGRA_PIN_LCD_D19_PM3,
1137};
1138
1139static const unsigned ld21_20_pins[] = {
1140 TEGRA_PIN_LCD_D20_PM4,
1141 TEGRA_PIN_LCD_D21_PM5,
1142};
1143
1144static const unsigned ld23_22_pins[] = {
1145 TEGRA_PIN_LCD_D22_PM6,
1146 TEGRA_PIN_LCD_D23_PM7,
1147};
1148
1149static const unsigned owc_pins[] = {
1150 TEGRA_PIN_OWC,
1151};
1152
1153static const unsigned pmc_pins[] = {
1154 TEGRA_PIN_LED_BLINK_PBB0,
1155 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1156 TEGRA_PIN_CORE_PWR_REQ,
1157 TEGRA_PIN_CPU_PWR_REQ,
1158 TEGRA_PIN_PWR_INT_N,
1159};
1160
1161static const unsigned pta_pins[] = {
1162 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1163 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1164};
1165
1166static const unsigned rm_pins[] = {
1167 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1168 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1169};
1170
1171static const unsigned sdb_pins[] = {
1172 TEGRA_PIN_SDIO3_CMD_PA7,
1173};
1174
1175static const unsigned sdc_pins[] = {
1176 TEGRA_PIN_SDIO3_DAT0_PB7,
1177 TEGRA_PIN_SDIO3_DAT1_PB6,
1178 TEGRA_PIN_SDIO3_DAT2_PB5,
1179 TEGRA_PIN_SDIO3_DAT3_PB4,
1180};
1181
1182static const unsigned sdd_pins[] = {
1183 TEGRA_PIN_SDIO3_CLK_PA6,
1184};
1185
1186static const unsigned sdio1_pins[] = {
1187 TEGRA_PIN_SDIO1_CLK_PZ0,
1188 TEGRA_PIN_SDIO1_CMD_PZ1,
1189 TEGRA_PIN_SDIO1_DAT0_PY7,
1190 TEGRA_PIN_SDIO1_DAT1_PY6,
1191 TEGRA_PIN_SDIO1_DAT2_PY5,
1192 TEGRA_PIN_SDIO1_DAT3_PY4,
1193};
1194
1195static const unsigned slxa_pins[] = {
1196 TEGRA_PIN_SDIO3_DAT4_PD1,
1197};
1198
1199static const unsigned slxc_pins[] = {
1200 TEGRA_PIN_SDIO3_DAT6_PD3,
1201};
1202
1203static const unsigned slxd_pins[] = {
1204 TEGRA_PIN_SDIO3_DAT7_PD4,
1205};
1206
1207static const unsigned slxk_pins[] = {
1208 TEGRA_PIN_SDIO3_DAT5_PD0,
1209};
1210
1211static const unsigned spdi_pins[] = {
1212 TEGRA_PIN_SPDIF_IN_PK6,
1213};
1214
1215static const unsigned spdo_pins[] = {
1216 TEGRA_PIN_SPDIF_OUT_PK5,
1217};
1218
1219static const unsigned spia_pins[] = {
1220 TEGRA_PIN_SPI2_MOSI_PX0,
1221};
1222
1223static const unsigned spib_pins[] = {
1224 TEGRA_PIN_SPI2_MISO_PX1,
1225};
1226
1227static const unsigned spic_pins[] = {
1228 TEGRA_PIN_SPI2_CS0_N_PX3,
1229 TEGRA_PIN_SPI2_SCK_PX2,
1230};
1231
1232static const unsigned spid_pins[] = {
1233 TEGRA_PIN_SPI1_MOSI_PX4,
1234};
1235
1236static const unsigned spie_pins[] = {
1237 TEGRA_PIN_SPI1_CS0_N_PX6,
1238 TEGRA_PIN_SPI1_SCK_PX5,
1239};
1240
1241static const unsigned spif_pins[] = {
1242 TEGRA_PIN_SPI1_MISO_PX7,
1243};
1244
1245static const unsigned spig_pins[] = {
1246 TEGRA_PIN_SPI2_CS1_N_PW2,
1247};
1248
1249static const unsigned spih_pins[] = {
1250 TEGRA_PIN_SPI2_CS2_N_PW3,
1251};
1252
1253static const unsigned uaa_pins[] = {
1254 TEGRA_PIN_ULPI_DATA0_PO1,
1255 TEGRA_PIN_ULPI_DATA1_PO2,
1256 TEGRA_PIN_ULPI_DATA2_PO3,
1257 TEGRA_PIN_ULPI_DATA3_PO4,
1258};
1259
1260static const unsigned uab_pins[] = {
1261 TEGRA_PIN_ULPI_DATA4_PO5,
1262 TEGRA_PIN_ULPI_DATA5_PO6,
1263 TEGRA_PIN_ULPI_DATA6_PO7,
1264 TEGRA_PIN_ULPI_DATA7_PO0,
1265};
1266
1267static const unsigned uac_pins[] = {
1268 TEGRA_PIN_PV0,
1269 TEGRA_PIN_PV1,
1270 TEGRA_PIN_PV2,
1271 TEGRA_PIN_PV3,
1272};
1273
1274static const unsigned ck32_pins[] = {
1275 TEGRA_PIN_CLK_32_K_IN,
1276};
1277
1278static const unsigned uad_pins[] = {
1279 TEGRA_PIN_UART2_RXD_PC3,
1280 TEGRA_PIN_UART2_TXD_PC2,
1281};
1282
1283static const unsigned uca_pins[] = {
1284 TEGRA_PIN_UART3_RXD_PW7,
1285 TEGRA_PIN_UART3_TXD_PW6,
1286};
1287
1288static const unsigned ucb_pins[] = {
1289 TEGRA_PIN_UART3_CTS_N_PA1,
1290 TEGRA_PIN_UART3_RTS_N_PC0,
1291};
1292
1293static const unsigned uda_pins[] = {
1294 TEGRA_PIN_ULPI_CLK_PY0,
1295 TEGRA_PIN_ULPI_DIR_PY1,
1296 TEGRA_PIN_ULPI_NXT_PY2,
1297 TEGRA_PIN_ULPI_STP_PY3,
1298};
1299
1300static const unsigned ddrc_pins[] = {
1301 TEGRA_PIN_DDR_COMP_PD,
1302 TEGRA_PIN_DDR_COMP_PU,
1303};
1304
1305static const unsigned pmca_pins[] = {
1306 TEGRA_PIN_LED_BLINK_PBB0,
1307};
1308
1309static const unsigned pmcb_pins[] = {
1310 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1311};
1312
1313static const unsigned pmcc_pins[] = {
1314 TEGRA_PIN_CORE_PWR_REQ,
1315};
1316
1317static const unsigned pmcd_pins[] = {
1318 TEGRA_PIN_CPU_PWR_REQ,
1319};
1320
1321static const unsigned pmce_pins[] = {
1322 TEGRA_PIN_PWR_INT_N,
1323};
1324
1325static const unsigned xm2c_pins[] = {
1326 TEGRA_PIN_DDR_A0,
1327 TEGRA_PIN_DDR_A1,
1328 TEGRA_PIN_DDR_A2,
1329 TEGRA_PIN_DDR_A3,
1330 TEGRA_PIN_DDR_A4,
1331 TEGRA_PIN_DDR_A5,
1332 TEGRA_PIN_DDR_A6,
1333 TEGRA_PIN_DDR_A7,
1334 TEGRA_PIN_DDR_A8,
1335 TEGRA_PIN_DDR_A9,
1336 TEGRA_PIN_DDR_A10,
1337 TEGRA_PIN_DDR_A11,
1338 TEGRA_PIN_DDR_A12,
1339 TEGRA_PIN_DDR_A13,
1340 TEGRA_PIN_DDR_A14,
1341 TEGRA_PIN_DDR_CAS_N,
1342 TEGRA_PIN_DDR_BA0,
1343 TEGRA_PIN_DDR_BA1,
1344 TEGRA_PIN_DDR_BA2,
1345 TEGRA_PIN_DDR_DQS0P,
1346 TEGRA_PIN_DDR_DQS0N,
1347 TEGRA_PIN_DDR_DQS1P,
1348 TEGRA_PIN_DDR_DQS1N,
1349 TEGRA_PIN_DDR_DQS2P,
1350 TEGRA_PIN_DDR_DQS2N,
1351 TEGRA_PIN_DDR_DQS3P,
1352 TEGRA_PIN_DDR_DQS3N,
1353 TEGRA_PIN_DDR_CS0_N,
1354 TEGRA_PIN_DDR_CS1_N,
1355 TEGRA_PIN_DDR_CKE0,
1356 TEGRA_PIN_DDR_CKE1,
1357 TEGRA_PIN_DDR_CLK,
1358 TEGRA_PIN_DDR_CLK_N,
1359 TEGRA_PIN_DDR_DM0,
1360 TEGRA_PIN_DDR_DM1,
1361 TEGRA_PIN_DDR_DM2,
1362 TEGRA_PIN_DDR_DM3,
1363 TEGRA_PIN_DDR_ODT,
1364 TEGRA_PIN_DDR_RAS_N,
1365 TEGRA_PIN_DDR_WE_N,
1366 TEGRA_PIN_DDR_QUSE0,
1367 TEGRA_PIN_DDR_QUSE1,
1368 TEGRA_PIN_DDR_QUSE2,
1369 TEGRA_PIN_DDR_QUSE3,
1370};
1371
1372static const unsigned xm2d_pins[] = {
1373 TEGRA_PIN_DDR_DQ0,
1374 TEGRA_PIN_DDR_DQ1,
1375 TEGRA_PIN_DDR_DQ2,
1376 TEGRA_PIN_DDR_DQ3,
1377 TEGRA_PIN_DDR_DQ4,
1378 TEGRA_PIN_DDR_DQ5,
1379 TEGRA_PIN_DDR_DQ6,
1380 TEGRA_PIN_DDR_DQ7,
1381 TEGRA_PIN_DDR_DQ8,
1382 TEGRA_PIN_DDR_DQ9,
1383 TEGRA_PIN_DDR_DQ10,
1384 TEGRA_PIN_DDR_DQ11,
1385 TEGRA_PIN_DDR_DQ12,
1386 TEGRA_PIN_DDR_DQ13,
1387 TEGRA_PIN_DDR_DQ14,
1388 TEGRA_PIN_DDR_DQ15,
1389 TEGRA_PIN_DDR_DQ16,
1390 TEGRA_PIN_DDR_DQ17,
1391 TEGRA_PIN_DDR_DQ18,
1392 TEGRA_PIN_DDR_DQ19,
1393 TEGRA_PIN_DDR_DQ20,
1394 TEGRA_PIN_DDR_DQ21,
1395 TEGRA_PIN_DDR_DQ22,
1396 TEGRA_PIN_DDR_DQ23,
1397 TEGRA_PIN_DDR_DQ24,
1398 TEGRA_PIN_DDR_DQ25,
1399 TEGRA_PIN_DDR_DQ26,
1400 TEGRA_PIN_DDR_DQ27,
1401 TEGRA_PIN_DDR_DQ28,
1402 TEGRA_PIN_DDR_DQ29,
1403 TEGRA_PIN_DDR_DQ30,
1404 TEGRA_PIN_DDR_DQ31,
1405};
1406
1407static const unsigned drive_ao1_pins[] = {
1408 TEGRA_PIN_SYS_RESET,
1409 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1410 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1411 TEGRA_PIN_KB_ROW0_PR0,
1412 TEGRA_PIN_KB_ROW1_PR1,
1413 TEGRA_PIN_KB_ROW2_PR2,
1414 TEGRA_PIN_KB_ROW3_PR3,
1415 TEGRA_PIN_KB_ROW4_PR4,
1416 TEGRA_PIN_KB_ROW5_PR5,
1417 TEGRA_PIN_KB_ROW6_PR6,
1418 TEGRA_PIN_KB_ROW7_PR7,
1419};
1420
1421static const unsigned drive_ao2_pins[] = {
1422 TEGRA_PIN_KB_ROW8_PS0,
1423 TEGRA_PIN_KB_ROW9_PS1,
1424 TEGRA_PIN_KB_ROW10_PS2,
1425 TEGRA_PIN_KB_ROW11_PS3,
1426 TEGRA_PIN_KB_ROW12_PS4,
1427 TEGRA_PIN_KB_ROW13_PS5,
1428 TEGRA_PIN_KB_ROW14_PS6,
1429 TEGRA_PIN_KB_ROW15_PS7,
1430 TEGRA_PIN_KB_COL0_PQ0,
1431 TEGRA_PIN_KB_COL1_PQ1,
1432 TEGRA_PIN_KB_COL2_PQ2,
1433 TEGRA_PIN_KB_COL3_PQ3,
1434 TEGRA_PIN_KB_COL4_PQ4,
1435 TEGRA_PIN_KB_COL5_PQ5,
1436 TEGRA_PIN_KB_COL6_PQ6,
1437 TEGRA_PIN_KB_COL7_PQ7,
1438 TEGRA_PIN_LED_BLINK_PBB0,
1439 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1440 TEGRA_PIN_CORE_PWR_REQ,
1441 TEGRA_PIN_CPU_PWR_REQ,
1442 TEGRA_PIN_PWR_INT_N,
1443 TEGRA_PIN_CLK_32_K_IN,
1444};
1445
1446static const unsigned drive_at1_pins[] = {
1447 TEGRA_PIN_GMI_IORDY_PI5,
1448 TEGRA_PIN_GMI_AD8_PH0,
1449 TEGRA_PIN_GMI_AD9_PH1,
1450 TEGRA_PIN_GMI_AD10_PH2,
1451 TEGRA_PIN_GMI_AD11_PH3,
1452 TEGRA_PIN_GMI_AD12_PH4,
1453 TEGRA_PIN_GMI_AD13_PH5,
1454 TEGRA_PIN_GMI_AD14_PH6,
1455 TEGRA_PIN_GMI_AD15_PH7,
1456 TEGRA_PIN_GMI_CS7_N_PI6,
1457 TEGRA_PIN_GMI_DPD_PT7,
1458 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1459 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1460};
1461
1462static const unsigned drive_at2_pins[] = {
1463 TEGRA_PIN_GMI_WAIT_PI7,
1464 TEGRA_PIN_GMI_ADV_N_PK0,
1465 TEGRA_PIN_GMI_CLK_PK1,
1466 TEGRA_PIN_GMI_CS6_N_PI3,
1467 TEGRA_PIN_GMI_CS5_N_PI2,
1468 TEGRA_PIN_GMI_CS4_N_PK2,
1469 TEGRA_PIN_GMI_CS3_N_PK4,
1470 TEGRA_PIN_GMI_CS2_N_PK3,
1471 TEGRA_PIN_GMI_AD0_PG0,
1472 TEGRA_PIN_GMI_AD1_PG1,
1473 TEGRA_PIN_GMI_AD2_PG2,
1474 TEGRA_PIN_GMI_AD3_PG3,
1475 TEGRA_PIN_GMI_AD4_PG4,
1476 TEGRA_PIN_GMI_AD5_PG5,
1477 TEGRA_PIN_GMI_AD6_PG6,
1478 TEGRA_PIN_GMI_AD7_PG7,
1479 TEGRA_PIN_GMI_HIOW_N_PI0,
1480 TEGRA_PIN_GMI_HIOR_N_PI1,
1481 TEGRA_PIN_GMI_RST_N_PI4,
1482};
1483
1484static const unsigned drive_cdev1_pins[] = {
1485 TEGRA_PIN_DAP_MCLK1_PW4,
1486};
1487
1488static const unsigned drive_cdev2_pins[] = {
1489 TEGRA_PIN_DAP_MCLK2_PW5,
1490};
1491
1492static const unsigned drive_csus_pins[] = {
1493 TEGRA_PIN_VI_MCLK_PT1,
1494};
1495
1496static const unsigned drive_dap1_pins[] = {
1497 TEGRA_PIN_DAP1_FS_PN0,
1498 TEGRA_PIN_DAP1_DIN_PN1,
1499 TEGRA_PIN_DAP1_DOUT_PN2,
1500 TEGRA_PIN_DAP1_SCLK_PN3,
1501 TEGRA_PIN_SPDIF_OUT_PK5,
1502 TEGRA_PIN_SPDIF_IN_PK6,
1503};
1504
1505static const unsigned drive_dap2_pins[] = {
1506 TEGRA_PIN_DAP2_FS_PA2,
1507 TEGRA_PIN_DAP2_SCLK_PA3,
1508 TEGRA_PIN_DAP2_DIN_PA4,
1509 TEGRA_PIN_DAP2_DOUT_PA5,
1510};
1511
1512static const unsigned drive_dap3_pins[] = {
1513 TEGRA_PIN_DAP3_FS_PP0,
1514 TEGRA_PIN_DAP3_DIN_PP1,
1515 TEGRA_PIN_DAP3_DOUT_PP2,
1516 TEGRA_PIN_DAP3_SCLK_PP3,
1517};
1518
1519static const unsigned drive_dap4_pins[] = {
1520 TEGRA_PIN_DAP4_FS_PP4,
1521 TEGRA_PIN_DAP4_DIN_PP5,
1522 TEGRA_PIN_DAP4_DOUT_PP6,
1523 TEGRA_PIN_DAP4_SCLK_PP7,
1524};
1525
1526static const unsigned drive_dbg_pins[] = {
1527 TEGRA_PIN_PU0,
1528 TEGRA_PIN_PU1,
1529 TEGRA_PIN_PU2,
1530 TEGRA_PIN_PU3,
1531 TEGRA_PIN_PU4,
1532 TEGRA_PIN_PU5,
1533 TEGRA_PIN_PU6,
1534 TEGRA_PIN_JTAG_RTCK_PU7,
1535 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1536 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1537 TEGRA_PIN_JTAG_TRST_N,
1538 TEGRA_PIN_JTAG_TDO,
1539 TEGRA_PIN_JTAG_TMS,
1540 TEGRA_PIN_JTAG_TCK,
1541 TEGRA_PIN_JTAG_TDI,
1542 TEGRA_PIN_TEST_MODE_EN,
1543};
1544
1545static const unsigned drive_lcd1_pins[] = {
1546 TEGRA_PIN_LCD_PWR1_PC1,
1547 TEGRA_PIN_LCD_PWR2_PC6,
1548 TEGRA_PIN_LCD_SDIN_PZ2,
1549 TEGRA_PIN_LCD_SDOUT_PN5,
1550 TEGRA_PIN_LCD_WR_N_PZ3,
1551 TEGRA_PIN_LCD_CS0_N_PN4,
1552 TEGRA_PIN_LCD_DC0_PN6,
1553 TEGRA_PIN_LCD_SCK_PZ4,
1554};
1555
1556static const unsigned drive_lcd2_pins[] = {
1557 TEGRA_PIN_LCD_PWR0_PB2,
1558 TEGRA_PIN_LCD_PCLK_PB3,
1559 TEGRA_PIN_LCD_DE_PJ1,
1560 TEGRA_PIN_LCD_HSYNC_PJ3,
1561 TEGRA_PIN_LCD_VSYNC_PJ4,
1562 TEGRA_PIN_LCD_D0_PE0,
1563 TEGRA_PIN_LCD_D1_PE1,
1564 TEGRA_PIN_LCD_D2_PE2,
1565 TEGRA_PIN_LCD_D3_PE3,
1566 TEGRA_PIN_LCD_D4_PE4,
1567 TEGRA_PIN_LCD_D5_PE5,
1568 TEGRA_PIN_LCD_D6_PE6,
1569 TEGRA_PIN_LCD_D7_PE7,
1570 TEGRA_PIN_LCD_D8_PF0,
1571 TEGRA_PIN_LCD_D9_PF1,
1572 TEGRA_PIN_LCD_D10_PF2,
1573 TEGRA_PIN_LCD_D11_PF3,
1574 TEGRA_PIN_LCD_D12_PF4,
1575 TEGRA_PIN_LCD_D13_PF5,
1576 TEGRA_PIN_LCD_D14_PF6,
1577 TEGRA_PIN_LCD_D15_PF7,
1578 TEGRA_PIN_LCD_D16_PM0,
1579 TEGRA_PIN_LCD_D17_PM1,
1580 TEGRA_PIN_LCD_D18_PM2,
1581 TEGRA_PIN_LCD_D19_PM3,
1582 TEGRA_PIN_LCD_D20_PM4,
1583 TEGRA_PIN_LCD_D21_PM5,
1584 TEGRA_PIN_LCD_D22_PM6,
1585 TEGRA_PIN_LCD_D23_PM7,
1586 TEGRA_PIN_LCD_CS1_N_PW0,
1587 TEGRA_PIN_LCD_M1_PW1,
1588 TEGRA_PIN_LCD_DC1_PV7,
1589 TEGRA_PIN_HDMI_INT_N_PN7,
1590};
1591
1592static const unsigned drive_sdmmc2_pins[] = {
1593 TEGRA_PIN_SDIO3_DAT4_PD1,
1594 TEGRA_PIN_SDIO3_DAT5_PD0,
1595 TEGRA_PIN_SDIO3_DAT6_PD3,
1596 TEGRA_PIN_SDIO3_DAT7_PD4,
1597};
1598
1599static const unsigned drive_sdmmc3_pins[] = {
1600 TEGRA_PIN_SDIO3_CLK_PA6,
1601 TEGRA_PIN_SDIO3_CMD_PA7,
1602 TEGRA_PIN_SDIO3_DAT0_PB7,
1603 TEGRA_PIN_SDIO3_DAT1_PB6,
1604 TEGRA_PIN_SDIO3_DAT2_PB5,
1605 TEGRA_PIN_SDIO3_DAT3_PB4,
1606 TEGRA_PIN_PV4,
1607 TEGRA_PIN_PV5,
1608 TEGRA_PIN_PV6,
1609};
1610
1611static const unsigned drive_spi_pins[] = {
1612 TEGRA_PIN_SPI2_MOSI_PX0,
1613 TEGRA_PIN_SPI2_MISO_PX1,
1614 TEGRA_PIN_SPI2_SCK_PX2,
1615 TEGRA_PIN_SPI2_CS0_N_PX3,
1616 TEGRA_PIN_SPI1_MOSI_PX4,
1617 TEGRA_PIN_SPI1_SCK_PX5,
1618 TEGRA_PIN_SPI1_CS0_N_PX6,
1619 TEGRA_PIN_SPI1_MISO_PX7,
1620 TEGRA_PIN_SPI2_CS1_N_PW2,
1621 TEGRA_PIN_SPI2_CS2_N_PW3,
1622};
1623
1624static const unsigned drive_uaa_pins[] = {
1625 TEGRA_PIN_ULPI_DATA0_PO1,
1626 TEGRA_PIN_ULPI_DATA1_PO2,
1627 TEGRA_PIN_ULPI_DATA2_PO3,
1628 TEGRA_PIN_ULPI_DATA3_PO4,
1629};
1630
1631static const unsigned drive_uab_pins[] = {
1632 TEGRA_PIN_ULPI_DATA4_PO5,
1633 TEGRA_PIN_ULPI_DATA5_PO6,
1634 TEGRA_PIN_ULPI_DATA6_PO7,
1635 TEGRA_PIN_ULPI_DATA7_PO0,
1636 TEGRA_PIN_PV0,
1637 TEGRA_PIN_PV1,
1638 TEGRA_PIN_PV2,
1639 TEGRA_PIN_PV3,
1640};
1641
1642static const unsigned drive_uart2_pins[] = {
1643 TEGRA_PIN_UART2_TXD_PC2,
1644 TEGRA_PIN_UART2_RXD_PC3,
1645 TEGRA_PIN_UART2_RTS_N_PJ6,
1646 TEGRA_PIN_UART2_CTS_N_PJ5,
1647};
1648
1649static const unsigned drive_uart3_pins[] = {
1650 TEGRA_PIN_UART3_TXD_PW6,
1651 TEGRA_PIN_UART3_RXD_PW7,
1652 TEGRA_PIN_UART3_RTS_N_PC0,
1653 TEGRA_PIN_UART3_CTS_N_PA1,
1654};
1655
1656static const unsigned drive_vi1_pins[] = {
1657 TEGRA_PIN_VI_D0_PT4,
1658 TEGRA_PIN_VI_D1_PD5,
1659 TEGRA_PIN_VI_D2_PL0,
1660 TEGRA_PIN_VI_D3_PL1,
1661 TEGRA_PIN_VI_D4_PL2,
1662 TEGRA_PIN_VI_D5_PL3,
1663 TEGRA_PIN_VI_D6_PL4,
1664 TEGRA_PIN_VI_D7_PL5,
1665 TEGRA_PIN_VI_D8_PL6,
1666 TEGRA_PIN_VI_D9_PL7,
1667 TEGRA_PIN_VI_D10_PT2,
1668 TEGRA_PIN_VI_D11_PT3,
1669 TEGRA_PIN_VI_PCLK_PT0,
1670 TEGRA_PIN_VI_VSYNC_PD6,
1671 TEGRA_PIN_VI_HSYNC_PD7,
1672};
1673
1674static const unsigned drive_vi2_pins[] = {
1675 TEGRA_PIN_VI_GP0_PBB1,
1676 TEGRA_PIN_CAM_I2C_SCL_PBB2,
1677 TEGRA_PIN_CAM_I2C_SDA_PBB3,
1678 TEGRA_PIN_VI_GP3_PBB4,
1679 TEGRA_PIN_VI_GP4_PBB5,
1680 TEGRA_PIN_VI_GP5_PD2,
1681 TEGRA_PIN_VI_GP6_PA0,
1682};
1683
1684static const unsigned drive_xm2a_pins[] = {
1685 TEGRA_PIN_DDR_A0,
1686 TEGRA_PIN_DDR_A1,
1687 TEGRA_PIN_DDR_A2,
1688 TEGRA_PIN_DDR_A3,
1689 TEGRA_PIN_DDR_A4,
1690 TEGRA_PIN_DDR_A5,
1691 TEGRA_PIN_DDR_A6,
1692 TEGRA_PIN_DDR_A7,
1693 TEGRA_PIN_DDR_A8,
1694 TEGRA_PIN_DDR_A9,
1695 TEGRA_PIN_DDR_A10,
1696 TEGRA_PIN_DDR_A11,
1697 TEGRA_PIN_DDR_A12,
1698 TEGRA_PIN_DDR_A13,
1699 TEGRA_PIN_DDR_A14,
1700 TEGRA_PIN_DDR_BA0,
1701 TEGRA_PIN_DDR_BA1,
1702 TEGRA_PIN_DDR_BA2,
1703 TEGRA_PIN_DDR_CS0_N,
1704 TEGRA_PIN_DDR_CS1_N,
1705 TEGRA_PIN_DDR_ODT,
1706 TEGRA_PIN_DDR_RAS_N,
1707 TEGRA_PIN_DDR_CAS_N,
1708 TEGRA_PIN_DDR_WE_N,
1709 TEGRA_PIN_DDR_CKE0,
1710 TEGRA_PIN_DDR_CKE1,
1711};
1712
1713static const unsigned drive_xm2c_pins[] = {
1714 TEGRA_PIN_DDR_DQS0P,
1715 TEGRA_PIN_DDR_DQS0N,
1716 TEGRA_PIN_DDR_DQS1P,
1717 TEGRA_PIN_DDR_DQS1N,
1718 TEGRA_PIN_DDR_DQS2P,
1719 TEGRA_PIN_DDR_DQS2N,
1720 TEGRA_PIN_DDR_DQS3P,
1721 TEGRA_PIN_DDR_DQS3N,
1722 TEGRA_PIN_DDR_QUSE0,
1723 TEGRA_PIN_DDR_QUSE1,
1724 TEGRA_PIN_DDR_QUSE2,
1725 TEGRA_PIN_DDR_QUSE3,
1726};
1727
1728static const unsigned drive_xm2d_pins[] = {
1729 TEGRA_PIN_DDR_DQ0,
1730 TEGRA_PIN_DDR_DQ1,
1731 TEGRA_PIN_DDR_DQ2,
1732 TEGRA_PIN_DDR_DQ3,
1733 TEGRA_PIN_DDR_DQ4,
1734 TEGRA_PIN_DDR_DQ5,
1735 TEGRA_PIN_DDR_DQ6,
1736 TEGRA_PIN_DDR_DQ7,
1737 TEGRA_PIN_DDR_DQ8,
1738 TEGRA_PIN_DDR_DQ9,
1739 TEGRA_PIN_DDR_DQ10,
1740 TEGRA_PIN_DDR_DQ11,
1741 TEGRA_PIN_DDR_DQ12,
1742 TEGRA_PIN_DDR_DQ13,
1743 TEGRA_PIN_DDR_DQ14,
1744 TEGRA_PIN_DDR_DQ15,
1745 TEGRA_PIN_DDR_DQ16,
1746 TEGRA_PIN_DDR_DQ17,
1747 TEGRA_PIN_DDR_DQ18,
1748 TEGRA_PIN_DDR_DQ19,
1749 TEGRA_PIN_DDR_DQ20,
1750 TEGRA_PIN_DDR_DQ21,
1751 TEGRA_PIN_DDR_DQ22,
1752 TEGRA_PIN_DDR_DQ23,
1753 TEGRA_PIN_DDR_DQ24,
1754 TEGRA_PIN_DDR_DQ25,
1755 TEGRA_PIN_DDR_DQ26,
1756 TEGRA_PIN_DDR_DQ27,
1757 TEGRA_PIN_DDR_DQ28,
1758 TEGRA_PIN_DDR_DQ29,
1759 TEGRA_PIN_DDR_DQ30,
1760 TEGRA_PIN_DDR_DQ31,
1761 TEGRA_PIN_DDR_DM0,
1762 TEGRA_PIN_DDR_DM1,
1763 TEGRA_PIN_DDR_DM2,
1764 TEGRA_PIN_DDR_DM3,
1765};
1766
1767static const unsigned drive_xm2clk_pins[] = {
1768 TEGRA_PIN_DDR_CLK,
1769 TEGRA_PIN_DDR_CLK_N,
1770};
1771
1772static const unsigned drive_sdio1_pins[] = {
1773 TEGRA_PIN_SDIO1_CLK_PZ0,
1774 TEGRA_PIN_SDIO1_CMD_PZ1,
1775 TEGRA_PIN_SDIO1_DAT0_PY7,
1776 TEGRA_PIN_SDIO1_DAT1_PY6,
1777 TEGRA_PIN_SDIO1_DAT2_PY5,
1778 TEGRA_PIN_SDIO1_DAT3_PY4,
1779};
1780
1781static const unsigned drive_crt_pins[] = {
1782 TEGRA_PIN_CRT_HSYNC,
1783 TEGRA_PIN_CRT_VSYNC,
1784};
1785
1786static const unsigned drive_ddc_pins[] = {
1787 TEGRA_PIN_DDC_SCL,
1788 TEGRA_PIN_DDC_SDA,
1789};
1790
1791static const unsigned drive_gma_pins[] = {
1792 TEGRA_PIN_GMI_AD20_PAA0,
1793 TEGRA_PIN_GMI_AD21_PAA1,
1794 TEGRA_PIN_GMI_AD22_PAA2,
1795 TEGRA_PIN_GMI_AD23_PAA3,
1796};
1797
1798static const unsigned drive_gmb_pins[] = {
1799 TEGRA_PIN_GMI_WP_N_PC7,
1800};
1801
1802static const unsigned drive_gmc_pins[] = {
1803 TEGRA_PIN_GMI_AD16_PJ7,
1804 TEGRA_PIN_GMI_AD17_PB0,
1805 TEGRA_PIN_GMI_AD18_PB1,
1806 TEGRA_PIN_GMI_AD19_PK7,
1807};
1808
1809static const unsigned drive_gmd_pins[] = {
1810 TEGRA_PIN_GMI_CS0_N_PJ0,
1811 TEGRA_PIN_GMI_CS1_N_PJ2,
1812};
1813
1814static const unsigned drive_gme_pins[] = {
1815 TEGRA_PIN_GMI_AD24_PAA4,
1816 TEGRA_PIN_GMI_AD25_PAA5,
1817 TEGRA_PIN_GMI_AD26_PAA6,
1818 TEGRA_PIN_GMI_AD27_PAA7,
1819};
1820
1821static const unsigned drive_owr_pins[] = {
1822 TEGRA_PIN_OWC,
1823};
1824
1825static const unsigned drive_uda_pins[] = {
1826 TEGRA_PIN_ULPI_CLK_PY0,
1827 TEGRA_PIN_ULPI_DIR_PY1,
1828 TEGRA_PIN_ULPI_NXT_PY2,
1829 TEGRA_PIN_ULPI_STP_PY3,
1830};
1831
1832enum tegra_mux {
1833 TEGRA_MUX_AHB_CLK,
1834 TEGRA_MUX_APB_CLK,
1835 TEGRA_MUX_AUDIO_SYNC,
1836 TEGRA_MUX_CRT,
1837 TEGRA_MUX_DAP1,
1838 TEGRA_MUX_DAP2,
1839 TEGRA_MUX_DAP3,
1840 TEGRA_MUX_DAP4,
1841 TEGRA_MUX_DAP5,
1842 TEGRA_MUX_DISPLAYA,
1843 TEGRA_MUX_DISPLAYB,
1844 TEGRA_MUX_EMC_TEST0_DLL,
1845 TEGRA_MUX_EMC_TEST1_DLL,
1846 TEGRA_MUX_GMI,
1847 TEGRA_MUX_GMI_INT,
1848 TEGRA_MUX_HDMI,
1849 TEGRA_MUX_I2CP,
1850 TEGRA_MUX_I2C1,
1851 TEGRA_MUX_I2C2,
1852 TEGRA_MUX_I2C3,
1853 TEGRA_MUX_IDE,
1854 TEGRA_MUX_IRDA,
1855 TEGRA_MUX_KBC,
1856 TEGRA_MUX_MIO,
1857 TEGRA_MUX_MIPI_HS,
1858 TEGRA_MUX_NAND,
1859 TEGRA_MUX_OSC,
1860 TEGRA_MUX_OWR,
1861 TEGRA_MUX_PCIE,
1862 TEGRA_MUX_PLLA_OUT,
1863 TEGRA_MUX_PLLC_OUT1,
1864 TEGRA_MUX_PLLM_OUT1,
1865 TEGRA_MUX_PLLP_OUT2,
1866 TEGRA_MUX_PLLP_OUT3,
1867 TEGRA_MUX_PLLP_OUT4,
1868 TEGRA_MUX_PWM,
1869 TEGRA_MUX_PWR_INTR,
1870 TEGRA_MUX_PWR_ON,
1871 TEGRA_MUX_RSVD1,
1872 TEGRA_MUX_RSVD2,
1873 TEGRA_MUX_RSVD3,
1874 TEGRA_MUX_RSVD4,
1875 TEGRA_MUX_RTCK,
1876 TEGRA_MUX_SDIO1,
1877 TEGRA_MUX_SDIO2,
1878 TEGRA_MUX_SDIO3,
1879 TEGRA_MUX_SDIO4,
1880 TEGRA_MUX_SFLASH,
1881 TEGRA_MUX_SPDIF,
1882 TEGRA_MUX_SPI1,
1883 TEGRA_MUX_SPI2,
1884 TEGRA_MUX_SPI2_ALT,
1885 TEGRA_MUX_SPI3,
1886 TEGRA_MUX_SPI4,
1887 TEGRA_MUX_TRACE,
1888 TEGRA_MUX_TWC,
1889 TEGRA_MUX_UARTA,
1890 TEGRA_MUX_UARTB,
1891 TEGRA_MUX_UARTC,
1892 TEGRA_MUX_UARTD,
1893 TEGRA_MUX_UARTE,
1894 TEGRA_MUX_ULPI,
1895 TEGRA_MUX_VI,
1896 TEGRA_MUX_VI_SENSOR_CLK,
1897 TEGRA_MUX_XIO,
1898};
1899
1900#define FUNCTION(fname) \
1901 { \
1902 .name = #fname, \
1903 }
1904
1905static struct tegra_function tegra20_functions[] = {
1906 FUNCTION(ahb_clk),
1907 FUNCTION(apb_clk),
1908 FUNCTION(audio_sync),
1909 FUNCTION(crt),
1910 FUNCTION(dap1),
1911 FUNCTION(dap2),
1912 FUNCTION(dap3),
1913 FUNCTION(dap4),
1914 FUNCTION(dap5),
1915 FUNCTION(displaya),
1916 FUNCTION(displayb),
1917 FUNCTION(emc_test0_dll),
1918 FUNCTION(emc_test1_dll),
1919 FUNCTION(gmi),
1920 FUNCTION(gmi_int),
1921 FUNCTION(hdmi),
1922 FUNCTION(i2cp),
1923 FUNCTION(i2c1),
1924 FUNCTION(i2c2),
1925 FUNCTION(i2c3),
1926 FUNCTION(ide),
1927 FUNCTION(irda),
1928 FUNCTION(kbc),
1929 FUNCTION(mio),
1930 FUNCTION(mipi_hs),
1931 FUNCTION(nand),
1932 FUNCTION(osc),
1933 FUNCTION(owr),
1934 FUNCTION(pcie),
1935 FUNCTION(plla_out),
1936 FUNCTION(pllc_out1),
1937 FUNCTION(pllm_out1),
1938 FUNCTION(pllp_out2),
1939 FUNCTION(pllp_out3),
1940 FUNCTION(pllp_out4),
1941 FUNCTION(pwm),
1942 FUNCTION(pwr_intr),
1943 FUNCTION(pwr_on),
1944 FUNCTION(rsvd1),
1945 FUNCTION(rsvd2),
1946 FUNCTION(rsvd3),
1947 FUNCTION(rsvd4),
1948 FUNCTION(rtck),
1949 FUNCTION(sdio1),
1950 FUNCTION(sdio2),
1951 FUNCTION(sdio3),
1952 FUNCTION(sdio4),
1953 FUNCTION(sflash),
1954 FUNCTION(spdif),
1955 FUNCTION(spi1),
1956 FUNCTION(spi2),
1957 FUNCTION(spi2_alt),
1958 FUNCTION(spi3),
1959 FUNCTION(spi4),
1960 FUNCTION(trace),
1961 FUNCTION(twc),
1962 FUNCTION(uarta),
1963 FUNCTION(uartb),
1964 FUNCTION(uartc),
1965 FUNCTION(uartd),
1966 FUNCTION(uarte),
1967 FUNCTION(ulpi),
1968 FUNCTION(vi),
1969 FUNCTION(vi_sensor_clk),
1970 FUNCTION(xio),
1971};
1972
1973#define TRISTATE_REG_A 0x14
1974#define PIN_MUX_CTL_REG_A 0x80
1975#define PULLUPDOWN_REG_A 0xa0
1976#define PINGROUP_REG_A 0x868
1977
1978/* Pin group with mux control, and typically tri-state and pull-up/down too */
1979#define MUX_PG(pg_name, f0, f1, f2, f3, \
1980 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
1981 { \
1982 .name = #pg_name, \
1983 .pins = pg_name##_pins, \
1984 .npins = ARRAY_SIZE(pg_name##_pins), \
1985 .funcs = { \
1986 TEGRA_MUX_ ## f0, \
1987 TEGRA_MUX_ ## f1, \
1988 TEGRA_MUX_ ## f2, \
1989 TEGRA_MUX_ ## f3, \
1990 }, \
1991 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
1992 .mux_bank = 1, \
1993 .mux_bit = mux_b, \
1994 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
1995 .pupd_bank = 2, \
1996 .pupd_bit = pupd_b, \
1997 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
1998 .tri_bank = 0, \
1999 .tri_bit = tri_b, \
2000 .parked_bit = -1, \
2001 .einput_bit = -1, \
2002 .odrain_bit = -1, \
2003 .lock_bit = -1, \
2004 .ioreset_bit = -1, \
2005 .rcv_sel_bit = -1, \
2006 .drv_reg = -1, \
2007 }
2008
2009/* Pin groups with only pull up and pull down control */
2010#define PULL_PG(pg_name, pupd_r, pupd_b) \
2011 { \
2012 .name = #pg_name, \
2013 .pins = pg_name##_pins, \
2014 .npins = ARRAY_SIZE(pg_name##_pins), \
2015 .mux_reg = -1, \
2016 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2017 .pupd_bank = 2, \
2018 .pupd_bit = pupd_b, \
2019 .drv_reg = -1, \
2020 .parked_bit = -1, \
2021 }
2022
2023/* Pin groups for drive strength registers (configurable version) */
2024#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2025 drvdn_b, drvup_b, \
2026 slwr_b, slwr_w, slwf_b, slwf_w) \
2027 { \
2028 .name = "drive_" #pg_name, \
2029 .pins = drive_##pg_name##_pins, \
2030 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2031 .mux_reg = -1, \
2032 .pupd_reg = -1, \
2033 .tri_reg = -1, \
2034 .drv_reg = ((r) - PINGROUP_REG_A), \
2035 .drv_bank = 3, \
2036 .parked_bit = -1, \
2037 .hsm_bit = hsm_b, \
2038 .schmitt_bit = schmitt_b, \
2039 .lpmd_bit = lpmd_b, \
2040 .drvdn_bit = drvdn_b, \
2041 .drvdn_width = 5, \
2042 .drvup_bit = drvup_b, \
2043 .drvup_width = 5, \
2044 .slwr_bit = slwr_b, \
2045 .slwr_width = slwr_w, \
2046 .slwf_bit = slwf_b, \
2047 .slwf_width = slwf_w, \
2048 .drvtype_bit = -1, \
2049 }
2050
2051/* Pin groups for drive strength registers (simple version) */
2052#define DRV_PG(pg_name, r) \
2053 DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
2054
2055static const struct tegra_pingroup tegra20_groups[] = {
2056 /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
2057 MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
2058 MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
2059 MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
2060 MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
2061 MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
2062 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
2063 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
2064 MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
2065 MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
2066 MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
2067 MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
2068 MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
2069 MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
2070 MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
2071 MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
2072 MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
2073 MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
2074 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
2075 MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
2076 MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
2077 MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
2078 MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
2079 MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
2080 MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
2081 MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
2082 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2083 MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
2084 MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
2085 MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
2086 MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
2087 MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
2088 MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
2089 MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
2090 MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
2091 MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
2092 MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
2093 MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
2094 MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
2095 MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
2096 MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
2097 MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
2098 MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
2099 MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
2100 MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
2101 MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
2102 MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
2103 MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
2104 MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
2105 MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
2106 MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
2107 MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
2108 MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
2109 MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
2110 MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
2111 MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
2112 MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
2113 MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
2114 MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
2115 MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
2116 MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
2117 MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
2118 MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
2119 MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
2120 MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
2121 MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
2122 MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
2123 MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
2124 MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
2125 MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
2126 MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
2127 MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
2128 MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
2129 MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
2130 MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
2131 MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
2132 MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
2133 MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
2134 MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
2135 MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
2136 MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
2137 MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
2138 MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
2139 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
2140 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
2141 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
2142 MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
2143 MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
2144 MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
2145 MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
2146 MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
2147 MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
2148 MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
2149 MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
2150 MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
2151 MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
2152 MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
2153 MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
2154 MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
2155 MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
2156 MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
2157 MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
2158 MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
2159 MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
2160 MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
2161 MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
2162 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
2163 MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
2164 /* pg_name, pupd_r/b */
2165 PULL_PG(ck32, 0xb0, 14),
2166 PULL_PG(ddrc, 0xac, 26),
2167 PULL_PG(pmca, 0xb0, 4),
2168 PULL_PG(pmcb, 0xb0, 6),
2169 PULL_PG(pmcc, 0xb0, 8),
2170 PULL_PG(pmcd, 0xb0, 10),
2171 PULL_PG(pmce, 0xb0, 12),
2172 PULL_PG(xm2c, 0xa8, 30),
2173 PULL_PG(xm2d, 0xa8, 28),
2174 PULL_PG(ls, 0xac, 20),
2175 PULL_PG(lc, 0xac, 22),
2176 PULL_PG(ld17_0, 0xac, 12),
2177 PULL_PG(ld19_18, 0xac, 14),
2178 PULL_PG(ld21_20, 0xac, 16),
2179 PULL_PG(ld23_22, 0xac, 18),
2180 /* pg_name, r */
2181 DRV_PG(ao1, 0x868),
2182 DRV_PG(ao2, 0x86c),
2183 DRV_PG(at1, 0x870),
2184 DRV_PG(at2, 0x874),
2185 DRV_PG(cdev1, 0x878),
2186 DRV_PG(cdev2, 0x87c),
2187 DRV_PG(csus, 0x880),
2188 DRV_PG(dap1, 0x884),
2189 DRV_PG(dap2, 0x888),
2190 DRV_PG(dap3, 0x88c),
2191 DRV_PG(dap4, 0x890),
2192 DRV_PG(dbg, 0x894),
2193 DRV_PG(lcd1, 0x898),
2194 DRV_PG(lcd2, 0x89c),
2195 DRV_PG(sdmmc2, 0x8a0),
2196 DRV_PG(sdmmc3, 0x8a4),
2197 DRV_PG(spi, 0x8a8),
2198 DRV_PG(uaa, 0x8ac),
2199 DRV_PG(uab, 0x8b0),
2200 DRV_PG(uart2, 0x8b4),
2201 DRV_PG(uart3, 0x8b8),
2202 DRV_PG(vi1, 0x8bc),
2203 DRV_PG(vi2, 0x8c0),
2204 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
2205 DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
2206 DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2207 DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2208 DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
2209 /* pg_name, r */
2210 DRV_PG(sdio1, 0x8e0),
2211 DRV_PG(crt, 0x8ec),
2212 DRV_PG(ddc, 0x8f0),
2213 DRV_PG(gma, 0x8f4),
2214 DRV_PG(gmb, 0x8f8),
2215 DRV_PG(gmc, 0x8fc),
2216 DRV_PG(gmd, 0x900),
2217 DRV_PG(gme, 0x904),
2218 DRV_PG(owr, 0x908),
2219 DRV_PG(uda, 0x90c),
2220};
2221
2222static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2223 .ngpios = NUM_GPIOS,
2224 .gpio_compatible = "nvidia,tegra20-gpio",
2225 .pins = tegra20_pins,
2226 .npins = ARRAY_SIZE(tegra20_pins),
2227 .functions = tegra20_functions,
2228 .nfunctions = ARRAY_SIZE(tegra20_functions),
2229 .groups = tegra20_groups,
2230 .ngroups = ARRAY_SIZE(tegra20_groups),
2231 .hsm_in_mux = false,
2232 .schmitt_in_mux = false,
2233 .drvtype_in_mux = false,
2234};
2235
2236static const char *cdev1_parents[] = {
2237 "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
2238};
2239
2240static const char *cdev2_parents[] = {
2241 "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
2242};
2243
2244static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
2245{
2246 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
2247
2248 clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
2249 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
2250
2251 clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
2252 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
2253}
2254
2255static int tegra20_pinctrl_probe(struct platform_device *pdev)
2256{
2257 int err;
2258
2259 err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2260 if (err)
2261 return err;
2262
2263 tegra20_pinctrl_register_clock_muxes(pdev);
2264
2265 return 0;
2266}
2267
2268static const struct of_device_id tegra20_pinctrl_of_match[] = {
2269 { .compatible = "nvidia,tegra20-pinmux", },
2270 { },
2271};
2272
2273static struct platform_driver tegra20_pinctrl_driver = {
2274 .driver = {
2275 .name = "tegra20-pinctrl",
2276 .of_match_table = tegra20_pinctrl_of_match,
2277 },
2278 .probe = tegra20_pinctrl_probe,
2279};
2280
2281static int __init tegra20_pinctrl_init(void)
2282{
2283 return platform_driver_register(&tegra20_pinctrl_driver);
2284}
2285arch_initcall(tegra20_pinctrl_init);