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1Devres - Managed Device Resource 2================================ 3 4Tejun Heo <teheo@suse.de> 5 6First draft 10 January 2007 7 8 91. Intro : Huh? Devres? 102. Devres : Devres in a nutshell 113. Devres Group : Group devres'es and release them together 124. Details : Life time rules, calling context, ... 135. Overhead : How much do we have to pay for this? 146. List of managed interfaces : Currently implemented managed interfaces 15 16 17 1. Intro 18 -------- 19 20devres came up while trying to convert libata to use iomap. Each 21iomapped address should be kept and unmapped on driver detach. For 22example, a plain SFF ATA controller (that is, good old PCI IDE) in 23native mode makes use of 5 PCI BARs and all of them should be 24maintained. 25 26As with many other device drivers, libata low level drivers have 27sufficient bugs in ->remove and ->probe failure path. Well, yes, 28that's probably because libata low level driver developers are lazy 29bunch, but aren't all low level driver developers? After spending a 30day fiddling with braindamaged hardware with no document or 31braindamaged document, if it's finally working, well, it's working. 32 33For one reason or another, low level drivers don't receive as much 34attention or testing as core code, and bugs on driver detach or 35initialization failure don't happen often enough to be noticeable. 36Init failure path is worse because it's much less travelled while 37needs to handle multiple entry points. 38 39So, many low level drivers end up leaking resources on driver detach 40and having half broken failure path implementation in ->probe() which 41would leak resources or even cause oops when failure occurs. iomap 42adds more to this mix. So do msi and msix. 43 44 45 2. Devres 46 --------- 47 48devres is basically linked list of arbitrarily sized memory areas 49associated with a struct device. Each devres entry is associated with 50a release function. A devres can be released in several ways. No 51matter what, all devres entries are released on driver detach. On 52release, the associated release function is invoked and then the 53devres entry is freed. 54 55Managed interface is created for resources commonly used by device 56drivers using devres. For example, coherent DMA memory is acquired 57using dma_alloc_coherent(). The managed version is called 58dmam_alloc_coherent(). It is identical to dma_alloc_coherent() except 59for the DMA memory allocated using it is managed and will be 60automatically released on driver detach. Implementation looks like 61the following. 62 63 struct dma_devres { 64 size_t size; 65 void *vaddr; 66 dma_addr_t dma_handle; 67 }; 68 69 static void dmam_coherent_release(struct device *dev, void *res) 70 { 71 struct dma_devres *this = res; 72 73 dma_free_coherent(dev, this->size, this->vaddr, this->dma_handle); 74 } 75 76 dmam_alloc_coherent(dev, size, dma_handle, gfp) 77 { 78 struct dma_devres *dr; 79 void *vaddr; 80 81 dr = devres_alloc(dmam_coherent_release, sizeof(*dr), gfp); 82 ... 83 84 /* alloc DMA memory as usual */ 85 vaddr = dma_alloc_coherent(...); 86 ... 87 88 /* record size, vaddr, dma_handle in dr */ 89 dr->vaddr = vaddr; 90 ... 91 92 devres_add(dev, dr); 93 94 return vaddr; 95 } 96 97If a driver uses dmam_alloc_coherent(), the area is guaranteed to be 98freed whether initialization fails half-way or the device gets 99detached. If most resources are acquired using managed interface, a 100driver can have much simpler init and exit code. Init path basically 101looks like the following. 102 103 my_init_one() 104 { 105 struct mydev *d; 106 107 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 108 if (!d) 109 return -ENOMEM; 110 111 d->ring = dmam_alloc_coherent(...); 112 if (!d->ring) 113 return -ENOMEM; 114 115 if (check something) 116 return -EINVAL; 117 ... 118 119 return register_to_upper_layer(d); 120 } 121 122And exit path, 123 124 my_remove_one() 125 { 126 unregister_from_upper_layer(d); 127 shutdown_my_hardware(); 128 } 129 130As shown above, low level drivers can be simplified a lot by using 131devres. Complexity is shifted from less maintained low level drivers 132to better maintained higher layer. Also, as init failure path is 133shared with exit path, both can get more testing. 134 135Note though that when converting current calls or assignments to 136managed devm_* versions it is up to you to check if internal operations 137like allocating memory, have failed. Managed resources pertains to the 138freeing of these resources *only* - all other checks needed are still 139on you. In some cases this may mean introducing checks that were not 140necessary before moving to the managed devm_* calls. 141 142 143 3. Devres group 144 --------------- 145 146Devres entries can be grouped using devres group. When a group is 147released, all contained normal devres entries and properly nested 148groups are released. One usage is to rollback series of acquired 149resources on failure. For example, 150 151 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 152 return -ENOMEM; 153 154 acquire A; 155 if (failed) 156 goto err; 157 158 acquire B; 159 if (failed) 160 goto err; 161 ... 162 163 devres_remove_group(dev, NULL); 164 return 0; 165 166 err: 167 devres_release_group(dev, NULL); 168 return err_code; 169 170As resource acquisition failure usually means probe failure, constructs 171like above are usually useful in midlayer driver (e.g. libata core 172layer) where interface function shouldn't have side effect on failure. 173For LLDs, just returning error code suffices in most cases. 174 175Each group is identified by void *id. It can either be explicitly 176specified by @id argument to devres_open_group() or automatically 177created by passing NULL as @id as in the above example. In both 178cases, devres_open_group() returns the group's id. The returned id 179can be passed to other devres functions to select the target group. 180If NULL is given to those functions, the latest open group is 181selected. 182 183For example, you can do something like the following. 184 185 int my_midlayer_create_something() 186 { 187 if (!devres_open_group(dev, my_midlayer_create_something, GFP_KERNEL)) 188 return -ENOMEM; 189 190 ... 191 192 devres_close_group(dev, my_midlayer_create_something); 193 return 0; 194 } 195 196 void my_midlayer_destroy_something() 197 { 198 devres_release_group(dev, my_midlayer_create_something); 199 } 200 201 202 4. Details 203 ---------- 204 205Lifetime of a devres entry begins on devres allocation and finishes 206when it is released or destroyed (removed and freed) - no reference 207counting. 208 209devres core guarantees atomicity to all basic devres operations and 210has support for single-instance devres types (atomic 211lookup-and-add-if-not-found). Other than that, synchronizing 212concurrent accesses to allocated devres data is caller's 213responsibility. This is usually non-issue because bus ops and 214resource allocations already do the job. 215 216For an example of single-instance devres type, read pcim_iomap_table() 217in lib/devres.c. 218 219All devres interface functions can be called without context if the 220right gfp mask is given. 221 222 223 5. Overhead 224 ----------- 225 226Each devres bookkeeping info is allocated together with requested data 227area. With debug option turned off, bookkeeping info occupies 16 228bytes on 32bit machines and 24 bytes on 64bit (three pointers rounded 229up to ull alignment). If singly linked list is used, it can be 230reduced to two pointers (8 bytes on 32bit, 16 bytes on 64bit). 231 232Each devres group occupies 8 pointers. It can be reduced to 6 if 233singly linked list is used. 234 235Memory space overhead on ahci controller with two ports is between 300 236and 400 bytes on 32bit machine after naive conversion (we can 237certainly invest a bit more effort into libata core layer). 238 239 240 6. List of managed interfaces 241 ----------------------------- 242 243CLOCK 244 devm_clk_get() 245 devm_clk_get_optional() 246 devm_clk_put() 247 devm_clk_hw_register() 248 devm_of_clk_add_hw_provider() 249 devm_clk_hw_register_clkdev() 250 251DMA 252 dmaenginem_async_device_register() 253 dmam_alloc_coherent() 254 dmam_alloc_attrs() 255 dmam_free_coherent() 256 dmam_pool_create() 257 dmam_pool_destroy() 258 259GPIO 260 devm_gpiod_get() 261 devm_gpiod_get_index() 262 devm_gpiod_get_index_optional() 263 devm_gpiod_get_optional() 264 devm_gpiod_put() 265 devm_gpiod_unhinge() 266 devm_gpiochip_add_data() 267 devm_gpio_request() 268 devm_gpio_request_one() 269 devm_gpio_free() 270 271IIO 272 devm_iio_device_alloc() 273 devm_iio_device_free() 274 devm_iio_device_register() 275 devm_iio_device_unregister() 276 devm_iio_kfifo_allocate() 277 devm_iio_kfifo_free() 278 devm_iio_triggered_buffer_setup() 279 devm_iio_triggered_buffer_cleanup() 280 devm_iio_trigger_alloc() 281 devm_iio_trigger_free() 282 devm_iio_trigger_register() 283 devm_iio_trigger_unregister() 284 devm_iio_channel_get() 285 devm_iio_channel_release() 286 devm_iio_channel_get_all() 287 devm_iio_channel_release_all() 288 289INPUT 290 devm_input_allocate_device() 291 292IO region 293 devm_release_mem_region() 294 devm_release_region() 295 devm_release_resource() 296 devm_request_mem_region() 297 devm_request_region() 298 devm_request_resource() 299 300IOMAP 301 devm_ioport_map() 302 devm_ioport_unmap() 303 devm_ioremap() 304 devm_ioremap_nocache() 305 devm_ioremap_wc() 306 devm_ioremap_resource() : checks resource, requests memory region, ioremaps 307 devm_iounmap() 308 pcim_iomap() 309 pcim_iomap_regions() : do request_region() and iomap() on multiple BARs 310 pcim_iomap_table() : array of mapped addresses indexed by BAR 311 pcim_iounmap() 312 313IRQ 314 devm_free_irq() 315 devm_request_any_context_irq() 316 devm_request_irq() 317 devm_request_threaded_irq() 318 devm_irq_alloc_descs() 319 devm_irq_alloc_desc() 320 devm_irq_alloc_desc_at() 321 devm_irq_alloc_desc_from() 322 devm_irq_alloc_descs_from() 323 devm_irq_alloc_generic_chip() 324 devm_irq_setup_generic_chip() 325 devm_irq_sim_init() 326 327LED 328 devm_led_classdev_register() 329 devm_led_classdev_unregister() 330 331MDIO 332 devm_mdiobus_alloc() 333 devm_mdiobus_alloc_size() 334 devm_mdiobus_free() 335 336MEM 337 devm_free_pages() 338 devm_get_free_pages() 339 devm_kasprintf() 340 devm_kcalloc() 341 devm_kfree() 342 devm_kmalloc() 343 devm_kmalloc_array() 344 devm_kmemdup() 345 devm_kstrdup() 346 devm_kvasprintf() 347 devm_kzalloc() 348 349MFD 350 devm_mfd_add_devices() 351 352MUX 353 devm_mux_chip_alloc() 354 devm_mux_chip_register() 355 devm_mux_control_get() 356 357PER-CPU MEM 358 devm_alloc_percpu() 359 devm_free_percpu() 360 361PCI 362 devm_pci_alloc_host_bridge() : managed PCI host bridge allocation 363 devm_pci_remap_cfgspace() : ioremap PCI configuration space 364 devm_pci_remap_cfg_resource() : ioremap PCI configuration space resource 365 pcim_enable_device() : after success, all PCI ops become managed 366 pcim_pin_device() : keep PCI device enabled after release 367 368PHY 369 devm_usb_get_phy() 370 devm_usb_put_phy() 371 372PINCTRL 373 devm_pinctrl_get() 374 devm_pinctrl_put() 375 devm_pinctrl_register() 376 devm_pinctrl_unregister() 377 378POWER 379 devm_reboot_mode_register() 380 devm_reboot_mode_unregister() 381 382PWM 383 devm_pwm_get() 384 devm_pwm_put() 385 386REGULATOR 387 devm_regulator_bulk_get() 388 devm_regulator_get() 389 devm_regulator_put() 390 devm_regulator_register() 391 392RESET 393 devm_reset_control_get() 394 devm_reset_controller_register() 395 396SERDEV 397 devm_serdev_device_open() 398 399SLAVE DMA ENGINE 400 devm_acpi_dma_controller_register() 401 402SPI 403 devm_spi_register_master() 404 405WATCHDOG 406 devm_watchdog_register_device()