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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_BW_H__
7#define __INTEL_BW_H__
8
9#include <drm/drm_atomic.h>
10
11#include "intel_display_limits.h"
12#include "intel_display_power.h"
13#include "intel_global_state.h"
14
15struct drm_i915_private;
16struct intel_atomic_state;
17struct intel_crtc_state;
18
19struct intel_dbuf_bw {
20 unsigned int max_bw[I915_MAX_DBUF_SLICES];
21 u8 active_planes[I915_MAX_DBUF_SLICES];
22};
23
24struct intel_bw_state {
25 struct intel_global_state base;
26 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
27
28 /*
29 * Contains a bit mask, used to determine, whether correspondent
30 * pipe allows SAGV or not.
31 */
32 u8 pipe_sagv_reject;
33
34 /* bitmask of active pipes */
35 u8 active_pipes;
36
37 /*
38 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
39 * the selected QGV point as the parameter in multiples of 100MB/s
40 */
41 u16 qgv_point_peakbw;
42
43 /*
44 * Current QGV points mask, which restricts
45 * some particular SAGV states, not to confuse
46 * with pipe_sagv_mask.
47 */
48 u16 qgv_points_mask;
49
50 /*
51 * Flag to force the QGV comparison in atomic check right after the
52 * hw state readout
53 */
54 bool force_check_qgv;
55
56 int min_cdclk[I915_MAX_PIPES];
57 unsigned int data_rate[I915_MAX_PIPES];
58 u8 num_active_planes[I915_MAX_PIPES];
59};
60
61#define to_intel_bw_state(global_state) \
62 container_of_const((global_state), struct intel_bw_state, base)
63
64struct intel_bw_state *
65intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
66
67struct intel_bw_state *
68intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
69
70struct intel_bw_state *
71intel_atomic_get_bw_state(struct intel_atomic_state *state);
72
73void intel_bw_init_hw(struct drm_i915_private *dev_priv);
74int intel_bw_init(struct drm_i915_private *dev_priv);
75int intel_bw_atomic_check(struct intel_atomic_state *state);
76void intel_bw_crtc_update(struct intel_bw_state *bw_state,
77 const struct intel_crtc_state *crtc_state);
78int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
79 u32 points_mask);
80int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
81 bool *need_cdclk_calc);
82int intel_bw_min_cdclk(struct drm_i915_private *i915,
83 const struct intel_bw_state *bw_state);
84
85#endif /* __INTEL_BW_H__ */