···11+library ieee;
22+use IEEE.STD_LOGIC_1164.all;
33+use ieee.numeric_std.all;
44+55+library STD;
66+use STD.textio.all;
77+88+entity tb is
99+end tb;
1010+1111+architecture beh of tb is
1212+1313+component simple
1414+port (
1515+ CLK, RESET : in std_ulogic;
1616+ DATA_OUT : out std_ulogic_vector(7 downto 0);
1717+ DONE_OUT : out std_ulogic
1818+);
1919+end component;
2020+2121+signal data : std_ulogic_vector(7 downto 0) := "00100000";
2222+signal clk : std_ulogic;
2323+signal RESET : std_ulogic := '0';
2424+signal done : std_ulogic := '0';
2525+signal cyclecount : integer := 0;
2626+2727+constant cycle_time_c : time := 200 ms;
2828+constant maxcycles : integer := 100;
2929+3030+begin
3131+3232+simple1 : simple
3333+port map (
3434+ CLK => clk,
3535+ RESET => RESET,
3636+ DATA_OUT => data,
3737+ DONE_OUT => done
3838+);
3939+4040+clk_process : process
4141+begin
4242+ clk <= '0';
4343+ wait for cycle_time_c/2;
4444+ clk <= '1';
4545+ wait for cycle_time_c/2;
4646+end process;
4747+4848+count_process : process(CLK)
4949+begin
5050+ if (CLK'event and CLK ='1') then
5151+ if (RESET = '1') then
5252+ cyclecount <= 0;
5353+ else
5454+ cyclecount <= cyclecount + 1;
5555+ end if;
5656+ end if;
5757+end process;
5858+5959+test : process
6060+6161+begin
6262+6363+RESET <= '1';
6464+wait until (clk'event and clk='1');
6565+wait until (clk'event and clk='1');
6666+RESET <= '0';
6767+wait until (clk'event and clk='1');
6868+for cyclecnt in 1 to maxcycles loop
6969+ exit when done = '1';
7070+ wait until (clk'event and clk='1');
7171+ report integer'image(to_integer(unsigned(data)));
7272+end loop;
7373+wait until (clk'event and clk='1');
7474+7575+report "All tests passed." severity NOTE;
7676+wait;
7777+end process;
7878+end beh;
+45
pkgs/development/compilers/ghdl/simple.vhd
···11+library IEEE;
22+use IEEE.STD_LOGIC_1164.all;
33+use IEEE.NUMERIC_STD.ALL;
44+use IEEE.STD_LOGIC_MISC.or_reduce;
55+66+entity simple is
77+88+port (
99+ CLK, RESET : in std_ulogic;
1010+ DATA_OUT : out std_ulogic_vector(7 downto 0);
1111+ DONE_OUT : out std_ulogic
1212+);
1313+end simple;
1414+1515+architecture beh of simple is
1616+1717+signal data : std_ulogic_vector(7 downto 0);
1818+signal done: std_ulogic;
1919+2020+begin
2121+2222+proc_ctr : process(CLK)
2323+begin
2424+if (CLK = '1' and CLK'event) then
2525+ if (RESET = '1') then
2626+ data <= "01011111";
2727+ done <= '0';
2828+ else
2929+ case data is
3030+ when "00100000" => data <= "01001110";
3131+ when "01001110" => data <= "01101001";
3232+ when "01101001" => data <= "01111000";
3333+ when "01111000" => data <= "01001111";
3434+ when "01001111" => data <= "01010011";
3535+ when others => data <= "00100000";
3636+ end case;
3737+ done <= not or_reduce(data xor "01010011");
3838+ end if;
3939+end if;
4040+end process;
4141+4242+DATA_OUT <= data;
4343+DONE_OUT <= done;
4444+4545+end beh;