verible: init at 0.0-2172-g238b6df6

Verible is a suite of SystemVerilog developer tools, including a parser,
style-linter, formatter, and language server.

Signed-off-by: Henner Zeller <[e-mail]>

pkgs/development/tools/verible/default.nix

···
+{ lib
+, stdenv
+, fetchFromGitHub
+, buildBazelPackage
+, bazel_4
+, flex
+, bison
+, python3
+}:
+
+buildBazelPackage rec {
+  pname = "verible";
+  version = "0.0-2172-g238b6df6";
+
+  # These environment variables are read in bazel/build-version.py to create
+  # a build string. Otherwise it would attempt to extract it from .git/.
+  GIT_DATE = "2022-08-08";
+  GIT_VERSION = version;
+
+  src = fetchFromGitHub {
+    owner = "chipsalliance";
+    repo = "verible";
+    rev = "v${version}";
+    sha256 = "sha256-iOJhdbipuqqBiYGgk95d1c8bEK6Z16l16GuzYCQRc2g=";
+  };
+
+  patches = [
+    # Patch WORKSPACE file to not include windows-related dependencies,
+    # as they are removed by bazel, breaking the fixed output derivation
+    # TODO: fix upstream
+    ./remove-unused-deps.patch
+  ];
+
+  bazelFlags = [ "--//bazel:use_local_flex_bison" ];
+
+  fetchAttrs = {
+    # Fixed output derivation hash after bazel fetch
+    sha256 = "sha256-XoLdlEeoDJlyWlnXZADHOKu06zKHgHJfgey8UhOt+LM=";
+  };
+
+  nativeBuildInputs = [
+    flex       # We use local flex and bison as WORKSPACE sources fail
+    bison      # .. to compile with newer glibc
+    python3
+  ];
+
+  postPatch = ''
+    patchShebangs bazel/build-version.py \
+      common/util/create_version_header.sh \
+      common/parser/move_yacc_stack_symbols.sh \
+      common/parser/record_syntax_error.sh
+  '';
+
+  removeRulesCC = false;
+  bazelTarget = ":install-binaries";
+  bazelBuildFlags = [
+    "-c opt"
+  ];
+  buildAttrs = {
+    installPhase = ''
+      mkdir -p "$out/bin"
+
+      install bazel-bin/common/tools/verible-patch-tool "$out/bin"
+
+      V_TOOLS_DIR=bazel-bin/verilog/tools
+      install $V_TOOLS_DIR/diff/verible-verilog-diff "$out/bin"
+      install $V_TOOLS_DIR/formatter/verible-verilog-format "$out/bin"
+      install $V_TOOLS_DIR/kythe/verible-verilog-kythe-extractor "$out/bin"
+      install $V_TOOLS_DIR/lint/verible-verilog-lint "$out/bin"
+      install $V_TOOLS_DIR/ls/verible-verilog-ls "$out/bin"
+      install $V_TOOLS_DIR/obfuscator/verible-verilog-obfuscate "$out/bin"
+      install $V_TOOLS_DIR/preprocessor/verible-verilog-preprocessor "$out/bin"
+      install $V_TOOLS_DIR/project/verible-verilog-project "$out/bin"
+      install $V_TOOLS_DIR/syntax/verible-verilog-syntax "$out/bin"
+    '';
+  };
+
+  meta = with lib; {
+    homepage = "https://github.com/chipsalliance/verible";
+    description = "Suite of SystemVerilog developer tools. Including a style-linter, indexer, formatter, and language server.";
+    license = licenses.asl20;
+    platforms = platforms.linux;
+    maintainers = with maintainers; [ hzeller ];
+  };
+}

pkgs/development/tools/verible/remove-unused-deps.patch

···
+diff --git a/WORKSPACE b/WORKSPACE
+index 696cc7ef..55a5bb8a 100644
+--- a/WORKSPACE
++++ b/WORKSPACE
+@@ -81,17 +81,6 @@ load("@com_github_google_rules_install//:setup.bzl", "install_rules_setup")
+ 
+ install_rules_setup()
+ 
+-# Need to load before rules_flex/rules_bison to make sure
+-# win_flex_bison is the chosen toolchain on Windows
+-load("//bazel:win_flex_bison.bzl", "win_flex_configure")
+-
+-win_flex_configure(
+-    name = "win_flex_bison",
+-    sha256 = "095cf65cb3f12ee5888022f93109acbe6264e5f18f6ffce0bda77feb31b65bd8",
+-    # bison 3.3.2, flex 2.6.4
+-    url = "https://github.com/lexxmark/winflexbison/releases/download/v2.5.18/win_flex_bison-2.5.18.zip",
+-)
+-
+ http_archive(
+     name = "rules_m4",
+     sha256 = "c67fa9891bb19e9e6c1050003ba648d35383b8cb3c9572f397ad24040fb7f0eb",

pkgs/top-level/all-packages.nix

···
 
   verco = callPackage ../applications/version-management/verco { };
 
+  verible = callPackage ../development/tools/verible { };
+
   verilator = callPackage ../applications/science/electronics/verilator {};
 
   verilog = callPackage ../applications/science/electronics/verilog {