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binutils: Add PaX patch

Ricardo M. Correia 2902c8f6 a0f68368

+1791
unified split
+5
pkgs/development/tools/misc/binutils/default.nix
··· 27 28 # Make binutils output deterministic by default. 29 ./deterministic.patch 30 ]; 31 32 buildInputs =
··· 27 28 # Make binutils output deterministic by default. 29 ./deterministic.patch 30 + 31 + # Always add PaX flags section to ELF files. 32 + # This is needed, for instance, so that running "ldd" on a binary that is 33 + # PaX-marked to disable mprotect doesn't fail with permission denied. 34 + ./pt-pax-flags-20121023.patch 35 ]; 36 37 buildInputs =
+1786
pkgs/development/tools/misc/binutils/pt-pax-flags-20121023.patch
···
··· 1 + --- binutils-2.23/bfd/elf-bfd.h 2 + +++ binutils-2.23/bfd/elf-bfd.h 3 + @@ -1577,6 +1577,9 @@ struct elf_obj_tdata 4 + /* Segment flags for the PT_GNU_STACK segment. */ 5 + unsigned int stack_flags; 6 + 7 + + /* Segment flags for the PT_PAX_FLAGS segment. */ 8 + + unsigned int pax_flags; 9 + + 10 + /* Symbol version definitions in external objects. */ 11 + Elf_Internal_Verdef *verdef; 12 + 13 + --- binutils-2.23/bfd/elf.c 14 + +++ binutils-2.23/bfd/elf.c 15 + @@ -1158,6 +1158,7 @@ get_segment_type (unsigned int p_type) 16 + case PT_GNU_EH_FRAME: pt = "EH_FRAME"; break; 17 + case PT_GNU_STACK: pt = "STACK"; break; 18 + case PT_GNU_RELRO: pt = "RELRO"; break; 19 + + case PT_PAX_FLAGS: pt = "PAX_FLAGS"; break; 20 + default: pt = NULL; break; 21 + } 22 + return pt; 23 + @@ -2477,6 +2478,9 @@ bfd_section_from_phdr (bfd *abfd, Elf_Internal_Phdr *hdr, int hdr_index) 24 + case PT_GNU_RELRO: 25 + return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index, "relro"); 26 + 27 + + case PT_PAX_FLAGS: 28 + + return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index, "pax_flags"); 29 + + 30 + default: 31 + /* Check for any processor-specific program segment types. */ 32 + bed = get_elf_backend_data (abfd); 33 + @@ -3551,6 +3555,11 @@ get_program_header_size (bfd *abfd, struct bfd_link_info *info) 34 + ++segs; 35 + } 36 + 37 + + { 38 + + /* We need a PT_PAX_FLAGS segment. */ 39 + + ++segs; 40 + + } 41 + + 42 + for (s = abfd->sections; s != NULL; s = s->next) 43 + { 44 + if ((s->flags & SEC_LOAD) != 0 45 + @@ -4153,6 +4162,20 @@ _bfd_elf_map_sections_to_segments (bfd *abfd, struct bfd_link_info *info) 46 + } 47 + } 48 + 49 + + { 50 + + amt = sizeof (struct elf_segment_map); 51 + + m = bfd_zalloc (abfd, amt); 52 + + if (m == NULL) 53 + + goto error_return; 54 + + m->next = NULL; 55 + + m->p_type = PT_PAX_FLAGS; 56 + + m->p_flags = elf_tdata (abfd)->pax_flags; 57 + + m->p_flags_valid = 1; 58 + + 59 + + *pm = m; 60 + + pm = &m->next; 61 + + } 62 + + 63 + free (sections); 64 + elf_tdata (abfd)->segment_map = mfirst; 65 + } 66 + @@ -5417,7 +5440,8 @@ rewrite_elf_program_header (bfd *ibfd, bfd *obfd) 67 + 6. PT_TLS segment includes only SHF_TLS sections. 68 + 7. SHF_TLS sections are only in PT_TLS or PT_LOAD segments. 69 + 8. PT_DYNAMIC should not contain empty sections at the beginning 70 + - (with the possible exception of .dynamic). */ 71 + + (with the possible exception of .dynamic). 72 + + 9. PT_PAX_FLAGS segments do not include any sections. */ 73 + #define IS_SECTION_IN_INPUT_SEGMENT(section, segment, bed) \ 74 + ((((segment->p_paddr \ 75 + ? IS_CONTAINED_BY_LMA (section, segment, segment->p_paddr) \ 76 + @@ -5425,6 +5449,7 @@ rewrite_elf_program_header (bfd *ibfd, bfd *obfd) 77 + && (section->flags & SEC_ALLOC) != 0) \ 78 + || IS_NOTE (segment, section)) \ 79 + && segment->p_type != PT_GNU_STACK \ 80 + + && segment->p_type != PT_PAX_FLAGS \ 81 + && (segment->p_type != PT_TLS \ 82 + || (section->flags & SEC_THREAD_LOCAL)) \ 83 + && (segment->p_type == PT_LOAD \ 84 + --- binutils-2.23/bfd/elflink.c 85 + +++ binutils-2.23/bfd/elflink.c 86 + @@ -5545,16 +5545,30 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd, 87 + return TRUE; 88 + 89 + bed = get_elf_backend_data (output_bfd); 90 + + 91 + + elf_tdata (output_bfd)->pax_flags = PF_NORANDEXEC; 92 + + if (info->execheap) 93 + + elf_tdata (output_bfd)->pax_flags |= PF_NOMPROTECT; 94 + + else if (info->noexecheap) 95 + + elf_tdata (output_bfd)->pax_flags |= PF_MPROTECT; 96 + + 97 + if (info->execstack) 98 + - elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X; 99 + + { 100 + + elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X; 101 + + elf_tdata (output_bfd)->pax_flags |= PF_EMUTRAMP; 102 + + } 103 + else if (info->noexecstack) 104 + - elf_tdata (output_bfd)->stack_flags = PF_R | PF_W; 105 + + { 106 + + elf_tdata (output_bfd)->stack_flags = PF_R | PF_W; 107 + + elf_tdata (output_bfd)->pax_flags |= PF_NOEMUTRAMP; 108 + + } 109 + else 110 + { 111 + bfd *inputobj; 112 + asection *notesec = NULL; 113 + int exec = 0; 114 + 115 + + elf_tdata (output_bfd)->pax_flags |= PF_NOEMUTRAMP; 116 + for (inputobj = info->input_bfds; 117 + inputobj; 118 + inputobj = inputobj->link_next) 119 + @@ -5567,7 +5581,11 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd, 120 + if (s) 121 + { 122 + if (s->flags & SEC_CODE) 123 + - exec = PF_X; 124 + + { 125 + + elf_tdata (output_bfd)->pax_flags &= ~PF_NOEMUTRAMP; 126 + + elf_tdata (output_bfd)->pax_flags |= PF_EMUTRAMP; 127 + + exec = PF_X; 128 + + } 129 + notesec = s; 130 + } 131 + else if (bed->default_execstack) 132 + --- binutils-2.23/binutils/readelf.c 133 + +++ binutils-2.23/binutils/readelf.c 134 + @@ -2740,6 +2740,7 @@ get_segment_type (unsigned long p_type) 135 + return "GNU_EH_FRAME"; 136 + case PT_GNU_STACK: return "GNU_STACK"; 137 + case PT_GNU_RELRO: return "GNU_RELRO"; 138 + + case PT_PAX_FLAGS: return "PAX_FLAGS"; 139 + 140 + default: 141 + if ((p_type >= PT_LOPROC) && (p_type <= PT_HIPROC)) 142 + --- binutils-2.23/include/bfdlink.h 143 + +++ binutils-2.23/include/bfdlink.h 144 + @@ -322,6 +322,14 @@ struct bfd_link_info 145 + /* TRUE if PT_GNU_RELRO segment should be created. */ 146 + unsigned int relro: 1; 147 + 148 + + /* TRUE if PT_PAX_FLAGS segment should be created with PF_NOMPROTECT 149 + + flags. */ 150 + + unsigned int execheap: 1; 151 + + 152 + + /* TRUE if PT_PAX_FLAGS segment should be created with PF_MPROTECT 153 + + flags. */ 154 + + unsigned int noexecheap: 1; 155 + + 156 + /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment 157 + should be created. */ 158 + unsigned int eh_frame_hdr: 1; 159 + --- binutils-2.23/include/elf/common.h 160 + +++ binutils-2.23/include/elf/common.h 161 + @@ -429,6 +429,7 @@ 162 + #define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME /* Solaris uses the same value */ 163 + #define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */ 164 + #define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */ 165 + +#define PT_PAX_FLAGS (PT_LOOS + 0x5041580) /* PaX flags */ 166 + 167 + /* Program segment permissions, in program header p_flags field. */ 168 + 169 + @@ -439,6 +440,21 @@ 170 + #define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ 171 + #define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ 172 + 173 + +/* Flags to control PaX behavior. */ 174 + + 175 + +#define PF_PAGEEXEC (1 << 4) /* Enable PAGEEXEC */ 176 + +#define PF_NOPAGEEXEC (1 << 5) /* Disable PAGEEXEC */ 177 + +#define PF_SEGMEXEC (1 << 6) /* Enable SEGMEXEC */ 178 + +#define PF_NOSEGMEXEC (1 << 7) /* Disable SEGMEXEC */ 179 + +#define PF_MPROTECT (1 << 8) /* Enable MPROTECT */ 180 + +#define PF_NOMPROTECT (1 << 9) /* Disable MPROTECT */ 181 + +#define PF_RANDEXEC (1 << 10) /* Enable RANDEXEC */ 182 + +#define PF_NORANDEXEC (1 << 11) /* Disable RANDEXEC */ 183 + +#define PF_EMUTRAMP (1 << 12) /* Enable EMUTRAMP */ 184 + +#define PF_NOEMUTRAMP (1 << 13) /* Disable EMUTRAMP */ 185 + +#define PF_RANDMMAP (1 << 14) /* Enable RANDMMAP */ 186 + +#define PF_NORANDMMAP (1 << 15) /* Disable RANDMMAP */ 187 + + 188 + /* Values for section header, sh_type field. */ 189 + 190 + #define SHT_NULL 0 /* Section header table entry unused */ 191 + --- binutils-2.23/ld/emultempl/elf32.em 192 + +++ binutils-2.23/ld/emultempl/elf32.em 193 + @@ -2285,6 +2285,16 @@ fragment <<EOF 194 + link_info.noexecstack = TRUE; 195 + link_info.execstack = FALSE; 196 + } 197 + + else if (strcmp (optarg, "execheap") == 0) 198 + + { 199 + + link_info.execheap = TRUE; 200 + + link_info.noexecheap = FALSE; 201 + + } 202 + + else if (strcmp (optarg, "noexecheap") == 0) 203 + + { 204 + + link_info.noexecheap = TRUE; 205 + + link_info.execheap = FALSE; 206 + + } 207 + EOF 208 + if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then 209 + fragment <<EOF 210 + @@ -2368,6 +2378,8 @@ fragment <<EOF 211 + -z defs Report unresolved symbols in object files.\n")); 212 + fprintf (file, _("\ 213 + -z execstack Mark executable as requiring executable stack\n")); 214 + + fprintf (file, _("\ 215 + + -z execheap Mark executable as requiring executable heap\n")); 216 + EOF 217 + 218 + if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then 219 + @@ -2391,6 +2403,8 @@ fragment <<EOF 220 + fragment <<EOF 221 + fprintf (file, _("\ 222 + -z noexecstack Mark executable as not requiring executable stack\n")); 223 + + fprintf (file, _("\ 224 + + -z noexecheap Mark executable as not requiring executable heap\n")); 225 + EOF 226 + if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then 227 + fragment <<EOF 228 + --- binutils-2.23/ld/ldgram.y 229 + +++ binutils-2.23/ld/ldgram.y 230 + @@ -1119,6 +1119,8 @@ phdr_type: 231 + $$ = exp_intop (0x6474e550); 232 + else if (strcmp (s, "PT_GNU_STACK") == 0) 233 + $$ = exp_intop (0x6474e551); 234 + + else if (strcmp (s, "PT_PAX_FLAGS") == 0) 235 + + $$ = exp_intop (0x65041580); 236 + else 237 + { 238 + einfo (_("\ 239 + --- binutils-2.23/ld/testsuite/ld-alpha/tlsbin.rd 240 + +++ binutils-2.23/ld/testsuite/ld-alpha/tlsbin.rd 241 + @@ -35,13 +35,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 242 + 243 + Program Headers: 244 + Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align 245 + - PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+150 R E 0x8 246 + + PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+188 R E 0x8 247 + INTERP +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1 248 + .*Requesting program interpreter.* 249 + LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000 250 + LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000 251 + DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8 252 + TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4 253 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 254 + #... 255 + 256 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries: 257 + --- binutils-2.23/ld/testsuite/ld-alpha/tlsbinr.rd 258 + +++ binutils-2.23/ld/testsuite/ld-alpha/tlsbinr.rd 259 + @@ -42,6 +42,7 @@ Program Headers: 260 + +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000 261 + +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8 262 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4 263 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 264 + #... 265 + 266 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: 267 + --- binutils-2.23/ld/testsuite/ld-alpha/tlspic.rd 268 + +++ binutils-2.23/ld/testsuite/ld-alpha/tlspic.rd 269 + @@ -38,6 +38,7 @@ Program Headers: 270 + +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000 271 + +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8 272 + +TLS +0x0+10e0 0x0+110e0 0x0+110e0 0x0+60 0x0+80 R +0x4 273 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 274 + #... 275 + 276 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 7 entries: 277 + --- binutils-2.23/ld/testsuite/ld-elf/eh1.d 278 + +++ binutils-2.23/ld/testsuite/ld-elf/eh1.d 279 + @@ -22,11 +22,11 @@ Contents of the .eh_frame section: 280 + DW_CFA_nop 281 + DW_CFA_nop 282 + 283 + -00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078 284 + - DW_CFA_advance_loc: 0 to 00400078 285 + +00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1 286 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 287 + DW_CFA_def_cfa_offset: 16 288 + DW_CFA_offset: r6 \(rbp\) at cfa-16 289 + - DW_CFA_advance_loc: 0 to 00400078 290 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 291 + DW_CFA_def_cfa_register: r6 \(rbp\) 292 + 293 + 00000038 ZERO terminator 294 + --- binutils-2.23/ld/testsuite/ld-elf/eh2.d 295 + +++ binutils-2.23/ld/testsuite/ld-elf/eh2.d 296 + @@ -22,11 +22,11 @@ Contents of the .eh_frame section: 297 + DW_CFA_nop 298 + DW_CFA_nop 299 + 300 + -00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078 301 + - DW_CFA_advance_loc: 0 to 00400078 302 + +00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1 303 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 304 + DW_CFA_def_cfa_offset: 16 305 + DW_CFA_offset: r6 \(rbp\) at cfa-16 306 + - DW_CFA_advance_loc: 0 to 00400078 307 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 308 + DW_CFA_def_cfa_register: r6 \(rbp\) 309 + 310 + 00000038 ZERO terminator 311 + --- binutils-2.23/ld/testsuite/ld-elf/eh3.d 312 + +++ binutils-2.23/ld/testsuite/ld-elf/eh3.d 313 + @@ -22,11 +22,11 @@ Contents of the .eh_frame section: 314 + DW_CFA_nop 315 + DW_CFA_nop 316 + 317 + -00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078 318 + - DW_CFA_advance_loc: 0 to 00400078 319 + +00000018 0000001c 0000001c FDE cie=00000000 pc=([0-9a-f]+)..\1 320 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 321 + DW_CFA_def_cfa_offset: 16 322 + DW_CFA_offset: r6 \(rbp\) at cfa-16 323 + - DW_CFA_advance_loc: 0 to 00400078 324 + + DW_CFA_advance_loc: 0 to [0-9a-f]+ 325 + DW_CFA_def_cfa_register: r6 \(rbp\) 326 + 327 + 00000038 ZERO terminator 328 + --- binutils-2.23/ld/testsuite/ld-elf/orphan-region.d 329 + +++ binutils-2.23/ld/testsuite/ld-elf/orphan-region.d 330 + @@ -15,7 +15,9 @@ 331 + Program Headers: 332 + Type.* 333 + LOAD[ \t]+0x[0-9a-f]+ 0x0*40000000 0x0*40000000 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x[0-9a-f]+ 334 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 335 + 336 + Section to Segment mapping: 337 + Segment Sections... 338 + 00 .text .rodata .moredata * 339 + + 01 + 340 + --- binutils-2.23/ld/testsuite/ld-i386/tlsbin.rd 341 + +++ binutils-2.23/ld/testsuite/ld-i386/tlsbin.rd 342 + @@ -44,6 +44,7 @@ Program Headers: 343 + +LOAD.* 344 + +DYNAMIC.* 345 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000 346 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 347 + 348 + Section to Segment mapping: 349 + +Segment Sections... 350 + @@ -53,6 +54,7 @@ Program Headers: 351 + +03 +.tdata .dynamic .got .got.plt * 352 + +04 +.dynamic * 353 + +05 +.tdata .tbss * 354 + + +06 + 355 + 356 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries: 357 + Offset +Info +Type +Sym.Value +Sym. Name 358 + --- binutils-2.23/ld/testsuite/ld-i386/tlsbindesc.rd 359 + +++ binutils-2.23/ld/testsuite/ld-i386/tlsbindesc.rd 360 + @@ -42,6 +42,7 @@ Program Headers: 361 + +LOAD.* 362 + +DYNAMIC.* 363 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000 364 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 365 + 366 + Section to Segment mapping: 367 + +Segment Sections... 368 + @@ -51,6 +52,7 @@ Program Headers: 369 + +03 +.tdata .dynamic .got .got.plt * 370 + +04 +.dynamic * 371 + +05 +.tdata .tbss * 372 + + +06 + 373 + 374 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries: 375 + Offset +Info +Type +Sym.Value +Sym. Name 376 + --- binutils-2.23/ld/testsuite/ld-i386/tlsdesc.rd 377 + +++ binutils-2.23/ld/testsuite/ld-i386/tlsdesc.rd 378 + @@ -39,6 +39,7 @@ Program Headers: 379 + +LOAD.* 380 + +DYNAMIC.* 381 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1 382 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 383 + 384 + Section to Segment mapping: 385 + +Segment Sections... 386 + @@ -46,6 +47,7 @@ Program Headers: 387 + +01 +.tdata .dynamic .got .got.plt * 388 + +02 +.dynamic * 389 + +03 +.tdata .tbss * 390 + + +04 + 391 + 392 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries: 393 + Offset +Info +Type +Sym.Value +Sym. Name 394 + --- binutils-2.23/ld/testsuite/ld-i386/tlsgdesc.rd 395 + +++ binutils-2.23/ld/testsuite/ld-i386/tlsgdesc.rd 396 + @@ -36,12 +36,14 @@ Program Headers: 397 + +LOAD.* 398 + +LOAD.* 399 + +DYNAMIC.* 400 + + +PAX_FLAGS.* 401 + 402 + Section to Segment mapping: 403 + +Segment Sections... 404 + +00 +.hash .dynsym .dynstr .rel.dyn .rel.plt .plt .text * 405 + +01 +.dynamic .got .got.plt * 406 + +02 +.dynamic * 407 + + +03 + 408 + 409 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 8 entries: 410 + Offset +Info +Type +Sym.Value +Sym. Name 411 + --- binutils-2.23/ld/testsuite/ld-i386/tlsnopic.rd 412 + +++ binutils-2.23/ld/testsuite/ld-i386/tlsnopic.rd 413 + @@ -37,6 +37,7 @@ Program Headers: 414 + +LOAD.* 415 + +DYNAMIC.* 416 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+ 0x0+24 R +0x1 417 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 418 + 419 + Section to Segment mapping: 420 + +Segment Sections... 421 + @@ -44,6 +45,7 @@ Program Headers: 422 + +01 +.dynamic .got .got.plt * 423 + +02 +.dynamic * 424 + +03 +.tbss * 425 + + +04 + 426 + 427 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries: 428 + Offset +Info +Type +Sym.Value +Sym. Name 429 + --- binutils-2.23/ld/testsuite/ld-i386/tlspic.rd 430 + +++ binutils-2.23/ld/testsuite/ld-i386/tlspic.rd 431 + @@ -40,6 +40,7 @@ Program Headers: 432 + +LOAD.* 433 + +DYNAMIC.* 434 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1 435 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 436 + 437 + Section to Segment mapping: 438 + +Segment Sections... 439 + @@ -47,6 +48,7 @@ Program Headers: 440 + +01 +.tdata .dynamic .got .got.plt * 441 + +02 +.dynamic * 442 + +03 +.tdata .tbss * 443 + + +04 + 444 + 445 + Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 26 entries: 446 + Offset +Info +Type +Sym.Value +Sym. Name 447 + --- binutils-2.23/ld/testsuite/ld-ia64/merge1.d 448 + +++ binutils-2.23/ld/testsuite/ld-ia64/merge1.d 449 + @@ -4,7 +4,7 @@ 450 + #objdump: -d 451 + 452 + #... 453 + -0+1e0 <.text>: 454 + +[a-f0-9]+ <.text>: 455 + [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;; 456 + [ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=24,r1 457 + [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; 458 + --- binutils-2.23/ld/testsuite/ld-ia64/merge2.d 459 + +++ binutils-2.23/ld/testsuite/ld-ia64/merge2.d 460 + @@ -4,7 +4,7 @@ 461 + #objdump: -d 462 + 463 + #... 464 + -0+1e0 <.text>: 465 + +[a-f0-9]+ <.text>: 466 + [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;; 467 + [ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=24,r1 468 + [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; 469 + --- binutils-2.23/ld/testsuite/ld-ia64/merge3.d 470 + +++ binutils-2.23/ld/testsuite/ld-ia64/merge3.d 471 + @@ -4,7 +4,7 @@ 472 + #objdump: -d 473 + 474 + #... 475 + -0+210 <.text>: 476 + +[a-f0-9]+ <.text>: 477 + [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;; 478 + [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1 479 + [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; 480 + --- binutils-2.23/ld/testsuite/ld-ia64/merge4.d 481 + +++ binutils-2.23/ld/testsuite/ld-ia64/merge4.d 482 + @@ -4,7 +4,7 @@ 483 + #objdump: -d 484 + 485 + #... 486 + -0+240 <.text>: 487 + +[a-f0-9]+ <.text>: 488 + [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;; 489 + [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1 490 + [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; 491 + --- binutils-2.23/ld/testsuite/ld-ia64/merge5.d 492 + +++ binutils-2.23/ld/testsuite/ld-ia64/merge5.d 493 + @@ -4,7 +4,7 @@ 494 + #objdump: -d 495 + 496 + #... 497 + -0+270 <.text>: 498 + +[a-f0-9]+ <.text>: 499 + [ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=32,r1;; 500 + [ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=40,r1 501 + [ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; 502 + --- binutils-2.23/ld/testsuite/ld-ia64/tlsbin.rd 503 + +++ binutils-2.23/ld/testsuite/ld-ia64/tlsbin.rd 504 + @@ -36,13 +36,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 505 + 506 + Program Headers: 507 + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align 508 + - +PHDR +0x0+40 0x40+40 0x40+40 0x0+188 0x0+188 R E 0x8 509 + - +INTERP +0x0+1c8 0x40+1c8 0x40+1c8 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1 510 + + +PHDR +0x0+40 0x40+40 0x40+40 (0x[0-9a-f]+) \1 R E 0x8 511 + + +INTERP +0x0+([0-9a-f]+) (0x40+\1) \2 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1 512 + .*Requesting program interpreter.* 513 + +LOAD +0x0+ 0x40+ 0x40+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000 514 + +LOAD +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000 515 + +DYNAMIC +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+150 0x0+150 RW +0x8 516 + +TLS +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+60 0x0+a0 R +0x4 517 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 518 + +IA_64_UNWIND .* R +0x8 519 + #... 520 + 521 + --- binutils-2.23/ld/testsuite/ld-ia64/tlspic.rd 522 + +++ binutils-2.23/ld/testsuite/ld-ia64/tlspic.rd 523 + @@ -40,6 +40,7 @@ Program Headers: 524 + +LOAD +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000 525 + +DYNAMIC +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+140 0x0+140 RW +0x8 526 + +TLS +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+60 0x0+80 R +0x4 527 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 528 + +IA_64_UNWIND +0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+18 0x0+18 R +0x8 529 + #... 530 + 531 + --- binutils-2.23/ld/testsuite/ld-mips-elf/multi-got-no-shared.d 532 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/multi-got-no-shared.d 533 + @@ -8,9 +8,9 @@ 534 + .*: +file format.* 535 + 536 + Disassembly of section \.text: 537 + -004000b0 <[^>]*> 3c1c0043 lui gp,0x43 538 + -004000b4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 539 + -004000b8 <[^>]*> afbc0008 sw gp,8\(sp\) 540 + +004000d0 <[^>]*> 3c1c0043 lui gp,0x43 541 + +004000d4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 542 + +004000d8 <[^>]*> afbc0008 sw gp,8\(sp\) 543 + #... 544 + 00408d60 <[^>]*> 3c1c0043 lui gp,0x43 545 + 00408d64 <[^>]*> 279c2c98 addiu gp,gp,11416 546 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd 547 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd 548 + @@ -1,7 +1,7 @@ 549 + 550 + Elf file type is DYN \(Shared object file\) 551 + Entry point .* 552 + -There are 5 program headers, starting at offset .* 553 + +There are [0-9] program headers, starting at offset .* 554 + 555 + Program Headers: 556 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 557 + @@ -9,6 +9,7 @@ Program Headers: 558 + * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.* 559 + * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW * 0x.* 560 + * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .* 561 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 562 + * NULL * .* 563 + 564 + *Section to Segment mapping: 565 + @@ -18,3 +19,4 @@ Program Headers: 566 + *0*2 * \.data \.got * 567 + *0*3 * \.dynamic * 568 + *0*4 * 569 + + *0*5 * 570 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd 571 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd 572 + @@ -1,7 +1,7 @@ 573 + 574 + Elf file type is EXEC \(Executable file\) 575 + Entry point 0x44000 576 + -There are 8 program headers, starting at offset .* 577 + +There are [0-9] program headers, starting at offset .* 578 + 579 + Program Headers: 580 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 581 + @@ -13,6 +13,7 @@ Program Headers: 582 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 583 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 584 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 585 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 586 + * NULL * .* 587 + 588 + *Section to Segment mapping: 589 + @@ -25,3 +26,4 @@ Program Headers: 590 + *0*5 *\.got \.data * 591 + *0*6 *\.dynamic * 592 + *0*7 * 593 + + *0*8 * 594 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd 595 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd 596 + @@ -1,7 +1,7 @@ 597 + 598 + Elf file type is EXEC \(Executable file\) 599 + Entry point 0x44000 600 + -There are 8 program headers, starting at offset .* 601 + +There are [0-9] program headers, starting at offset .* 602 + 603 + Program Headers: 604 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 605 + @@ -13,6 +13,7 @@ Program Headers: 606 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 607 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 608 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 609 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 610 + * NULL * .* 611 + 612 + *Section to Segment mapping: 613 + @@ -25,3 +26,4 @@ Program Headers: 614 + *0*5 * \.got \.data \.bss * 615 + *0*6 * \.dynamic * 616 + *0*7 * 617 + + *0*8 * 618 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd 619 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd 620 + @@ -1,7 +1,7 @@ 621 + 622 + Elf file type is EXEC \(Executable file\) 623 + Entry point 0x44000 624 + -There are 8 program headers, starting at offset .* 625 + +There are [0-9] program headers, starting at offset .* 626 + 627 + Program Headers: 628 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 629 + @@ -13,6 +13,7 @@ Program Headers: 630 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 631 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 632 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 633 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 634 + * NULL * .* 635 + 636 + *Section to Segment mapping: 637 + @@ -25,3 +26,4 @@ Program Headers: 638 + *0*5 * \.got \.data \.bss * 639 + *0*6 * \.dynamic * 640 + *0*7 * 641 + + *0*8 * 642 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd 643 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd 644 + @@ -1,7 +1,7 @@ 645 + 646 + Elf file type is EXEC \(Executable file\) 647 + Entry point 0x44000 648 + -There are 8 program headers, starting at offset .* 649 + +There are [0-9] program headers, starting at offset .* 650 + 651 + Program Headers: 652 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 653 + @@ -13,6 +13,7 @@ Program Headers: 654 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 655 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 656 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 657 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 658 + * NULL * .* 659 + 660 + *Section to Segment mapping: 661 + @@ -25,3 +26,4 @@ Program Headers: 662 + *0*5 * \.got \.data \.bss * 663 + *0*6 * \.dynamic * 664 + *0*7 * 665 + + *0*8 * 666 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd 667 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd 668 + @@ -1,7 +1,7 @@ 669 + 670 + Elf file type is EXEC \(Executable file\) 671 + Entry point 0x44000 672 + -There are 7 program headers, starting at offset .* 673 + +There are [0-9] program headers, starting at offset .* 674 + 675 + Program Headers: 676 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 677 + @@ -12,6 +12,7 @@ Program Headers: 678 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 679 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 680 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 681 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 682 + * NULL * .* 683 + 684 + *Section to Segment mapping: 685 + @@ -23,3 +24,4 @@ Program Headers: 686 + *0*4 * \.got \.data \.bss * 687 + *0*5 * \.dynamic * 688 + *0*6 * 689 + + *0*7 * 690 + --- binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd 691 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd 692 + @@ -1,7 +1,7 @@ 693 + 694 + Elf file type is EXEC \(Executable file\) 695 + Entry point 0x44000 696 + -There are 8 program headers, starting at offset .* 697 + +There are [0-9] program headers, starting at offset .* 698 + 699 + Program Headers: 700 + * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align 701 + @@ -13,6 +13,7 @@ Program Headers: 702 + * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW * 0x.* 703 + * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW * 0x.* 704 + * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .* 705 + + * PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 706 + * NULL * .* 707 + 708 + *Section to Segment mapping: 709 + @@ -25,3 +26,4 @@ Program Headers: 710 + *0*5 * \.got \.data \.bss * 711 + *0*6 * \.dynamic * 712 + *0*7 * 713 + + *0*8 * 714 + --- binutils-2.23/ld/testsuite/ld-mips-elf/tlsbin-o32.d 715 + +++ binutils-2.23/ld/testsuite/ld-mips-elf/tlsbin-o32.d 716 + @@ -2,42 +2,42 @@ 717 + 718 + Disassembly of section .text: 719 + 720 + -004000d0 <__start>: 721 + - 4000d0: 3c1c0fc0 lui gp,0xfc0 722 + - 4000d4: 279c7f30 addiu gp,gp,32560 723 + - 4000d8: 0399e021 addu gp,gp,t9 724 + - 4000dc: 27bdfff0 addiu sp,sp,-16 725 + - 4000e0: afbe0008 sw s8,8\(sp\) 726 + - 4000e4: 03a0f021 move s8,sp 727 + - 4000e8: afbc0000 sw gp,0\(sp\) 728 + - 4000ec: 8f998018 lw t9,-32744\(gp\) 729 + - 4000f0: 27848028 addiu a0,gp,-32728 730 + - 4000f4: 0320f809 jalr t9 731 + - 4000f8: 00000000 nop 732 + - 4000fc: 8fdc0000 lw gp,0\(s8\) 733 + - 400100: 00000000 nop 734 + - 400104: 8f998018 lw t9,-32744\(gp\) 735 + - 400108: 27848020 addiu a0,gp,-32736 736 + - 40010c: 0320f809 jalr t9 737 + - 400110: 00000000 nop 738 + - 400114: 8fdc0000 lw gp,0\(s8\) 739 + - 400118: 00401021 move v0,v0 740 + - 40011c: 3c030000 lui v1,0x0 741 + - 400120: 24638000 addiu v1,v1,-32768 742 + - 400124: 00621821 addu v1,v1,v0 743 + - 400128: 7c02283b rdhwr v0,\$5 744 + - 40012c: 8f83801c lw v1,-32740\(gp\) 745 + - 400130: 00000000 nop 746 + - 400134: 00621821 addu v1,v1,v0 747 + - 400138: 7c02283b rdhwr v0,\$5 748 + - 40013c: 3c030000 lui v1,0x0 749 + - 400140: 24639004 addiu v1,v1,-28668 750 + - 400144: 00621821 addu v1,v1,v0 751 + - 400148: 03c0e821 move sp,s8 752 + - 40014c: 8fbe0008 lw s8,8\(sp\) 753 + - 400150: 03e00008 jr ra 754 + - 400154: 27bd0010 addiu sp,sp,16 755 + +00400[0-9a-f]{3} <__start>: 756 + + 400[0-9a-f]{3}: 3c1c0fc0 lui gp,0xfc0 757 + + 400[0-9a-f]{3}: 279c7f30 addiu gp,gp,32560 758 + + 400[0-9a-f]{3}: 0399e021 addu gp,gp,t9 759 + + 400[0-9a-f]{3}: 27bdfff0 addiu sp,sp,-16 760 + + 400[0-9a-f]{3}: afbe0008 sw s8,8\(sp\) 761 + + 400[0-9a-f]{3}: 03a0f021 move s8,sp 762 + + 400[0-9a-f]{3}: afbc0000 sw gp,0\(sp\) 763 + + 400[0-9a-f]{3}: 8f998018 lw t9,-32744\(gp\) 764 + + 400[0-9a-f]{3}: 27848028 addiu a0,gp,-32728 765 + + 400[0-9a-f]{3}: 0320f809 jalr t9 766 + + 400[0-9a-f]{3}: 00000000 nop 767 + + 400[0-9a-f]{3}: 8fdc0000 lw gp,0\(s8\) 768 + + 400[0-9a-f]{3}: 00000000 nop 769 + + 400[0-9a-f]{3}: 8f998018 lw t9,-32744\(gp\) 770 + + 400[0-9a-f]{3}: 27848020 addiu a0,gp,-32736 771 + + 400[0-9a-f]{3}: 0320f809 jalr t9 772 + + 400[0-9a-f]{3}: 00000000 nop 773 + + 400[0-9a-f]{3}: 8fdc0000 lw gp,0\(s8\) 774 + + 400[0-9a-f]{3}: 00401021 move v0,v0 775 + + 400[0-9a-f]{3}: 3c030000 lui v1,0x0 776 + + 400[0-9a-f]{3}: 24638000 addiu v1,v1,-32768 777 + + 400[0-9a-f]{3}: 00621821 addu v1,v1,v0 778 + + 400[0-9a-f]{3}: 7c02283b rdhwr v0,\$5 779 + + 400[0-9a-f]{3}: 8f83801c lw v1,-32740\(gp\) 780 + + 400[0-9a-f]{3}: 00000000 nop 781 + + 400[0-9a-f]{3}: 00621821 addu v1,v1,v0 782 + + 400[0-9a-f]{3}: 7c02283b rdhwr v0,\$5 783 + + 400[0-9a-f]{3}: 3c030000 lui v1,0x0 784 + + 400[0-9a-f]{3}: 24639004 addiu v1,v1,-28668 785 + + 400[0-9a-f]{3}: 00621821 addu v1,v1,v0 786 + + 400[0-9a-f]{3}: 03c0e821 move sp,s8 787 + + 400[0-9a-f]{3}: 8fbe0008 lw s8,8\(sp\) 788 + + 400[0-9a-f]{3}: 03e00008 jr ra 789 + + 400[0-9a-f]{3}: 27bd0010 addiu sp,sp,16 790 + 791 + -00400158 <__tls_get_addr>: 792 + - 400158: 03e00008 jr ra 793 + - 40015c: 00000000 nop 794 + +00400[0-9a-f]{3} <__tls_get_addr>: 795 + + 400[0-9a-f]{3}: 03e00008 jr ra 796 + + 400[0-9a-f]{3}: 00000000 nop 797 + --- binutils-2.23/ld/testsuite/ld-powerpc/tls.d 798 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tls.d 799 + @@ -9,45 +9,45 @@ 800 + 801 + Disassembly of section \.text: 802 + 803 + -0+100000e8 <_start>: 804 + - 100000e8: 3c 6d 00 00 addis r3,r13,0 805 + - 100000ec: 60 00 00 00 nop 806 + - 100000f0: 38 63 90 78 addi r3,r3,-28552 807 + - 100000f4: 3c 6d 00 00 addis r3,r13,0 808 + - 100000f8: 60 00 00 00 nop 809 + - 100000fc: 38 63 10 00 addi r3,r3,4096 810 + - 10000100: 3c 6d 00 00 addis r3,r13,0 811 + - 10000104: 60 00 00 00 nop 812 + - 10000108: 38 63 90 40 addi r3,r3,-28608 813 + - 1000010c: 3c 6d 00 00 addis r3,r13,0 814 + - 10000110: 60 00 00 00 nop 815 + - 10000114: 38 63 10 00 addi r3,r3,4096 816 + - 10000118: 39 23 80 48 addi r9,r3,-32696 817 + - 1000011c: 3d 23 00 00 addis r9,r3,0 818 + - 10000120: 81 49 80 50 lwz r10,-32688\(r9\) 819 + - 10000124: e9 22 80 10 ld r9,-32752\(r2\) 820 + - 10000128: 7d 49 18 2a ldx r10,r9,r3 821 + - 1000012c: 3d 2d 00 00 addis r9,r13,0 822 + - 10000130: a1 49 90 60 lhz r10,-28576\(r9\) 823 + - 10000134: 89 4d 90 68 lbz r10,-28568\(r13\) 824 + - 10000138: 3d 2d 00 00 addis r9,r13,0 825 + - 1000013c: 99 49 90 70 stb r10,-28560\(r9\) 826 + - 10000140: 3c 6d 00 00 addis r3,r13,0 827 + - 10000144: 60 00 00 00 nop 828 + - 10000148: 38 63 90 00 addi r3,r3,-28672 829 + - 1000014c: 3c 6d 00 00 addis r3,r13,0 830 + - 10000150: 60 00 00 00 nop 831 + - 10000154: 38 63 10 00 addi r3,r3,4096 832 + - 10000158: f9 43 80 08 std r10,-32760\(r3\) 833 + - 1000015c: 3d 23 00 00 addis r9,r3,0 834 + - 10000160: 91 49 80 10 stw r10,-32752\(r9\) 835 + - 10000164: e9 22 80 08 ld r9,-32760\(r2\) 836 + - 10000168: 7d 49 19 2a stdx r10,r9,r3 837 + - 1000016c: 3d 2d 00 00 addis r9,r13,0 838 + - 10000170: b1 49 90 60 sth r10,-28576\(r9\) 839 + - 10000174: e9 4d 90 2a lwa r10,-28632\(r13\) 840 + - 10000178: 3d 2d 00 00 addis r9,r13,0 841 + - 1000017c: a9 49 90 30 lha r10,-28624\(r9\) 842 + +0+10000[0-9a-f]{3} <_start>: 843 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 844 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 845 + + 10000[0-9a-f]{3}: 38 63 90 78 addi r3,r3,-28552 846 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 847 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 848 + + 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 849 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 850 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 851 + + 10000[0-9a-f]{3}: 38 63 90 40 addi r3,r3,-28608 852 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 853 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 854 + + 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 855 + + 10000[0-9a-f]{3}: 39 23 80 48 addi r9,r3,-32696 856 + + 10000[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0 857 + + 10000[0-9a-f]{3}: 81 49 80 50 lwz r10,-32688\(r9\) 858 + + 10000[0-9a-f]{3}: e9 22 80 10 ld r9,-32752\(r2\) 859 + + 10000[0-9a-f]{3}: 7d 49 18 2a ldx r10,r9,r3 860 + + 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0 861 + + 10000[0-9a-f]{3}: a1 49 90 60 lhz r10,-28576\(r9\) 862 + + 10000[0-9a-f]{3}: 89 4d 90 68 lbz r10,-28568\(r13\) 863 + + 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0 864 + + 10000[0-9a-f]{3}: 99 49 90 70 stb r10,-28560\(r9\) 865 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 866 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 867 + + 10000[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672 868 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 869 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 870 + + 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 871 + + 10000[0-9a-f]{3}: f9 43 80 08 std r10,-32760\(r3\) 872 + + 10000[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0 873 + + 10000[0-9a-f]{3}: 91 49 80 10 stw r10,-32752\(r9\) 874 + + 10000[0-9a-f]{3}: e9 22 80 08 ld r9,-32760\(r2\) 875 + + 10000[0-9a-f]{3}: 7d 49 19 2a stdx r10,r9,r3 876 + + 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0 877 + + 10000[0-9a-f]{3}: b1 49 90 60 sth r10,-28576\(r9\) 878 + + 10000[0-9a-f]{3}: e9 4d 90 2a lwa r10,-28632\(r13\) 879 + + 10000[0-9a-f]{3}: 3d 2d 00 00 addis r9,r13,0 880 + + 10000[0-9a-f]{3}: a9 49 90 30 lha r10,-28624\(r9\) 881 + 882 + -0+10000180 <\.__tls_get_addr>: 883 + - 10000180: 4e 80 00 20 blr 884 + +0+10000[0-9a-f]{3} <\.__tls_get_addr>: 885 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 886 + --- binutils-2.23/ld/testsuite/ld-powerpc/tls.g 887 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tls.g 888 + @@ -8,5 +8,5 @@ 889 + .*: +file format elf64-powerpc 890 + 891 + Contents of section \.got: 892 + - 100101e0 00000000 100181e0 ffffffff ffff8018 .* 893 + - 100101f0 ffffffff ffff8058 .* 894 + + 10010([0-9a-f]{3}) 00000000 10018\1 ffffffff ffff8018 .* 895 + + 10010[0-9a-f]{3} ffffffff ffff8058 .* 896 + --- binutils-2.23/ld/testsuite/ld-powerpc/tls32.d 897 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tls32.d 898 + @@ -9,42 +9,42 @@ 899 + 900 + Disassembly of section \.text: 901 + 902 + -0+1800094 <_start>: 903 + - 1800094: 3c 62 00 00 addis r3,r2,0 904 + - 1800098: 38 63 90 3c addi r3,r3,-28612 905 + - 180009c: 3c 62 00 00 addis r3,r2,0 906 + - 18000a0: 38 63 10 00 addi r3,r3,4096 907 + - 18000a4: 3c 62 00 00 addis r3,r2,0 908 + - 18000a8: 38 63 90 20 addi r3,r3,-28640 909 + - 18000ac: 3c 62 00 00 addis r3,r2,0 910 + - 18000b0: 38 63 10 00 addi r3,r3,4096 911 + - 18000b4: 39 23 80 24 addi r9,r3,-32732 912 + - 18000b8: 3d 23 00 00 addis r9,r3,0 913 + - 18000bc: 81 49 80 28 lwz r10,-32728\(r9\) 914 + - 18000c0: 3d 22 00 00 addis r9,r2,0 915 + - 18000c4: a1 49 90 30 lhz r10,-28624\(r9\) 916 + - 18000c8: 89 42 90 34 lbz r10,-28620\(r2\) 917 + - 18000cc: 3d 22 00 00 addis r9,r2,0 918 + - 18000d0: 99 49 90 38 stb r10,-28616\(r9\) 919 + - 18000d4: 3c 62 00 00 addis r3,r2,0 920 + - 18000d8: 38 63 90 00 addi r3,r3,-28672 921 + - 18000dc: 3c 62 00 00 addis r3,r2,0 922 + - 18000e0: 38 63 10 00 addi r3,r3,4096 923 + - 18000e4: 91 43 80 04 stw r10,-32764\(r3\) 924 + - 18000e8: 3d 23 00 00 addis r9,r3,0 925 + - 18000ec: 91 49 80 08 stw r10,-32760\(r9\) 926 + - 18000f0: 3d 22 00 00 addis r9,r2,0 927 + - 18000f4: b1 49 90 30 sth r10,-28624\(r9\) 928 + - 18000f8: a1 42 90 14 lhz r10,-28652\(r2\) 929 + - 18000fc: 3d 22 00 00 addis r9,r2,0 930 + - 1800100: a9 49 90 18 lha r10,-28648\(r9\) 931 + +0+1800[0-9a-f]{3} <_start>: 932 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 933 + + 1800[0-9a-f]{3}: 38 63 90 3c addi r3,r3,-28612 934 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 935 + + 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 936 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 937 + + 1800[0-9a-f]{3}: 38 63 90 20 addi r3,r3,-28640 938 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 939 + + 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 940 + + 1800[0-9a-f]{3}: 39 23 80 24 addi r9,r3,-32732 941 + + 1800[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0 942 + + 1800[0-9a-f]{3}: 81 49 80 28 lwz r10,-32728\(r9\) 943 + + 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0 944 + + 1800[0-9a-f]{3}: a1 49 90 30 lhz r10,-28624\(r9\) 945 + + 1800[0-9a-f]{3}: 89 42 90 34 lbz r10,-28620\(r2\) 946 + + 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0 947 + + 1800[0-9a-f]{3}: 99 49 90 38 stb r10,-28616\(r9\) 948 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 949 + + 1800[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672 950 + + 1800[0-9a-f]{3}: 3c 62 00 00 addis r3,r2,0 951 + + 1800[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 952 + + 1800[0-9a-f]{3}: 91 43 80 04 stw r10,-32764\(r3\) 953 + + 1800[0-9a-f]{3}: 3d 23 00 00 addis r9,r3,0 954 + + 1800[0-9a-f]{3}: 91 49 80 08 stw r10,-32760\(r9\) 955 + + 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0 956 + + 1800[0-9a-f]{3}: b1 49 90 30 sth r10,-28624\(r9\) 957 + + 1800[0-9a-f]{3}: a1 42 90 14 lhz r10,-28652\(r2\) 958 + + 1800[0-9a-f]{3}: 3d 22 00 00 addis r9,r2,0 959 + + 1800[0-9a-f]{3}: a9 49 90 18 lha r10,-28648\(r9\) 960 + 961 + -0+1800104 <__tls_get_addr>: 962 + - 1800104: 4e 80 00 20 blr 963 + +0+1800[0-9a-f]{3} <__tls_get_addr>: 964 + + 1800[0-9a-f]{3}: 4e 80 00 20 blr 965 + Disassembly of section \.got: 966 + 967 + -0+1810128 <_GLOBAL_OFFSET_TABLE_-0x4>: 968 + - 1810128: 4e 80 00 21 blrl 969 + +0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_-0x4>: 970 + + 1810[0-9a-f]{3}: 4e 80 00 21 blrl 971 + 972 + -0+181012c <_GLOBAL_OFFSET_TABLE_>: 973 + +0+1810[0-9a-f]{3} <_GLOBAL_OFFSET_TABLE_>: 974 + \.\.\. 975 + --- binutils-2.23/ld/testsuite/ld-powerpc/tls32.g 976 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tls32.g 977 + @@ -8,4 +8,4 @@ 978 + .*: +file format elf32-powerpc 979 + 980 + Contents of section \.got: 981 + - 1810128 4e800021 00000000 00000000 00000000 .* 982 + + 18101[0-9a-f]{2} 4e800021 00000000 00000000 00000000 .* 983 + --- binutils-2.23/ld/testsuite/ld-powerpc/tls32.t 984 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tls32.t 985 + @@ -8,5 +8,5 @@ 986 + .*: +file format elf32-powerpc 987 + 988 + Contents of section \.tdata: 989 + - 1810108 12345678 23456789 3456789a 456789ab .* 990 + - 1810118 56789abc 6789abcd 789abcde 00c0ffee .* 991 + + 18101[0-9a-f]{2} 12345678 23456789 3456789a 456789ab .* 992 + + 18101[0-9a-f]{2} 56789abc 6789abcd 789abcde 00c0ffee .* 993 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.d 994 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.d 995 + @@ -44,4 +44,4 @@ Disassembly of section \.got: 996 + .*: 4e 80 00 21 blrl 997 + 998 + .* <_GLOBAL_OFFSET_TABLE_>: 999 + -.*: 01 81 02 b8 00 00 00 00 00 00 00 00 .* 1000 + +.*: 01 81 02 [bd]8 00 00 00 00 00 00 00 00 .* 1001 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.g 1002 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.g 1003 + @@ -8,4 +8,4 @@ 1004 + 1005 + Contents of section \.got: 1006 + .* 00000000 00000000 00000000 4e800021 .* 1007 + -.* 018102b8 00000000 00000000 .* 1008 + +.* 018102[bd]8 00000000 00000000 .* 1009 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.r 1010 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsexe32.r 1011 + @@ -33,13 +33,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 1012 + 1013 + Program Headers: 1014 + +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align 1015 + - +PHDR +0x000034 0x01800034 0x01800034 0x000c0 0x000c0 R E 0x4 1016 + - +INTERP +0x0000f4 0x018000f4 0x018000f4 0x00011 0x00011 R +0x1 1017 + + +PHDR +0x000034 0x01800034 0x01800034 (0x000[0-9a-f]{2}) \1 R E 0x4 1018 + + +INTERP +0x000([0-9a-f]{3}) 0x01800\1 0x01800\1 0x00011 0x00011 R +0x1 1019 + +\[Requesting program interpreter: .*\] 1020 + +LOAD .* R E 0x10000 1021 + +LOAD .* RWE 0x10000 1022 + +DYNAMIC .* RW +0x4 1023 + +TLS .* 0x0001c 0x00038 R +0x4 1024 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1025 + 1026 + Section to Segment mapping: 1027 + +Segment Sections\.\.\. 1028 + @@ -49,6 +50,7 @@ Program Headers: 1029 + +03 +\.tdata \.dynamic \.got \.plt 1030 + +04 +\.dynamic 1031 + +05 +\.tdata \.tbss 1032 + + +06 + 1033 + 1034 + Relocation section '\.rela\.dyn' at offset .* contains 2 entries: 1035 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend 1036 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsmark.d 1037 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsmark.d 1038 + @@ -9,29 +9,29 @@ 1039 + 1040 + Disassembly of section \.text: 1041 + 1042 + -0+100000e8 <_start>: 1043 + - 100000e8: 48 00 00 18 b 10000100 <_start\+0x18> 1044 + - 100000ec: 60 00 00 00 nop 1045 + - 100000f0: 38 63 90 00 addi r3,r3,-28672 1046 + - 100000f4: e8 83 00 00 ld r4,0\(r3\) 1047 + - 100000f8: 3c 6d 00 00 addis r3,r13,0 1048 + - 100000fc: 48 00 00 0c b 10000108 <_start\+0x20> 1049 + - 10000100: 3c 6d 00 00 addis r3,r13,0 1050 + - 10000104: 4b ff ff e8 b 100000ec <_start\+0x4> 1051 + - 10000108: 60 00 00 00 nop 1052 + - 1000010c: 38 63 10 00 addi r3,r3,4096 1053 + - 10000110: e8 83 80 00 ld r4,-32768\(r3\) 1054 + - 10000114: 3c 6d 00 00 addis r3,r13,0 1055 + - 10000118: 48 00 00 0c b 10000124 <_start\+0x3c> 1056 + - 1000011c: 3c 6d 00 00 addis r3,r13,0 1057 + - 10000120: 48 00 00 14 b 10000134 <_start\+0x4c> 1058 + - 10000124: 60 00 00 00 nop 1059 + - 10000128: 38 63 90 04 addi r3,r3,-28668 1060 + - 1000012c: e8 a3 00 00 ld r5,0\(r3\) 1061 + - 10000130: 4b ff ff ec b 1000011c <_start\+0x34> 1062 + - 10000134: 60 00 00 00 nop 1063 + - 10000138: 38 63 10 00 addi r3,r3,4096 1064 + - 1000013c: e8 a3 80 04 ld r5,-32764\(r3\) 1065 + +0+10000[0-9a-f]{3} <_start>: 1066 + + 10000[0-9a-f]{3}: 48 00 00 18 b 10000[0-9a-f]{3} <_start\+0x18> 1067 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1068 + + 10000[0-9a-f]{3}: 38 63 90 00 addi r3,r3,-28672 1069 + + 10000[0-9a-f]{3}: e8 83 00 00 ld r4,0\(r3\) 1070 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1071 + + 10000[0-9a-f]{3}: 48 00 00 0c b 10000[0-9a-f]{3} <_start\+0x20> 1072 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1073 + + 10000[0-9a-f]{3}: 4b ff ff e8 b 10000[0-9a-f]{3} <_start\+0x4> 1074 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1075 + + 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 1076 + + 10000[0-9a-f]{3}: e8 83 80 00 ld r4,-32768\(r3\) 1077 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1078 + + 10000[0-9a-f]{3}: 48 00 00 0c b 10000[0-9a-f]{3} <_start\+0x3c> 1079 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1080 + + 10000[0-9a-f]{3}: 48 00 00 14 b 10000[0-9a-f]{3} <_start\+0x4c> 1081 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1082 + + 10000[0-9a-f]{3}: 38 63 90 04 addi r3,r3,-28668 1083 + + 10000[0-9a-f]{3}: e8 a3 00 00 ld r5,0\(r3\) 1084 + + 10000[0-9a-f]{3}: 4b ff ff ec b 10000[0-9a-f]{3} <_start\+0x34> 1085 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1086 + + 10000[0-9a-f]{3}: 38 63 10 00 addi r3,r3,4096 1087 + + 10000[0-9a-f]{3}: e8 a3 80 04 ld r5,-32764\(r3\) 1088 + 1089 + -0+10000140 <\.__tls_get_addr>: 1090 + - 10000140: 4e 80 00 20 blr 1091 + +0+10000[0-9a-f]{3} <\.__tls_get_addr>: 1092 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 1093 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsmark32.d 1094 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsmark32.d 1095 + @@ -9,17 +9,17 @@ 1096 + 1097 + Disassembly of section \.text: 1098 + 1099 + -0+1800094 <_start>: 1100 + - 1800094: 48 00 00 14 b 18000a8 <_start\+0x14> 1101 + - 1800098: 38 63 90 00 addi r3,r3,-28672 1102 + - 180009c: 80 83 00 00 lwz r4,0\(r3\) 1103 + - 18000a0: 3c 62 00 00 addis r3,r2,0 1104 + - 18000a4: 48 00 00 0c b 18000b0 <_start\+0x1c> 1105 + - 18000a8: 3c 62 00 00 addis r3,r2,0 1106 + - 18000ac: 4b ff ff ec b 1800098 <_start\+0x4> 1107 + - 18000b0: 38 63 10 00 addi r3,r3,4096 1108 + - 18000b4: 80 83 80 00 lwz r4,-32768\(r3\) 1109 + +0+18000[0-9a-f]{2} <_start>: 1110 + + 18000[0-9a-f]{2}: 48 00 00 14 b 18000[0-9a-f]{2} <_start\+0x14> 1111 + + 18000[0-9a-f]{2}: 38 63 90 00 addi r3,r3,-28672 1112 + + 18000[0-9a-f]{2}: 80 83 00 00 lwz r4,0\(r3\) 1113 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1114 + + 18000[0-9a-f]{2}: 48 00 00 0c b 18000[0-9a-f]{2} <_start\+0x1c> 1115 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1116 + + 18000[0-9a-f]{2}: 4b ff ff ec b 18000[0-9a-f]{2} <_start\+0x4> 1117 + + 18000[0-9a-f]{2}: 38 63 10 00 addi r3,r3,4096 1118 + + 18000[0-9a-f]{2}: 80 83 80 00 lwz r4,-32768\(r3\) 1119 + 1120 + -0+18000b8 <__tls_get_addr>: 1121 + - 18000b8: 4e 80 00 20 blr 1122 + -#pass 1123 + \ No newline at end of file 1124 + +0+18000[0-9a-f]{2} <__tls_get_addr>: 1125 + + 18000[0-9a-f]{2}: 4e 80 00 20 blr 1126 + +#pass 1127 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt1.d 1128 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt1.d 1129 + @@ -9,17 +9,17 @@ 1130 + 1131 + Disassembly of section \.text: 1132 + 1133 + -0+100000e8 <\.__tls_get_addr>: 1134 + - 100000e8: 4e 80 00 20 blr 1135 + +0+10000[0-9a-f]{3} <\.__tls_get_addr>: 1136 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 1137 + 1138 + Disassembly of section \.no_opt1: 1139 + 1140 + -0+100000ec <\.no_opt1>: 1141 + - 100000ec: 38 62 80 08 addi r3,r2,-32760 1142 + - 100000f0: 2c 24 00 00 cmpdi r4,0 1143 + - 100000f4: 41 82 00 10 beq- .* 1144 + - 100000f8: 4b ff ff f1 bl 100000e8 <\.__tls_get_addr> 1145 + - 100000fc: 60 00 00 00 nop 1146 + - 10000100: 48 00 00 0c b .* 1147 + - 10000104: 4b ff ff e5 bl 100000e8 <\.__tls_get_addr> 1148 + - 10000108: 60 00 00 00 nop 1149 + +0+10000[0-9a-f]{3} <\.no_opt1>: 1150 + + 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760 1151 + + 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0 1152 + + 10000[0-9a-f]{3}: 41 82 00 10 beq- .* 1153 + + 10000[0-9a-f]{3}: 4b ff ff f1 bl 10000[0-9a-f]{3} <\.__tls_get_addr> 1154 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1155 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1156 + + 10000[0-9a-f]{3}: 4b ff ff e5 bl 10000[0-9a-f]{3} <\.__tls_get_addr> 1157 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1158 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt1_32.d 1159 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt1_32.d 1160 + @@ -9,16 +9,16 @@ 1161 + 1162 + Disassembly of section \.text: 1163 + 1164 + -0+1800094 <__tls_get_addr>: 1165 + - 1800094: 4e 80 00 20 blr 1166 + +0+18000[0-9a-f]{2} <__tls_get_addr>: 1167 + + 18000[0-9a-f]{2}: 4e 80 00 20 blr 1168 + 1169 + Disassembly of section \.no_opt1: 1170 + 1171 + -0+1800098 <\.no_opt1>: 1172 + - 1800098: 38 6d ff f4 addi r3,r13,-12 1173 + - 180009c: 2c 04 00 00 cmpwi r4,0 1174 + - 18000a0: 41 82 00 0c beq- .* 1175 + - 18000a4: 4b ff ff f1 bl 1800094 <__tls_get_addr> 1176 + - 18000a8: 48 00 00 08 b .* 1177 + - 18000ac: 4b ff ff e9 bl 1800094 <__tls_get_addr> 1178 + +0+18000[0-9a-f]{2} <\.no_opt1>: 1179 + + 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12 1180 + + 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0 1181 + + 18000[0-9a-f]{2}: 41 82 00 0c beq- .* 1182 + + 18000[0-9a-f]{2}: 4b ff ff f1 bl 18000[0-9a-f]{2} <__tls_get_addr> 1183 + + 18000[0-9a-f]{2}: 48 00 00 08 b .* 1184 + + 18000[0-9a-f]{2}: 4b ff ff e9 bl 18000[0-9a-f]{2} <__tls_get_addr> 1185 + #pass 1186 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt2.d 1187 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt2.d 1188 + @@ -9,15 +9,15 @@ 1189 + 1190 + Disassembly of section \.text: 1191 + 1192 + -0+100000e8 <\.__tls_get_addr>: 1193 + - 100000e8: 4e 80 00 20 blr 1194 + +0+10000[0-9a-f]{3} <\.__tls_get_addr>: 1195 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 1196 + 1197 + Disassembly of section \.no_opt2: 1198 + 1199 + -0+100000ec <\.no_opt2>: 1200 + - 100000ec: 38 62 80 08 addi r3,r2,-32760 1201 + - 100000f0: 2c 24 00 00 cmpdi r4,0 1202 + - 100000f4: 41 82 00 08 beq- .* 1203 + - 100000f8: 38 62 80 08 addi r3,r2,-32760 1204 + - 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr> 1205 + - 10000100: 60 00 00 00 nop 1206 + +0+10000[0-9a-f]{3} <\.no_opt2>: 1207 + + 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760 1208 + + 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0 1209 + + 10000[0-9a-f]{3}: 41 82 00 08 beq- .* 1210 + + 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760 1211 + + 10000[0-9a-f]{3}: 4b ff ff ed bl 10000[0-9a-f]{3} <\.__tls_get_addr> 1212 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1213 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt2_32.d 1214 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt2_32.d 1215 + @@ -9,15 +9,15 @@ 1216 + 1217 + Disassembly of section \.text: 1218 + 1219 + -0+1800094 <__tls_get_addr>: 1220 + - 1800094: 4e 80 00 20 blr 1221 + +0+18000[0-9a-f]{2} <__tls_get_addr>: 1222 + + 18000[0-9a-f]{2}: 4e 80 00 20 blr 1223 + 1224 + Disassembly of section \.no_opt2: 1225 + 1226 + -0+1800098 <\.no_opt2>: 1227 + - 1800098: 38 6d ff f4 addi r3,r13,-12 1228 + - 180009c: 2c 04 00 00 cmpwi r4,0 1229 + - 18000a0: 41 82 00 08 beq- .* 1230 + - 18000a4: 38 6d ff f4 addi r3,r13,-12 1231 + - 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr> 1232 + +0+18000[0-9a-f]{2} <\.no_opt2>: 1233 + + 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12 1234 + + 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0 1235 + + 18000[0-9a-f]{2}: 41 82 00 08 beq- .* 1236 + + 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12 1237 + + 18000[0-9a-f]{2}: 4b ff ff ed bl 18000[0-9a-f]{2} <__tls_get_addr> 1238 + #pass 1239 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt3.d 1240 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt3.d 1241 + @@ -9,18 +9,18 @@ 1242 + 1243 + Disassembly of section \.text: 1244 + 1245 + -00000000100000e8 <\.__tls_get_addr>: 1246 + - 100000e8: 4e 80 00 20 blr 1247 + +0000000010000[0-9a-f]{3} <\.__tls_get_addr>: 1248 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 1249 + 1250 + Disassembly of section \.no_opt3: 1251 + 1252 + -00000000100000ec <\.no_opt3>: 1253 + - 100000ec: 38 62 80 08 addi r3,r2,-32760 1254 + - 100000f0: 48 00 00 0c b .* 1255 + - 100000f4: 38 62 80 18 addi r3,r2,-32744 1256 + - 100000f8: 48 00 00 10 b .* 1257 + - 100000fc: 4b ff ff ed bl 100000e8 <\.__tls_get_addr> 1258 + - 10000100: 60 00 00 00 nop 1259 + - 10000104: 48 00 00 0c b .* 1260 + - 10000108: 4b ff ff e1 bl 100000e8 <\.__tls_get_addr> 1261 + - 1000010c: 60 00 00 00 nop 1262 + +0000000010000[0-9a-f]{3} <\.no_opt3>: 1263 + + 10000[0-9a-f]{3}: 38 62 80 08 addi r3,r2,-32760 1264 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1265 + + 10000[0-9a-f]{3}: 38 62 80 18 addi r3,r2,-32744 1266 + + 10000[0-9a-f]{3}: 48 00 00 10 b .* 1267 + + 10000[0-9a-f]{3}: 4b ff ff ed bl 10000[0-9a-f]{3} <\.__tls_get_addr> 1268 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1269 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1270 + + 10000[0-9a-f]{3}: 4b ff ff e1 bl 10000[0-9a-f]{3} <\.__tls_get_addr> 1271 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1272 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt3_32.d 1273 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt3_32.d 1274 + @@ -9,17 +9,17 @@ 1275 + 1276 + Disassembly of section \.text: 1277 + 1278 + -0+1800094 <__tls_get_addr>: 1279 + - 1800094: 4e 80 00 20 blr 1280 + +0+18000[0-9a-f]{2} <__tls_get_addr>: 1281 + + 18000[0-9a-f]{2}: 4e 80 00 20 blr 1282 + 1283 + Disassembly of section \.no_opt3: 1284 + 1285 + -0+1800098 <\.no_opt3>: 1286 + - 1800098: 38 6d ff ec addi r3,r13,-20 1287 + - 180009c: 48 00 00 0c b .* 1288 + - 18000a0: 38 6d ff f4 addi r3,r13,-12 1289 + - 18000a4: 48 00 00 0c b .* 1290 + - 18000a8: 4b ff ff ed bl 1800094 <__tls_get_addr> 1291 + - 18000ac: 48 00 00 08 b .* 1292 + - 18000b0: 4b ff ff e5 bl 1800094 <__tls_get_addr> 1293 + +0+18000[0-9a-f]{2} <\.no_opt3>: 1294 + + 18000[0-9a-f]{2}: 38 6d ff ec addi r3,r13,-20 1295 + + 18000[0-9a-f]{2}: 48 00 00 0c b .* 1296 + + 18000[0-9a-f]{2}: 38 6d ff f4 addi r3,r13,-12 1297 + + 18000[0-9a-f]{2}: 48 00 00 0c b .* 1298 + + 18000[0-9a-f]{2}: 4b ff ff ed bl 18000[0-9a-f]{2} <__tls_get_addr> 1299 + + 18000[0-9a-f]{2}: 48 00 00 08 b .* 1300 + + 18000[0-9a-f]{2}: 4b ff ff e5 bl 18000[0-9a-f]{2} <__tls_get_addr> 1301 + #pass 1302 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt4.d 1303 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt4.d 1304 + @@ -9,40 +9,40 @@ 1305 + 1306 + Disassembly of section \.text: 1307 + 1308 + -0+100000e8 <\.__tls_get_addr>: 1309 + - 100000e8: 4e 80 00 20 blr 1310 + +0+10000[0-9a-f]{3} <\.__tls_get_addr>: 1311 + + 10000[0-9a-f]{3}: 4e 80 00 20 blr 1312 + 1313 + Disassembly of section \.opt1: 1314 + 1315 + -0+100000ec <\.opt1>: 1316 + - 100000ec: 3c 6d 00 00 addis r3,r13,0 1317 + - 100000f0: 2c 24 00 00 cmpdi r4,0 1318 + - 100000f4: 41 82 00 10 beq- .* 1319 + - 100000f8: 60 00 00 00 nop 1320 + - 100000fc: 38 63 90 10 addi r3,r3,-28656 1321 + - 10000100: 48 00 00 0c b .* 1322 + - 10000104: 60 00 00 00 nop 1323 + - 10000108: 38 63 90 10 addi r3,r3,-28656 1324 + +0+10000[0-9a-f]{3} <\.opt1>: 1325 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1326 + + 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0 1327 + + 10000[0-9a-f]{3}: 41 82 00 10 beq- .* 1328 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1329 + + 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656 1330 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1331 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1332 + + 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656 1333 + 1334 + Disassembly of section \.opt2: 1335 + 1336 + -0+1000010c <\.opt2>: 1337 + - 1000010c: 3c 6d 00 00 addis r3,r13,0 1338 + - 10000110: 2c 24 00 00 cmpdi r4,0 1339 + - 10000114: 41 82 00 08 beq- .* 1340 + - 10000118: 3c 6d 00 00 addis r3,r13,0 1341 + - 1000011c: 60 00 00 00 nop 1342 + - 10000120: 38 63 90 10 addi r3,r3,-28656 1343 + +0+10000[0-9a-f]{3} <\.opt2>: 1344 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1345 + + 10000[0-9a-f]{3}: 2c 24 00 00 cmpdi r4,0 1346 + + 10000[0-9a-f]{3}: 41 82 00 08 beq- .* 1347 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1348 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1349 + + 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656 1350 + 1351 + Disassembly of section \.opt3: 1352 + 1353 + -0+10000124 <\.opt3>: 1354 + - 10000124: 3c 6d 00 00 addis r3,r13,0 1355 + - 10000128: 48 00 00 0c b .* 1356 + - 1000012c: 3c 6d 00 00 addis r3,r13,0 1357 + - 10000130: 48 00 00 10 b .* 1358 + - 10000134: 60 00 00 00 nop 1359 + - 10000138: 38 63 90 10 addi r3,r3,-28656 1360 + - 1000013c: 48 00 00 0c b .* 1361 + - 10000140: 60 00 00 00 nop 1362 + - 10000144: 38 63 90 08 addi r3,r3,-28664 1363 + +0+10000[0-9a-f]{3} <\.opt3>: 1364 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1365 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1366 + + 10000[0-9a-f]{3}: 3c 6d 00 00 addis r3,r13,0 1367 + + 10000[0-9a-f]{3}: 48 00 00 10 b .* 1368 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1369 + + 10000[0-9a-f]{3}: 38 63 90 10 addi r3,r3,-28656 1370 + + 10000[0-9a-f]{3}: 48 00 00 0c b .* 1371 + + 10000[0-9a-f]{3}: 60 00 00 00 nop 1372 + + 10000[0-9a-f]{3}: 38 63 90 08 addi r3,r3,-28664 1373 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsopt4_32.d 1374 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsopt4_32.d 1375 + @@ -9,36 +9,36 @@ 1376 + 1377 + Disassembly of section \.text: 1378 + 1379 + -0+1800094 <__tls_get_addr>: 1380 + - 1800094: 4e 80 00 20 blr 1381 + +0+18000[0-9a-f]{2} <__tls_get_addr>: 1382 + + 18000[0-9a-f]{2}: 4e 80 00 20 blr 1383 + 1384 + Disassembly of section \.opt1: 1385 + 1386 + -0+1800098 <\.opt1>: 1387 + - 1800098: 3c 62 00 00 addis r3,r2,0 1388 + - 180009c: 2c 04 00 00 cmpwi r4,0 1389 + - 18000a0: 41 82 00 0c beq- .* 1390 + - 18000a4: 38 63 90 10 addi r3,r3,-28656 1391 + - 18000a8: 48 00 00 08 b .* 1392 + - 18000ac: 38 63 90 10 addi r3,r3,-28656 1393 + +0+18000[0-9a-f]{2} <\.opt1>: 1394 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1395 + + 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0 1396 + + 18000[0-9a-f]{2}: 41 82 00 0c beq- .* 1397 + + 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656 1398 + + 18000[0-9a-f]{2}: 48 00 00 08 b .* 1399 + + 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656 1400 + 1401 + Disassembly of section \.opt2: 1402 + 1403 + -0+18000b0 <\.opt2>: 1404 + - 18000b0: 3c 62 00 00 addis r3,r2,0 1405 + - 18000b4: 2c 04 00 00 cmpwi r4,0 1406 + - 18000b8: 41 82 00 08 beq- .* 1407 + - 18000bc: 3c 62 00 00 addis r3,r2,0 1408 + - 18000c0: 38 63 90 10 addi r3,r3,-28656 1409 + +0+18000[0-9a-f]{2} <\.opt2>: 1410 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1411 + + 18000[0-9a-f]{2}: 2c 04 00 00 cmpwi r4,0 1412 + + 18000[0-9a-f]{2}: 41 82 00 08 beq- .* 1413 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1414 + + 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656 1415 + 1416 + Disassembly of section \.opt3: 1417 + 1418 + -0+18000c4 <\.opt3>: 1419 + - 18000c4: 3c 62 00 00 addis r3,r2,0 1420 + - 18000c8: 48 00 00 0c b .* 1421 + - 18000cc: 3c 62 00 00 addis r3,r2,0 1422 + - 18000d0: 48 00 00 0c b .* 1423 + - 18000d4: 38 63 90 10 addi r3,r3,-28656 1424 + - 18000d8: 48 00 00 08 b .* 1425 + - 18000dc: 38 63 90 08 addi r3,r3,-28664 1426 + +0+18000[0-9a-f]{2} <\.opt3>: 1427 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1428 + + 18000[0-9a-f]{2}: 48 00 00 0c b .* 1429 + + 18000[0-9a-f]{2}: 3c 62 00 00 addis r3,r2,0 1430 + + 18000[0-9a-f]{2}: 48 00 00 0c b .* 1431 + + 18000[0-9a-f]{2}: 38 63 90 10 addi r3,r3,-28656 1432 + + 18000[0-9a-f]{2}: 48 00 00 08 b .* 1433 + + 18000[0-9a-f]{2}: 38 63 90 08 addi r3,r3,-28664 1434 + #pass 1435 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.d 1436 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.d 1437 + @@ -42,5 +42,5 @@ Disassembly of section \.got: 1438 + #... 1439 + .*: 4e 80 00 21 blrl 1440 + .* <_GLOBAL_OFFSET_TABLE_>: 1441 + -.*: 00 01 03 ec .* 1442 + +.*: 00 01 [0-9a-f]{2} [0-9a-f]{2} .* 1443 + #pass 1444 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.g 1445 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.g 1446 + @@ -9,5 +9,5 @@ 1447 + Contents of section \.got: 1448 + .* 00000000 00000000 00000000 00000000 .* 1449 + .* 00000000 00000000 00000000 00000000 .* 1450 + -.* 00000000 4e800021 000103ec 00000000 .* 1451 + +.* 00000000 4e800021 00010[0-9a-f]{3} 00000000 .* 1452 + .* 00000000 .* 1453 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.r 1454 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlsso32.r 1455 + @@ -35,6 +35,7 @@ Program Headers: 1456 + +LOAD .* RWE 0x10000 1457 + +DYNAMIC .* RW +0x4 1458 + +TLS .* 0x0+1c 0x0+38 R +0x4 1459 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1460 + 1461 + Section to Segment mapping: 1462 + +Segment Sections\.\.\. 1463 + @@ -42,6 +43,7 @@ Program Headers: 1464 + +01 +\.tdata \.dynamic \.got \.plt 1465 + +02 +\.dynamic 1466 + +03 +\.tdata \.tbss 1467 + + +04 + 1468 + 1469 + Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries: 1470 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend 1471 + @@ -52,9 +54,9 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries: 1472 + [0-9a-f ]+R_PPC_TPREL16 +0+30 +le0 \+ 0 1473 + [0-9a-f ]+R_PPC_TPREL16_HA +0+34 +le1 \+ 0 1474 + [0-9a-f ]+R_PPC_TPREL16_LO +0+34 +le1 \+ 0 1475 + -[0-9a-f ]+R_PPC_TPREL16 +0+103d0 +\.tdata \+ 103e4 1476 + -[0-9a-f ]+R_PPC_TPREL16_HA +0+103d0 +\.tdata \+ 103e8 1477 + -[0-9a-f ]+R_PPC_TPREL16_LO +0+103d0 +\.tdata \+ 103e8 1478 + +[0-9a-f ]+R_PPC_TPREL16 +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3} 1479 + +[0-9a-f ]+R_PPC_TPREL16_HA +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3} 1480 + +[0-9a-f ]+R_PPC_TPREL16_LO +0+103[df]0 +\.tdata \+ 10[0-9a-f]{3} 1481 + [0-9a-f ]+R_PPC_DTPMOD32 +0 1482 + [0-9a-f ]+R_PPC_DTPREL32 +0 1483 + [0-9a-f ]+R_PPC_DTPMOD32 +0 1484 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlstoc.g 1485 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlstoc.g 1486 + @@ -8,8 +8,8 @@ 1487 + .*: +file format elf64-powerpc 1488 + 1489 + Contents of section \.got: 1490 + - 100101a0 00000000 00000001 00000000 00000000 .* 1491 + - 100101b0 00000000 00000001 00000000 00000000 .* 1492 + - 100101c0 00000000 00000001 00000000 00000000 .* 1493 + - 100101d0 00000000 00000001 00000000 00000000 .* 1494 + - 100101e0 ffffffff ffff8060 00000000 00000000 .* 1495 + + 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .* 1496 + + 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .* 1497 + + 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .* 1498 + + 10010[0-9a-f]{3} 00000000 00000001 00000000 00000000 .* 1499 + + 10010[0-9a-f]{3} ffffffff ffff8060 00000000 00000000 .* 1500 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlstoc.t 1501 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlstoc.t 1502 + @@ -8,7 +8,7 @@ 1503 + .*: +file format elf64-powerpc 1504 + 1505 + Contents of section \.tdata: 1506 + - 10010148 00c0ffee 00000000 12345678 9abcdef0 .* 1507 + - 10010158 23456789 abcdef01 3456789a bcdef012 .* 1508 + - 10010168 456789ab cdef0123 56789abc def01234 .* 1509 + - 10010178 6789abcd ef012345 789abcde f0123456 .* 1510 + + 10010180 00c0ffee 00000000 12345678 9abcdef0 .* 1511 + + 10010190 23456789 abcdef01 3456789a bcdef012 .* 1512 + + 100101a0 456789ab cdef0123 56789abc def01234 .* 1513 + + 100101b0 6789abcd ef012345 789abcde f0123456 .* 1514 + --- binutils-2.23/ld/testsuite/ld-powerpc/tlstocso.g 1515 + +++ binutils-2.23/ld/testsuite/ld-powerpc/tlstocso.g 1516 + @@ -7,7 +7,7 @@ 1517 + .*: +file format elf64-powerpc 1518 + 1519 + Contents of section \.got: 1520 + -.* 00000000 000186c0 00000000 00000000 .* 1521 + +.* 00000000 000186f8 00000000 00000000 .* 1522 + .* 00000000 00000000 00000000 00000000 .* 1523 + .* 00000000 00000000 00000000 00000000 .* 1524 + .* 00000000 00000000 00000000 00000000 .* 1525 + --- binutils-2.23/ld/testsuite/ld-s390/tlsbin.rd 1526 + +++ binutils-2.23/ld/testsuite/ld-s390/tlsbin.rd 1527 + @@ -36,6 +36,7 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 1528 + +LOAD .* RW +0x1000 1529 + +DYNAMIC .* RW +0x4 1530 + +TLS .* 0x0+60 0x0+a0 R +0x20 1531 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1532 + 1533 + Section to Segment mapping: 1534 + +Segment Sections... 1535 + @@ -52,6 +53,7 @@ Program Headers: 1536 + +03 +.tdata .dynamic .got * 1537 + +04 +.dynamic * 1538 + +05 +.tdata .tbss * 1539 + + +06 + 1540 + 1541 + Relocation section '.rela.dyn' at offset .* contains 4 entries: 1542 + Offset +Info +Type +Sym.Value +Sym. Name \+ Addend 1543 + --- binutils-2.23/ld/testsuite/ld-s390/tlsbin_64.rd 1544 + +++ binutils-2.23/ld/testsuite/ld-s390/tlsbin_64.rd 1545 + @@ -36,6 +36,7 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 1546 + +LOAD .* RW +0x1000 1547 + +DYNAMIC .* RW +0x8 1548 + +TLS .* 0x0+60 0x0+a0 R +0x20 1549 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1550 + 1551 + Section to Segment mapping: 1552 + +Segment Sections... 1553 + @@ -52,6 +53,7 @@ Program Headers: 1554 + +03 +.tdata .dynamic .got * 1555 + +04 +.dynamic * 1556 + +05 +.tdata .tbss * 1557 + + +06 + 1558 + 1559 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries: 1560 + +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend 1561 + --- binutils-2.23/ld/testsuite/ld-s390/tlspic.rd 1562 + +++ binutils-2.23/ld/testsuite/ld-s390/tlspic.rd 1563 + @@ -39,6 +39,7 @@ Program Headers: 1564 + +LOAD .* RW +0x1000 1565 + +DYNAMIC .* RW +0x4 1566 + +TLS .* 0x0+60 0x0+80 R +0x20 1567 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1568 + 1569 + Section to Segment mapping: 1570 + +Segment Sections... 1571 + @@ -46,6 +47,7 @@ Program Headers: 1572 + +01 +.tdata .dynamic .got 1573 + +02 +.dynamic 1574 + +03 +.tdata .tbss 1575 + + +04 + 1576 + 1577 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1578 + Offset +Info +Type +Sym.Value +Sym. Name \+ Addend 1579 + --- binutils-2.23/ld/testsuite/ld-s390/tlspic_64.rd 1580 + +++ binutils-2.23/ld/testsuite/ld-s390/tlspic_64.rd 1581 + @@ -39,6 +39,7 @@ Program Headers: 1582 + +LOAD .* RW +0x1000 1583 + +DYNAMIC .* RW +0x8 1584 + +TLS .* 0x0+60 0x0+80 R +0x20 1585 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1586 + 1587 + Section to Segment mapping: 1588 + +Segment Sections... 1589 + @@ -46,6 +47,7 @@ Program Headers: 1590 + +01 +.tdata .dynamic .got * 1591 + +02 +.dynamic * 1592 + +03 +.tdata .tbss * 1593 + + +04 + 1594 + 1595 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1596 + +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend 1597 + --- binutils-2.23/ld/testsuite/ld-scripts/empty-aligned.d 1598 + +++ binutils-2.23/ld/testsuite/ld-scripts/empty-aligned.d 1599 + @@ -8,7 +8,9 @@ 1600 + Program Headers: 1601 + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align 1602 + +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ [RWE ]+ +0x[0-9a-f]+ 1603 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1604 + 1605 + Section to Segment mapping: 1606 + +Segment Sections\.\.\. 1607 + +00 +.text 1608 + + +01 + 1609 + --- binutils-2.23/ld/testsuite/ld-sh/tlsbin-2.d 1610 + +++ binutils-2.23/ld/testsuite/ld-sh/tlsbin-2.d 1611 + @@ -44,6 +44,7 @@ Program Headers: 1612 + +LOAD.* 1613 + +DYNAMIC.* 1614 + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+18 0x0+28 R +0x4 1615 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1616 + 1617 + Section to Segment mapping: 1618 + +Segment Sections\.\.\. 1619 + @@ -53,6 +54,7 @@ Program Headers: 1620 + +03 +\.tdata \.dynamic \.got * 1621 + +04 +\.dynamic * 1622 + +05 +\.tdata \.tbss * 1623 + + +06 + 1624 + 1625 + Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries: 1626 + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend 1627 + --- binutils-2.23/ld/testsuite/ld-sh/tlspic-2.d 1628 + +++ binutils-2.23/ld/testsuite/ld-sh/tlspic-2.d 1629 + @@ -32,7 +32,7 @@ Key to Flags: 1630 + 1631 + Elf file type is DYN \(Shared object file\) 1632 + Entry point 0x[0-9a-f]+ 1633 + -There are 4 program headers, starting at offset [0-9]+ 1634 + +There are [0-9] program headers, starting at offset [0-9]+ 1635 + 1636 + Program Headers: 1637 + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align 1638 + @@ -40,6 +40,7 @@ Program Headers: 1639 + +LOAD.* 1640 + +DYNAMIC.* 1641 + +TLS .* 0x0+18 0x0+20 R +0x4 1642 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1643 + 1644 + Section to Segment mapping: 1645 + +Segment Sections\.\.\. 1646 + @@ -47,6 +48,7 @@ Program Headers: 1647 + +01 +\.tdata \.dynamic \.got * 1648 + +02 +\.dynamic * 1649 + +03 +\.tdata \.tbss * 1650 + + +04 + 1651 + 1652 + Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 10 entries: 1653 + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend 1654 + --- binutils-2.23/ld/testsuite/ld-sparc/gotop32.rd 1655 + +++ binutils-2.23/ld/testsuite/ld-sparc/gotop32.rd 1656 + @@ -31,6 +31,7 @@ Program Headers: 1657 + +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x10000 1658 + +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+2000 0x0+2000 RW +0x10000 1659 + +DYNAMIC +0x0+2000 0x0+12000 0x0+12000 0x0+70 0x0+70 RW +0x4 1660 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1661 + #... 1662 + 1663 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries: 1664 + --- binutils-2.23/ld/testsuite/ld-sparc/gotop64.rd 1665 + +++ binutils-2.23/ld/testsuite/ld-sparc/gotop64.rd 1666 + @@ -31,6 +31,7 @@ Program Headers: 1667 + +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x100000 1668 + +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+2000 0x0+2000 RW +0x100000 1669 + +DYNAMIC +0x0+2000 0x0+102000 0x0+102000 0x0+e0 0x0+e0 RW +0x8 1670 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1671 + #... 1672 + 1673 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries: 1674 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunbin32.rd 1675 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunbin32.rd 1676 + @@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 1677 + 1678 + Program Headers: 1679 + +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align 1680 + - +PHDR +0x0+34 0x0+10034 0x0+10034 0x0+c0 0x0+c0 R E 0x4 1681 + - +INTERP +0x0+f4 0x0+100f4 0x0+100f4 0x0+11 0x0+11 R +0x1 1682 + + +PHDR +0x0+34 0x0+10034 0x0+10034 (0x[0-9a-f]+) \1 R E 0x4 1683 + + +INTERP +(0x[0-9a-f]+ ){3}0x0+11 0x0+11 R +0x1 1684 + .*Requesting program interpreter.* 1685 + +LOAD .* R E 0x10000 1686 + +LOAD .* RW +0x10000 1687 + +DYNAMIC .* RW +0x4 1688 + +TLS .* 0x0+1060 0x0+10a0 R +0x4 1689 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1690 + #... 1691 + 1692 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries: 1693 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunbin64.rd 1694 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunbin64.rd 1695 + @@ -30,13 +30,14 @@ There are [0-9]+ program headers, starting at offset [0-9]+ 1696 + 1697 + Program Headers: 1698 + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align 1699 + - +PHDR +0x0+40 0x0+100040 0x0+100040 0x0+150 0x0+150 R E 0x8 1700 + - +INTERP +0x0+190 0x0+100190 0x0+100190 0x0+19 0x0+19 R +0x1 1701 + + +PHDR +0x0+40 0x0+100040 0x0+100040 (0x[0-9a-f]+) \1 R E 0x8 1702 + + +INTERP +0x0+([0-9a-f]+) (0x0+10+\1) \2 0x0+19 0x0+19 R +0x1 1703 + .*Requesting program interpreter.* 1704 + +LOAD .* R E 0x100000 1705 + +LOAD .* RW +0x100000 1706 + +DYNAMIC .* RW +0x8 1707 + +TLS .* 0x0+60 0x0+a0 R +0x4 1708 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1709 + #... 1710 + 1711 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries: 1712 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunnopic32.rd 1713 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunnopic32.rd 1714 + @@ -32,6 +32,7 @@ Program Headers: 1715 + +LOAD .* RW +0x10000 1716 + +DYNAMIC .* RW +0x4 1717 + +TLS .* 0x0+ 0x0+24 R +0x4 1718 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1719 + #... 1720 + 1721 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 12 entries: 1722 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunnopic64.rd 1723 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunnopic64.rd 1724 + @@ -32,6 +32,7 @@ Program Headers: 1725 + +LOAD .* RW +0x100000 1726 + +DYNAMIC .* RW +0x8 1727 + +TLS .* 0x0+ 0x0+24 R +0x4 1728 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1729 + #... 1730 + 1731 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1732 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunpic32.rd 1733 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunpic32.rd 1734 + @@ -36,6 +36,7 @@ Program Headers: 1735 + +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+184 0x0+184 RWE 0x10000 1736 + +DYNAMIC +0x0+2060 0x0+12060 0x0+12060 0x0+98 0x0+98 RW +0x4 1737 + +TLS +0x0+2000 0x0+12000 0x0+12000 0x0+60 0x0+80 R +0x4 1738 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1739 + #... 1740 + 1741 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1742 + --- binutils-2.23/ld/testsuite/ld-sparc/tlssunpic64.rd 1743 + +++ binutils-2.23/ld/testsuite/ld-sparc/tlssunpic64.rd 1744 + @@ -36,6 +36,7 @@ Program Headers: 1745 + +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+3a0 0x0+3a0 RWE 0x100000 1746 + +DYNAMIC +0x0+2060 0x0+102060 0x0+102060 0x0+130 0x0+130 RW +0x8 1747 + +TLS +0x0+2000 0x0+102000 0x0+102000 0x0+60 0x0+80 R +0x4 1748 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1749 + #... 1750 + 1751 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1752 + --- binutils-2.23/ld/testsuite/ld-x86-64/tlsgdesc.rd 1753 + +++ binutils-2.23/ld/testsuite/ld-x86-64/tlsgdesc.rd 1754 + @@ -36,12 +36,14 @@ Program Headers: 1755 + +LOAD.* 1756 + +LOAD.* 1757 + +DYNAMIC.* 1758 + + +PAX_FLAGS.* 1759 + 1760 + Section to Segment mapping: 1761 + +Segment Sections... 1762 + +00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text * 1763 + +01 +.dynamic .got .got.plt * 1764 + +02 +.dynamic * 1765 + + +03 + 1766 + 1767 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 8 entries: 1768 + +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend 1769 + --- binutils-2.23/ld/testsuite/ld-x86-64/tlspic.rd 1770 + +++ binutils-2.23/ld/testsuite/ld-x86-64/tlspic.rd 1771 + @@ -40,6 +40,7 @@ Program Headers: 1772 + +LOAD +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+244 0x0+244 RW +0x200000 1773 + +DYNAMIC +0x0+1210 0x0+201210 0x0+201210 0x0+130 0x0+130 RW +0x8 1774 + +TLS +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+60 0x0+80 R +0x1 1775 + + +PAX_FLAGS +0x0+ 0x0+ 0x0+ 0x0+ 0x0+ +0x[48] 1776 + 1777 + Section to Segment mapping: 1778 + +Segment Sections... 1779 + @@ -47,6 +48,7 @@ Program Headers: 1780 + +01 +.tdata .dynamic .got .got.plt * 1781 + +02 +.dynamic * 1782 + +03 +.tdata .tbss * 1783 + + +04 + 1784 + 1785 + Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries: 1786 + +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend